ARM: 6078/1: ux500: add per-SoC register definitions
Split up all the hardware register definitions previously found in hardware.h into per-SoC files db8500-regs.h and db5500-regs.h. Rename a couple of macros to prepare for sharing code between the variants. Acked-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Rabin Vincent
Russell King
parent
f38406bbfc
commit
c9c0957286
4 changed files with 289 additions and 103 deletions
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@ -124,10 +124,10 @@ static struct map_desc u8500_io_desc[] __initdata = {
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__IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_GPIO5_BASE, SZ_4K),
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__IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K),
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};
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@ -137,7 +137,7 @@ static struct map_desc u8500ed_io_desc[] __initdata = {
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};
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static struct map_desc u8500v1_io_desc[] __initdata = {
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__IO_DEV_DESC(U8500_MTU0_BASE_V1, SZ_4K),
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__IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
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};
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void __init u8500_map_io(void)
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@ -177,7 +177,7 @@ static void __init u8500_timer_init(void)
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if (cpu_is_u8500ed())
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mtu_base = __io_address(U8500_MTU0_BASE_ED);
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else
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mtu_base = __io_address(U8500_MTU0_BASE_V1);
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mtu_base = __io_address(U8500_MTU0_BASE);
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nmdk_timer_init();
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}
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103
arch/arm/mach-ux500/include/mach/db5500-regs.h
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103
arch/arm/mach-ux500/include/mach/db5500-regs.h
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@ -0,0 +1,103 @@
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/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* License terms: GNU General Public License (GPL) version 2
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*/
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#ifndef __MACH_DB5500_REGS_H
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#define __MACH_DB5500_REGS_H
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#define U5500_PER1_BASE 0xA0020000
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#define U5500_PER2_BASE 0xA0010000
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#define U5500_PER3_BASE 0x80140000
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#define U5500_PER4_BASE 0x80150000
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#define U5500_PER5_BASE 0x80100000
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#define U5500_PER6_BASE 0x80120000
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#define U5500_GIC_DIST_BASE 0xA0411000
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#define U5500_GIC_CPU_BASE 0xA0410100
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#define U5500_DMA_BASE 0x90030000
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#define U5500_MCDE_BASE 0xA0400000
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#define U5500_MODEM_BASE 0xB0000000
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#define U5500_L2CC_BASE 0xA0412000
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#define U5500_SCU_BASE 0xA0410000
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#define U5500_DSI1_BASE 0xA0401000
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#define U5500_DSI2_BASE 0xA0402000
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#define U5500_SIA_BASE 0xA0100000
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#define U5500_SVA_BASE 0x80200000
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#define U5500_HSEM_BASE 0xA0000000
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#define U5500_NAND0_BASE 0x60000000
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#define U5500_NAND1_BASE 0x70000000
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#define U5500_TWD_BASE 0xa0410600
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#define U5500_B2R2_BASE 0xa0200000
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#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000)
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#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000)
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#define U5500_SDI2_BASE (U5500_PER1_BASE + 0x2000)
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#define U5500_UART0_BASE (U5500_PER1_BASE + 0x3000)
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#define U5500_I2C1_BASE (U5500_PER1_BASE + 0x4000)
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#define U5500_MSP0_BASE (U5500_PER1_BASE + 0x5000)
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#define U5500_GPIO0_BASE (U5500_PER1_BASE + 0xE000)
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#define U5500_CLKRST1_BASE (U5500_PER1_BASE + 0xF000)
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#define U5500_USBOTG_BASE (U5500_PER2_BASE + 0x0000)
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#define U5500_GPIO1_BASE (U5500_PER2_BASE + 0xE000)
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#define U5500_CLKRST2_BASE (U5500_PER2_BASE + 0xF000)
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#define U5500_KEYPAD_BASE (U5500_PER3_BASE + 0x0000)
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#define U5500_PWM_BASE (U5500_PER3_BASE + 0x1000)
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#define U5500_GPIO3_BASE (U5500_PER3_BASE + 0xE000)
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#define U5500_CLKRST3_BASE (U5500_PER3_BASE + 0xF000)
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#define U5500_BACKUPRAM0_BASE (U5500_PER4_BASE + 0x0000)
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#define U5500_BACKUPRAM1_BASE (U5500_PER4_BASE + 0x1000)
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#define U5500_RTT0_BASE (U5500_PER4_BASE + 0x2000)
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#define U5500_RTT1_BASE (U5500_PER4_BASE + 0x3000)
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#define U5500_RTC_BASE (U5500_PER4_BASE + 0x4000)
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#define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000)
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#define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000)
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#define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000)
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#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000)
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#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000)
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#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000)
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#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000)
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#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000)
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#define U5500_SPI2_BASE (U5500_PER5_BASE + 0x2000)
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#define U5500_SPI3_BASE (U5500_PER5_BASE + 0x3000)
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#define U5500_UART1_BASE (U5500_PER5_BASE + 0x4000)
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#define U5500_UART2_BASE (U5500_PER5_BASE + 0x5000)
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#define U5500_UART3_BASE (U5500_PER5_BASE + 0x6000)
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#define U5500_SDI1_BASE (U5500_PER5_BASE + 0x7000)
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#define U5500_SDI3_BASE (U5500_PER5_BASE + 0x8000)
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#define U5500_SDI4_BASE (U5500_PER5_BASE + 0x9000)
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#define U5500_I2C2_BASE (U5500_PER5_BASE + 0xA000)
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#define U5500_I2C3_BASE (U5500_PER5_BASE + 0xB000)
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#define U5500_MSP2_BASE (U5500_PER5_BASE + 0xC000)
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#define U5500_IRDA_BASE (U5500_PER5_BASE + 0xD000)
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#define U5500_IRRC_BASE (U5500_PER5_BASE + 0x10000)
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#define U5500_GPIO4_BASE (U5500_PER5_BASE + 0x1E000)
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#define U5500_CLKRST5_BASE (U5500_PER5_BASE + 0x1F000)
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#define U5500_RNG_BASE (U5500_PER6_BASE + 0x0000)
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#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000)
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#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000)
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#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000)
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#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5000)
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#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000)
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#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000)
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#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000)
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#define U5500_CRYP0_BASE (U5500_PER6_BASE + 0xA000)
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#define U5500_CRYP1_BASE (U5500_PER6_BASE + 0xB000)
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#define U5500_CLKRST6_BASE (U5500_PER6_BASE + 0xF000)
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#define U5500_GPIOBANK0_BASE U5500_GPIO0_BASE
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#define U5500_GPIOBANK1_BASE (U5500_GPIO0_BASE + 0x80)
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#define U5500_GPIOBANK2_BASE U5500_GPIO1_BASE
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#define U5500_GPIOBANK3_BASE U5500_GPIO2_BASE
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#define U5500_GPIOBANK4_BASE U5500_GPIO3_BASE
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#define U5500_GPIOBANK5_BASE U5500_GPIO4_BASE
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#define U5500_GPIOBANK6_BASE (U5500_GPIO4_BASE + 0x80)
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#define U5500_GPIOBANK7_BASE (U5500_GPIO4_BASE + 0x100)
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#endif
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135
arch/arm/mach-ux500/include/mach/db8500-regs.h
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135
arch/arm/mach-ux500/include/mach/db8500-regs.h
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@ -0,0 +1,135 @@
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/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* License terms: GNU General Public License (GPL) version 2
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*/
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#ifndef __MACH_DB8500_REGS_H
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#define __MACH_DB8500_REGS_H
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#define U8500_PER3_BASE 0x80000000
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#define U8500_STM_BASE 0x80100000
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#define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
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#define U8500_PER2_BASE 0x80110000
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#define U8500_PER1_BASE 0x80120000
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#define U8500_B2R2_BASE 0x80130000
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#define U8500_HSEM_BASE 0x80140000
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#define U8500_PER4_BASE 0x80150000
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#define U8500_ICN_BASE 0x81000000
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#define U8500_BOOT_ROM_BASE 0x90000000
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/* ASIC ID is at 0xff4 offset within this region */
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#define U8500_ASIC_ID_BASE 0x9001F000
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#define U8500_PER6_BASE 0xa03c0000
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#define U8500_PER5_BASE 0xa03e0000
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#define U8500_PER7_BASE_ED 0xa03d0000
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#define U8500_SVA_BASE 0xa0100000
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#define U8500_SIA_BASE 0xa0200000
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#define U8500_SGA_BASE 0xa0300000
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#define U8500_MCDE_BASE 0xa0350000
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#define U8500_DMA_BASE_ED 0xa0362000
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#define U8500_DMA_BASE 0x801C0000 /* v1 */
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#define U8500_SBAG_BASE 0xa0390000
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#define U8500_SCU_BASE 0xa0410000
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#define U8500_GIC_CPU_BASE 0xa0410100
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#define U8500_TWD_BASE 0xa0410600
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#define U8500_GIC_DIST_BASE 0xa0411000
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#define U8500_L2CC_BASE 0xa0412000
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#define U8500_MODEM_I2C 0xb7e02000
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#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000)
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#define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000)
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#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000)
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#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000)
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/* per7 base addressess */
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#define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000)
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#define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000)
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#define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000)
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#define U8500_TZPC0_BASE_ED (U8500_PER7_BASE_ED + 0xc000)
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#define U8500_CLKRST7_BASE_ED (U8500_PER7_BASE_ED + 0xf000)
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#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
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#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
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/* per6 base addressess */
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#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
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#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000)
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#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000)
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#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */
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#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */
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#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */
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#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000)
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#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000)
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#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
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/* per5 base addressess */
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#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
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#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
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/* per4 base addressess */
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#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000)
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#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000)
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#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000)
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#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000)
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#define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000)
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#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000)
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#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000)
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#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
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#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000)
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/* per3 base addresses */
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#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
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#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
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#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
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#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
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#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
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#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
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#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
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#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
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#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
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/* per2 base addressess */
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#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
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#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
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#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
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#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
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#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
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#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
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#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
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#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
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#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
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#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
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#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
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#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
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/* per1 base addresses */
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#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
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#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
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#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
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#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
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#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
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#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
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#define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000)
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#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000)
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#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
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#define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040
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#define U8500_GPIOBANK0_BASE U8500_GPIO0_BASE
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#define U8500_GPIOBANK1_BASE (U8500_GPIO0_BASE + 0x80)
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#define U8500_GPIOBANK2_BASE U8500_GPIO1_BASE
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#define U8500_GPIOBANK3_BASE (U8500_GPIO1_BASE + 0x80)
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#define U8500_GPIOBANK4_BASE (U8500_GPIO1_BASE + 0x100)
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#define U8500_GPIOBANK5_BASE (U8500_GPIO1_BASE + 0x180)
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#define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE
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#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80)
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#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE
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#endif
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@ -26,119 +26,67 @@
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/* used by some plat-nomadik code */
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#define io_p2v(n) __io_address(n)
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/*
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* Base address definitions for U8500 Onchip IPs. All the
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* peripherals are contained in a single 1 Mbyte region, with
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* AHB peripherals at the bottom and APB peripherals at the
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* top of the region. PER stands for PERIPHERAL region which
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* itself divided into sub regions.
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*/
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#define U8500_PER3_BASE 0x80000000
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#define U8500_PER2_BASE 0x80110000
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#define U8500_PER1_BASE 0x80120000
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#define U8500_PER4_BASE 0x80150000
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#include <mach/db8500-regs.h>
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#include <mach/db5500-regs.h>
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#define U8500_PER6_BASE 0xa03c0000
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#define U8500_PER5_BASE 0xa03e0000
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#define U8500_PER7_BASE 0xa03d0000
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#ifdef CONFIG_UX500_SOC_DB8500
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#define UX500(periph) U8500_##periph##_BASE
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#elif defined(CONFIG_UX500_SOC_DB5500)
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#define UX500(periph) U5500_##periph##_BASE
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#endif
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#define U8500_SVA_BASE 0xa0100000
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#define U8500_SIA_BASE 0xa0200000
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#define UX500_BACKUPRAM0_BASE UX500(BACKUPRAM0)
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#define UX500_BACKUPRAM1_BASE UX500(BACKUPRAM1)
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#define UX500_B2R2_BASE UX500(B2R2)
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#define U8500_SGA_BASE 0xa0300000
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#define U8500_MCDE_BASE 0xa0350000
|
||||
#define U8500_DMA_BASE 0xa0362000
|
||||
#define UX500_CLKRST1_BASE UX500(CLKRST1)
|
||||
#define UX500_CLKRST2_BASE UX500(CLKRST2)
|
||||
#define UX500_CLKRST3_BASE UX500(CLKRST3)
|
||||
#define UX500_CLKRST5_BASE UX500(CLKRST5)
|
||||
#define UX500_CLKRST6_BASE UX500(CLKRST6)
|
||||
|
||||
#define U8500_SCU_BASE 0xa0410000
|
||||
#define U8500_GIC_CPU_BASE 0xa0410100
|
||||
#define U8500_TWD_BASE 0xa0410600
|
||||
#define U8500_GIC_DIST_BASE 0xa0411000
|
||||
#define U8500_L2CC_BASE 0xa0412000
|
||||
#define UX500_DMA_BASE UX500(DMA)
|
||||
#define UX500_FSMC_BASE UX500(FSMC)
|
||||
|
||||
#define U8500_TWD_SIZE 0x100
|
||||
#define UX500_GIC_CPU_BASE UX500(GIC_CPU)
|
||||
#define UX500_GIC_DIST_BASE UX500(GIC_DIST)
|
||||
|
||||
/* per7 base addressess */
|
||||
#define U8500_CR_BASE_ED (U8500_PER7_BASE + 0x8000)
|
||||
#define U8500_MTU0_BASE_ED (U8500_PER7_BASE + 0xa000)
|
||||
#define U8500_MTU1_BASE_ED (U8500_PER7_BASE + 0xb000)
|
||||
#define U8500_TZPC0_BASE_ED (U8500_PER7_BASE + 0xc000)
|
||||
#define U8500_CLKRST7_BASE_ED (U8500_PER7_BASE + 0xf000)
|
||||
#define UX500_I2C1_BASE UX500(I2C1)
|
||||
#define UX500_I2C2_BASE UX500(I2C2)
|
||||
#define UX500_I2C3_BASE UX500(I2C3)
|
||||
|
||||
/* per6 base addressess */
|
||||
#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
|
||||
#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000)
|
||||
#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000)
|
||||
#define U8500_MTU0_BASE_V1 (U8500_PER6_BASE + 0x6000)
|
||||
#define U8500_MTU1_BASE_V1 (U8500_PER6_BASE + 0x7000)
|
||||
#define U8500_CR_BASE_V1 (U8500_PER6_BASE + 0x8000)
|
||||
#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000)
|
||||
#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000)
|
||||
#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
|
||||
#define UX500_L2CC_BASE UX500(L2CC)
|
||||
#define UX500_MCDE_BASE UX500(MCDE)
|
||||
#define UX500_MTU0_BASE UX500(MTU0)
|
||||
#define UX500_MTU1_BASE UX500(MTU1)
|
||||
#define UX500_PRCMU_BASE UX500(PRCMU)
|
||||
|
||||
/* per5 base addressess */
|
||||
#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
|
||||
#define U8500_GPIO5_BASE (U8500_PER5_BASE + 0x1e000)
|
||||
#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
|
||||
#define UX500_RNG_BASE UX500(RNG)
|
||||
#define UX500_RTC_BASE UX500(RTC)
|
||||
|
||||
/* per4 base addressess */
|
||||
#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x0000)
|
||||
#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x1000)
|
||||
#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x2000)
|
||||
#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x3000)
|
||||
#define U8500_RTC_BASE (U8500_PER4_BASE + 0x4000)
|
||||
#define U8500_SCR_BASE (U8500_PER4_BASE + 0x5000)
|
||||
#define U8500_DMC_BASE (U8500_PER4_BASE + 0x6000)
|
||||
#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x7000)
|
||||
#define UX500_SCU_BASE UX500(SCU)
|
||||
|
||||
/* per3 base addressess */
|
||||
#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
|
||||
#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
|
||||
#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
|
||||
#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
|
||||
#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
|
||||
#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
|
||||
#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
|
||||
#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
|
||||
#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xe000)
|
||||
#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
|
||||
#define UX500_SDI0_BASE UX500(SDI0)
|
||||
#define UX500_SDI1_BASE UX500(SDI1)
|
||||
#define UX500_SDI2_BASE UX500(SDI2)
|
||||
#define UX500_SDI3_BASE UX500(SDI3)
|
||||
#define UX500_SDI4_BASE UX500(SDI4)
|
||||
|
||||
/* per2 base addressess */
|
||||
#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
|
||||
#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
|
||||
#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
|
||||
#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
|
||||
#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
|
||||
#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
|
||||
#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
|
||||
#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
|
||||
#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
|
||||
#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
|
||||
#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
|
||||
#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xe000)
|
||||
#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
|
||||
#define UX500_SPI0_BASE UX500(SPI0)
|
||||
#define UX500_SPI1_BASE UX500(SPI1)
|
||||
#define UX500_SPI2_BASE UX500(SPI2)
|
||||
#define UX500_SPI3_BASE UX500(SPI3)
|
||||
|
||||
/* per1 base addresses */
|
||||
#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
|
||||
#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
|
||||
#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
|
||||
#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
|
||||
#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
|
||||
#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
|
||||
#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
|
||||
#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
|
||||
#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xa000)
|
||||
#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xe000)
|
||||
#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
|
||||
#define UX500_SIA_BASE UX500(SIA)
|
||||
#define UX500_SVA_BASE UX500(SVA)
|
||||
|
||||
#define U8500_GPIOBANK0_BASE U8500_GPIO1_BASE
|
||||
#define U8500_GPIOBANK1_BASE (U8500_GPIO1_BASE + 0x80)
|
||||
#define U8500_GPIOBANK2_BASE U8500_GPIO3_BASE
|
||||
#define U8500_GPIOBANK3_BASE (U8500_GPIO3_BASE + 0x80)
|
||||
#define U8500_GPIOBANK4_BASE (U8500_GPIO3_BASE + 0x100)
|
||||
#define U8500_GPIOBANK5_BASE (U8500_GPIO3_BASE + 0x180)
|
||||
#define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE
|
||||
#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80)
|
||||
#define U8500_GPIOBANK8_BASE U8500_GPIO5_BASE
|
||||
#define UX500_TWD_BASE UX500(TWD)
|
||||
|
||||
#define UX500_UART0_BASE UX500(UART0)
|
||||
#define UX500_UART1_BASE UX500(UART1)
|
||||
#define UX500_UART2_BASE UX500(UART2)
|
||||
|
||||
#define UX500_USBOTG_BASE UX500(USBOTG)
|
||||
|
||||
/* ST-Ericsson modified pl022 id */
|
||||
#define SSP_PER_ID 0x01080022
|
||||
|
|
|
|||
Loading…
Reference in a new issue