iwlagn: cosmetics in iwl-trans.h
Remove a few dereferences of priv from the transport layer while at it. Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Emmanuel Grumbach
John W. Linville
parent
7f01d567c5
commit
c91bd12489
5 changed files with 44 additions and 44 deletions
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@ -2565,7 +2565,7 @@ static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
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case IEEE80211_AMPDU_TX_OPERATIONAL:
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buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
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iwl_trans_txq_agg_setup(trans(priv), ctx->ctxid, iwl_sta_id(sta),
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iwl_trans_tx_agg_setup(trans(priv), ctx->ctxid, iwl_sta_id(sta),
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tid, buf_size);
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/*
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@ -194,15 +194,15 @@ int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans,
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enum iwl_rxon_context_id ctx, int sta_id,
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int tid);
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void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, int txq_id, u32 index);
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void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
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void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
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struct iwl_tx_queue *txq,
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int tx_fifo_id, int scd_retry);
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int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans,
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enum iwl_rxon_context_id ctx, int sta_id,
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int tid, u16 *ssn);
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void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv,
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enum iwl_rxon_context_id ctx,
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int sta_id, int tid, int frame_limit);
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void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
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enum iwl_rxon_context_id ctx,
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int sta_id, int tid, int frame_limit);
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void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
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int index);
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int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
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@ -403,14 +403,15 @@ void iwl_trans_set_wr_ptrs(struct iwl_trans *trans,
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iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(txq_id), index);
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}
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void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
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void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
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struct iwl_tx_queue *txq,
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int tx_fifo_id, int scd_retry)
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{
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int txq_id = txq->q.id;
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int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
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int active =
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test_bit(txq_id, &priv(trans)->txq_ctx_active_msk) ? 1 : 0;
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iwl_write_prph(bus(priv), SCD_QUEUE_STATUS_BITS(txq_id),
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iwl_write_prph(bus(trans), SCD_QUEUE_STATUS_BITS(txq_id),
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(active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
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(tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
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(1 << SCD_QUEUE_STTS_REG_POS_WSL) |
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@ -418,7 +419,7 @@ void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
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txq->sched_retry = scd_retry;
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IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
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IWL_DEBUG_INFO(trans, "%s %s Queue %d on FIFO %d\n",
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active ? "Activate" : "Deactivate",
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scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
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}
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@ -434,16 +435,15 @@ static inline int get_fifo_from_tid(struct iwl_trans_pcie *trans_pcie,
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return -EINVAL;
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}
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void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv,
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enum iwl_rxon_context_id ctx, int sta_id,
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int tid, int frame_limit)
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void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
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enum iwl_rxon_context_id ctx, int sta_id,
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int tid, int frame_limit)
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{
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int tx_fifo, txq_id, ssn_idx;
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u16 ra_tid;
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unsigned long flags;
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struct iwl_tid_data *tid_data;
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struct iwl_trans *trans = trans(priv);
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struct iwl_trans_pcie *trans_pcie =
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IWL_TRANS_GET_PCIE_TRANS(trans);
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@ -458,15 +458,15 @@ void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv,
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return;
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}
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spin_lock_irqsave(&priv->shrd->sta_lock, flags);
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tid_data = &priv->shrd->tid_data[sta_id][tid];
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spin_lock_irqsave(&trans->shrd->sta_lock, flags);
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tid_data = &trans->shrd->tid_data[sta_id][tid];
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ssn_idx = SEQ_TO_SN(tid_data->seq_number);
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txq_id = tid_data->agg.txq_id;
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spin_unlock_irqrestore(&priv->shrd->sta_lock, flags);
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spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
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ra_tid = BUILD_RAxTID(sta_id, tid);
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spin_lock_irqsave(&priv->shrd->lock, flags);
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spin_lock_irqsave(&trans->shrd->lock, flags);
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/* Stop this Tx queue before configuring it */
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iwlagn_tx_queue_stop_scheduler(trans, txq_id);
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@ -475,19 +475,19 @@ void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv,
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iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id);
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/* Set this queue as a chain-building queue */
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iwl_set_bits_prph(bus(priv), SCD_QUEUECHAIN_SEL, (1<<txq_id));
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iwl_set_bits_prph(bus(trans), SCD_QUEUECHAIN_SEL, (1<<txq_id));
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/* enable aggregations for the queue */
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iwl_set_bits_prph(bus(priv), SCD_AGGR_SEL, (1<<txq_id));
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iwl_set_bits_prph(bus(trans), SCD_AGGR_SEL, (1<<txq_id));
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/* Place first TFD at index corresponding to start sequence number.
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* Assumes that ssn_idx is valid (!= 0xFFF) */
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priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
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priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
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priv(trans)->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
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priv(trans)->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
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iwl_trans_set_wr_ptrs(trans, txq_id, ssn_idx);
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/* Set up Tx window size and frame limit for this queue */
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iwl_write_targ_mem(bus(priv), trans_pcie->scd_base_addr +
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iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
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SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
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sizeof(u32),
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((frame_limit <<
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@ -497,15 +497,16 @@ void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv,
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SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
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SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
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iwl_set_bits_prph(bus(priv), SCD_INTERRUPT_MASK, (1 << txq_id));
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iwl_set_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id));
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/* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
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iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
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iwl_trans_tx_queue_set_status(trans, &priv(trans)->txq[txq_id],
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tx_fifo, 1);
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priv->txq[txq_id].sta_id = sta_id;
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priv->txq[txq_id].tid = tid;
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priv(trans)->txq[txq_id].sta_id = sta_id;
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priv(trans)->txq[txq_id].tid = tid;
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spin_unlock_irqrestore(&priv->shrd->lock, flags);
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spin_unlock_irqrestore(&trans->shrd->lock, flags);
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}
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/*
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@ -574,8 +575,7 @@ void iwl_trans_pcie_txq_agg_disable(struct iwl_trans *trans, int txq_id)
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iwl_clear_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id));
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iwl_txq_ctx_deactivate(priv(trans), txq_id);
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iwl_trans_tx_queue_set_status(priv(trans),
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&priv(trans)->txq[txq_id], 0, 0);
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iwl_trans_tx_queue_set_status(trans, &priv(trans)->txq[txq_id], 0, 0);
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}
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int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans,
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@ -774,7 +774,7 @@ static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
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struct iwl_trans_pcie *trans_pcie =
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IWL_TRANS_GET_PCIE_TRANS(trans);
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priv->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
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trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
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trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
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trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
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@ -784,7 +784,7 @@ static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
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trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
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trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
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if ((hw_params(priv).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
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if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
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iwl_trans_pcie_prepare_card_hw(trans)) {
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IWL_WARN(trans, "Exit HW not ready\n");
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return -EIO;
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@ -862,7 +862,7 @@ static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
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a += 4)
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iwl_write_targ_mem(bus(trans), a, 0);
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for (; a < trans_pcie->scd_base_addr +
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SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(priv).max_txq_num);
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SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
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a += 4)
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iwl_write_targ_mem(bus(trans), a, 0);
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@ -881,11 +881,11 @@ static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
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reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
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iwl_write_prph(bus(trans), SCD_QUEUECHAIN_SEL,
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SCD_QUEUECHAIN_SEL_ALL(priv));
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SCD_QUEUECHAIN_SEL_ALL(trans));
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iwl_write_prph(bus(trans), SCD_AGGR_SEL, 0);
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/* initiate the queues */
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for (i = 0; i < hw_params(priv).max_txq_num; i++) {
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for (i = 0; i < hw_params(trans).max_txq_num; i++) {
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iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(i), 0);
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iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 0 | (i << 8));
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iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
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@ -941,7 +941,7 @@ static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
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if (ac != IWL_AC_UNSET)
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iwl_set_swq_id(&priv->txq[i], ac, i);
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iwl_trans_tx_queue_set_status(priv, &priv->txq[i], fifo, 0);
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iwl_trans_tx_queue_set_status(trans, &priv->txq[i], fifo, 0);
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}
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spin_unlock_irqrestore(&trans->shrd->lock, flags);
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@ -2017,7 +2017,7 @@ const struct iwl_trans_ops trans_ops_pcie = {
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.tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
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.tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
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.txq_agg_setup = iwl_trans_pcie_txq_agg_setup,
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.tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
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.kick_nic = iwl_trans_pcie_kick_nic,
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@ -95,7 +95,7 @@ struct iwl_device_cmd;
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* @tx: send an skb
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* @reclaim: free packet until ssn. Returns a list of freed packets.
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* @tx_agg_alloc: allocate resources for a TX BA session
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* @txq_agg_setup: setup a tx queue for AMPDU - will be called once the HW is
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* @tx_agg_setup: setup a tx queue for AMPDU - will be called once the HW is
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* ready and a successful ADDBA response has been received.
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* @tx_agg_disable: de-configure a Tx queue to send AMPDUs
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* @kick_nic: remove the RESET from the embedded CPU and let it run
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@ -128,14 +128,14 @@ struct iwl_trans_ops {
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struct sk_buff_head *skbs);
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int (*tx_agg_disable)(struct iwl_trans *trans,
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enum iwl_rxon_context_id ctx, int sta_id,
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int tid);
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enum iwl_rxon_context_id ctx, int sta_id,
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int tid);
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int (*tx_agg_alloc)(struct iwl_trans *trans,
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enum iwl_rxon_context_id ctx, int sta_id, int tid,
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u16 *ssn);
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void (*txq_agg_setup)(struct iwl_priv *priv,
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enum iwl_rxon_context_id ctx, int sta_id,
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int tid, int frame_limit);
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void (*tx_agg_setup)(struct iwl_trans *trans,
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enum iwl_rxon_context_id ctx, int sta_id, int tid,
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int frame_limit);
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void (*kick_nic)(struct iwl_trans *trans);
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@ -233,12 +233,12 @@ static inline int iwl_trans_tx_agg_alloc(struct iwl_trans *trans,
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}
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static inline void iwl_trans_txq_agg_setup(struct iwl_trans *trans,
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static inline void iwl_trans_tx_agg_setup(struct iwl_trans *trans,
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enum iwl_rxon_context_id ctx,
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int sta_id, int tid,
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int frame_limit)
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{
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trans->ops->txq_agg_setup(priv(trans), ctx, sta_id, tid, frame_limit);
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trans->ops->tx_agg_setup(trans, ctx, sta_id, tid, frame_limit);
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}
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static inline void iwl_trans_kick_nic(struct iwl_trans *trans)
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