ptp: Added a clock that uses the eTSEC found on the MPC85xx.
The eTSEC includes a PTP clock with quite a few features. This patch adds support for the basic clock adjustment functions, plus two external time stamps, one alarm, and the PPS callback. Signed-off-by: Richard Cochran <richard.cochran@omicron.at> Acked-by: David S. Miller <davem@davemloft.net> Acked-by: John Stultz <john.stultz@linaro.org> Signed-off-by: John Stultz <john.stultz@linaro.org>
This commit is contained in:
Richard Cochran
John Stultz
parent
d94ba80ebb
commit
c78275f366
8 changed files with 708 additions and 0 deletions
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@ -74,3 +74,57 @@ Example:
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interrupt-parent = <&mpic>;
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phy-handle = <&phy0>
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};
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* Gianfar PTP clock nodes
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General Properties:
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- compatible Should be "fsl,etsec-ptp"
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- reg Offset and length of the register set for the device
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- interrupts There should be at least two interrupts. Some devices
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have as many as four PTP related interrupts.
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Clock Properties:
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- fsl,tclk-period Timer reference clock period in nanoseconds.
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- fsl,tmr-prsc Prescaler, divides the output clock.
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- fsl,tmr-add Frequency compensation value.
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- fsl,tmr-fiper1 Fixed interval period pulse generator.
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- fsl,tmr-fiper2 Fixed interval period pulse generator.
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- fsl,max-adj Maximum frequency adjustment in parts per billion.
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These properties set the operational parameters for the PTP
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clock. You must choose these carefully for the clock to work right.
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Here is how to figure good values:
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TimerOsc = system clock MHz
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tclk_period = desired clock period nanoseconds
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NominalFreq = 1000 / tclk_period MHz
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FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
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tmr_add = ceil(2^32 / FreqDivRatio)
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OutputClock = NominalFreq / tmr_prsc MHz
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PulseWidth = 1 / OutputClock microseconds
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FiperFreq1 = desired frequency in Hz
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FiperDiv1 = 1000000 * OutputClock / FiperFreq1
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tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
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max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1
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The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
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driver expects that tmr_fiper1 will be correctly set to produce a 1
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Pulse Per Second (PPS) signal, since this will be offered to the PPS
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subsystem to synchronize the Linux clock.
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Example:
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ptp_clock@24E00 {
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compatible = "fsl,etsec-ptp";
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reg = <0x24E00 0xB0>;
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interrupts = <12 0x8 13 0x8>;
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interrupt-parent = < &ipic >;
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fsl,tclk-period = <10>;
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fsl,tmr-prsc = <100>;
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fsl,tmr-add = <0x999999A4>;
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fsl,tmr-fiper1 = <0x3B9AC9F6>;
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fsl,tmr-fiper2 = <0x00018696>;
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fsl,max-adj = <659999998>;
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};
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@ -176,6 +176,19 @@
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sleep = <&pmc 0x00300000>;
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};
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ptp_clock@24E00 {
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compatible = "fsl,etsec-ptp";
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reg = <0x24E00 0xB0>;
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interrupts = <12 0x8 13 0x8>;
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interrupt-parent = < &ipic >;
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fsl,tclk-period = <10>;
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fsl,tmr-prsc = <100>;
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fsl,tmr-add = <0x999999A4>;
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fsl,tmr-fiper1 = <0x3B9AC9F6>;
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fsl,tmr-fiper2 = <0x00018696>;
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fsl,max-adj = <659999998>;
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};
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enet0: ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -324,6 +324,19 @@
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};
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};
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ptp_clock@24E00 {
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compatible = "fsl,etsec-ptp";
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reg = <0x24E00 0xB0>;
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interrupts = <68 2 69 2 70 2 71 2>;
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interrupt-parent = < &mpic >;
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fsl,tclk-period = <5>;
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fsl,tmr-prsc = <200>;
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fsl,tmr-add = <0xAAAAAAAB>;
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fsl,tmr-fiper1 = <0x3B9AC9FB>;
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fsl,tmr-fiper2 = <0x3B9AC9FB>;
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fsl,max-adj = <499999999>;
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};
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enet0: ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -178,6 +178,19 @@
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};
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ptp_clock@24E00 {
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compatible = "fsl,etsec-ptp";
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reg = <0x24E00 0xB0>;
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interrupts = <68 2 69 2 70 2>;
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interrupt-parent = < &mpic >;
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fsl,tclk-period = <5>;
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fsl,tmr-prsc = <200>;
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fsl,tmr-add = <0xCCCCCCCD>;
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fsl,tmr-fiper1 = <0x3B9AC9FB>;
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fsl,tmr-fiper2 = <0x0001869B>;
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fsl,max-adj = <249999999>;
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};
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enet0: ethernet@24000 {
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tbi-handle = <&tbi0>;
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phy-handle = <&phy0>;
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@ -224,6 +224,19 @@
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status = "disabled";
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};
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ptp_clock@24E00 {
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compatible = "fsl,etsec-ptp";
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reg = <0x24E00 0xB0>;
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interrupts = <68 2 69 2 70 2>;
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interrupt-parent = < &mpic >;
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fsl,tclk-period = <5>;
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fsl,tmr-prsc = <200>;
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fsl,tmr-add = <0xCCCCCCCD>;
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fsl,tmr-fiper1 = <0x3B9AC9FB>;
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fsl,tmr-fiper2 = <0x0001869B>;
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fsl,max-adj = <249999999>;
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};
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enet0: ethernet@24000 {
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fixed-link = <1 1 1000 0 0>;
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phy-connection-type = "rgmii-id";
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@ -31,6 +31,7 @@ obj-$(CONFIG_ATL2) += atlx/
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obj-$(CONFIG_ATL1E) += atl1e/
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obj-$(CONFIG_ATL1C) += atl1c/
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obj-$(CONFIG_GIANFAR) += gianfar_driver.o
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obj-$(CONFIG_PTP_1588_CLOCK_GIANFAR) += gianfar_ptp.o
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obj-$(CONFIG_TEHUTI) += tehuti.o
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obj-$(CONFIG_ENIC) += enic/
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obj-$(CONFIG_JME) += jme.o
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588
drivers/net/gianfar_ptp.c
Normal file
588
drivers/net/gianfar_ptp.c
Normal file
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@ -0,0 +1,588 @@
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/*
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* PTP 1588 clock using the eTSEC
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*
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* Copyright (C) 2010 OMICRON electronics GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/device.h>
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#include <linux/hrtimer.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/timex.h>
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#include <linux/io.h>
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#include <linux/ptp_clock_kernel.h>
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#include "gianfar.h"
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/*
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* gianfar ptp registers
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* Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
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*/
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struct gianfar_ptp_registers {
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u32 tmr_ctrl; /* Timer control register */
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u32 tmr_tevent; /* Timestamp event register */
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u32 tmr_temask; /* Timer event mask register */
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u32 tmr_pevent; /* Timestamp event register */
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u32 tmr_pemask; /* Timer event mask register */
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u32 tmr_stat; /* Timestamp status register */
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u32 tmr_cnt_h; /* Timer counter high register */
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u32 tmr_cnt_l; /* Timer counter low register */
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u32 tmr_add; /* Timer drift compensation addend register */
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u32 tmr_acc; /* Timer accumulator register */
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u32 tmr_prsc; /* Timer prescale */
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u8 res1[4];
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u32 tmroff_h; /* Timer offset high */
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u32 tmroff_l; /* Timer offset low */
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u8 res2[8];
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u32 tmr_alarm1_h; /* Timer alarm 1 high register */
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u32 tmr_alarm1_l; /* Timer alarm 1 high register */
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u32 tmr_alarm2_h; /* Timer alarm 2 high register */
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u32 tmr_alarm2_l; /* Timer alarm 2 high register */
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u8 res3[48];
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u32 tmr_fiper1; /* Timer fixed period interval */
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u32 tmr_fiper2; /* Timer fixed period interval */
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u32 tmr_fiper3; /* Timer fixed period interval */
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u8 res4[20];
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u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */
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u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */
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u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */
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u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */
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};
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/* Bit definitions for the TMR_CTRL register */
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#define ALM1P (1<<31) /* Alarm1 output polarity */
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#define ALM2P (1<<30) /* Alarm2 output polarity */
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#define FS (1<<28) /* FIPER start indication */
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#define PP1L (1<<27) /* Fiper1 pulse loopback mode enabled. */
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#define PP2L (1<<26) /* Fiper2 pulse loopback mode enabled. */
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#define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */
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#define TCLK_PERIOD_MASK (0x3ff)
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#define RTPE (1<<15) /* Record Tx Timestamp to PAL Enable. */
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#define FRD (1<<14) /* FIPER Realignment Disable */
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#define ESFDP (1<<11) /* External Tx/Rx SFD Polarity. */
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#define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */
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#define ETEP2 (1<<9) /* External trigger 2 edge polarity */
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#define ETEP1 (1<<8) /* External trigger 1 edge polarity */
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#define COPH (1<<7) /* Generated clock output phase. */
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#define CIPH (1<<6) /* External oscillator input clock phase */
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#define TMSR (1<<5) /* Timer soft reset. */
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#define BYP (1<<3) /* Bypass drift compensated clock */
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#define TE (1<<2) /* 1588 timer enable. */
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#define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */
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#define CKSEL_MASK (0x3)
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/* Bit definitions for the TMR_TEVENT register */
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#define ETS2 (1<<25) /* External trigger 2 timestamp sampled */
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#define ETS1 (1<<24) /* External trigger 1 timestamp sampled */
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#define ALM2 (1<<17) /* Current time = alarm time register 2 */
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#define ALM1 (1<<16) /* Current time = alarm time register 1 */
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#define PP1 (1<<7) /* periodic pulse generated on FIPER1 */
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#define PP2 (1<<6) /* periodic pulse generated on FIPER2 */
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#define PP3 (1<<5) /* periodic pulse generated on FIPER3 */
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/* Bit definitions for the TMR_TEMASK register */
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#define ETS2EN (1<<25) /* External trigger 2 timestamp enable */
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#define ETS1EN (1<<24) /* External trigger 1 timestamp enable */
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#define ALM2EN (1<<17) /* Timer ALM2 event enable */
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#define ALM1EN (1<<16) /* Timer ALM1 event enable */
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#define PP1EN (1<<7) /* Periodic pulse event 1 enable */
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#define PP2EN (1<<6) /* Periodic pulse event 2 enable */
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/* Bit definitions for the TMR_PEVENT register */
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#define TXP2 (1<<9) /* PTP transmitted timestamp im TXTS2 */
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#define TXP1 (1<<8) /* PTP transmitted timestamp in TXTS1 */
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#define RXP (1<<0) /* PTP frame has been received */
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/* Bit definitions for the TMR_PEMASK register */
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#define TXP2EN (1<<9) /* Transmit PTP packet event 2 enable */
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#define TXP1EN (1<<8) /* Transmit PTP packet event 1 enable */
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#define RXPEN (1<<0) /* Receive PTP packet event enable */
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/* Bit definitions for the TMR_STAT register */
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#define STAT_VEC_SHIFT (0) /* Timer general purpose status vector */
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#define STAT_VEC_MASK (0x3f)
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/* Bit definitions for the TMR_PRSC register */
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#define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */
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#define PRSC_OCK_MASK (0xffff)
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#define DRIVER "gianfar_ptp"
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#define DEFAULT_CKSEL 1
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#define N_ALARM 1 /* first alarm is used internally to reset fipers */
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#define N_EXT_TS 2
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#define REG_SIZE sizeof(struct gianfar_ptp_registers)
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struct etsects {
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struct gianfar_ptp_registers *regs;
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spinlock_t lock; /* protects regs */
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struct ptp_clock *clock;
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struct ptp_clock_info caps;
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struct resource *rsrc;
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int irq;
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u64 alarm_interval; /* for periodic alarm */
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u64 alarm_value;
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u32 tclk_period; /* nanoseconds */
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u32 tmr_prsc;
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u32 tmr_add;
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u32 cksel;
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u32 tmr_fiper1;
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u32 tmr_fiper2;
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};
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/*
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* Register access functions
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*/
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/* Caller must hold etsects->lock. */
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static u64 tmr_cnt_read(struct etsects *etsects)
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{
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u64 ns;
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u32 lo, hi;
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lo = gfar_read(&etsects->regs->tmr_cnt_l);
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hi = gfar_read(&etsects->regs->tmr_cnt_h);
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ns = ((u64) hi) << 32;
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ns |= lo;
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return ns;
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}
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/* Caller must hold etsects->lock. */
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static void tmr_cnt_write(struct etsects *etsects, u64 ns)
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{
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u32 hi = ns >> 32;
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u32 lo = ns & 0xffffffff;
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gfar_write(&etsects->regs->tmr_cnt_l, lo);
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gfar_write(&etsects->regs->tmr_cnt_h, hi);
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}
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/* Caller must hold etsects->lock. */
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static void set_alarm(struct etsects *etsects)
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{
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u64 ns;
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u32 lo, hi;
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ns = tmr_cnt_read(etsects) + 1500000000ULL;
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ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
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ns -= etsects->tclk_period;
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hi = ns >> 32;
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lo = ns & 0xffffffff;
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gfar_write(&etsects->regs->tmr_alarm1_l, lo);
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gfar_write(&etsects->regs->tmr_alarm1_h, hi);
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}
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/* Caller must hold etsects->lock. */
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static void set_fipers(struct etsects *etsects)
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{
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u32 tmr_ctrl = gfar_read(&etsects->regs->tmr_ctrl);
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gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl & (~TE));
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gfar_write(&etsects->regs->tmr_prsc, etsects->tmr_prsc);
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gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
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gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
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set_alarm(etsects);
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gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl|TE);
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}
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/*
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* Interrupt service routine
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*/
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static irqreturn_t isr(int irq, void *priv)
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{
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struct etsects *etsects = priv;
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struct ptp_clock_event event;
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u64 ns;
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u32 ack = 0, lo, hi, mask, val;
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val = gfar_read(&etsects->regs->tmr_tevent);
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if (val & ETS1) {
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ack |= ETS1;
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hi = gfar_read(&etsects->regs->tmr_etts1_h);
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lo = gfar_read(&etsects->regs->tmr_etts1_l);
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event.type = PTP_CLOCK_EXTTS;
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event.index = 0;
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event.timestamp = ((u64) hi) << 32;
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event.timestamp |= lo;
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ptp_clock_event(etsects->clock, &event);
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}
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if (val & ETS2) {
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ack |= ETS2;
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hi = gfar_read(&etsects->regs->tmr_etts2_h);
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lo = gfar_read(&etsects->regs->tmr_etts2_l);
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event.type = PTP_CLOCK_EXTTS;
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event.index = 1;
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event.timestamp = ((u64) hi) << 32;
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event.timestamp |= lo;
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ptp_clock_event(etsects->clock, &event);
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}
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if (val & ALM2) {
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ack |= ALM2;
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if (etsects->alarm_value) {
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event.type = PTP_CLOCK_ALARM;
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event.index = 0;
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event.timestamp = etsects->alarm_value;
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ptp_clock_event(etsects->clock, &event);
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}
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if (etsects->alarm_interval) {
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ns = etsects->alarm_value + etsects->alarm_interval;
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hi = ns >> 32;
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lo = ns & 0xffffffff;
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spin_lock(&etsects->lock);
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gfar_write(&etsects->regs->tmr_alarm2_l, lo);
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gfar_write(&etsects->regs->tmr_alarm2_h, hi);
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spin_unlock(&etsects->lock);
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etsects->alarm_value = ns;
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||||
} else {
|
||||
gfar_write(&etsects->regs->tmr_tevent, ALM2);
|
||||
spin_lock(&etsects->lock);
|
||||
mask = gfar_read(&etsects->regs->tmr_temask);
|
||||
mask &= ~ALM2EN;
|
||||
gfar_write(&etsects->regs->tmr_temask, mask);
|
||||
spin_unlock(&etsects->lock);
|
||||
etsects->alarm_value = 0;
|
||||
etsects->alarm_interval = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (val & PP1) {
|
||||
ack |= PP1;
|
||||
event.type = PTP_CLOCK_PPS;
|
||||
ptp_clock_event(etsects->clock, &event);
|
||||
}
|
||||
|
||||
if (ack) {
|
||||
gfar_write(&etsects->regs->tmr_tevent, ack);
|
||||
return IRQ_HANDLED;
|
||||
} else
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
/*
|
||||
* PTP clock operations
|
||||
*/
|
||||
|
||||
static int ptp_gianfar_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
|
||||
{
|
||||
u64 adj;
|
||||
u32 diff, tmr_add;
|
||||
int neg_adj = 0;
|
||||
struct etsects *etsects = container_of(ptp, struct etsects, caps);
|
||||
|
||||
if (ppb < 0) {
|
||||
neg_adj = 1;
|
||||
ppb = -ppb;
|
||||
}
|
||||
tmr_add = etsects->tmr_add;
|
||||
adj = tmr_add;
|
||||
adj *= ppb;
|
||||
diff = div_u64(adj, 1000000000ULL);
|
||||
|
||||
tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
|
||||
|
||||
gfar_write(&etsects->regs->tmr_add, tmr_add);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ptp_gianfar_adjtime(struct ptp_clock_info *ptp, s64 delta)
|
||||
{
|
||||
s64 now;
|
||||
unsigned long flags;
|
||||
struct etsects *etsects = container_of(ptp, struct etsects, caps);
|
||||
|
||||
spin_lock_irqsave(&etsects->lock, flags);
|
||||
|
||||
now = tmr_cnt_read(etsects);
|
||||
now += delta;
|
||||
tmr_cnt_write(etsects, now);
|
||||
|
||||
spin_unlock_irqrestore(&etsects->lock, flags);
|
||||
|
||||
set_fipers(etsects);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ptp_gianfar_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
|
||||
{
|
||||
u64 ns;
|
||||
u32 remainder;
|
||||
unsigned long flags;
|
||||
struct etsects *etsects = container_of(ptp, struct etsects, caps);
|
||||
|
||||
spin_lock_irqsave(&etsects->lock, flags);
|
||||
|
||||
ns = tmr_cnt_read(etsects);
|
||||
|
||||
spin_unlock_irqrestore(&etsects->lock, flags);
|
||||
|
||||
ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
|
||||
ts->tv_nsec = remainder;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ptp_gianfar_settime(struct ptp_clock_info *ptp,
|
||||
const struct timespec *ts)
|
||||
{
|
||||
u64 ns;
|
||||
unsigned long flags;
|
||||
struct etsects *etsects = container_of(ptp, struct etsects, caps);
|
||||
|
||||
ns = ts->tv_sec * 1000000000ULL;
|
||||
ns += ts->tv_nsec;
|
||||
|
||||
spin_lock_irqsave(&etsects->lock, flags);
|
||||
|
||||
tmr_cnt_write(etsects, ns);
|
||||
set_fipers(etsects);
|
||||
|
||||
spin_unlock_irqrestore(&etsects->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ptp_gianfar_enable(struct ptp_clock_info *ptp,
|
||||
struct ptp_clock_request *rq, int on)
|
||||
{
|
||||
struct etsects *etsects = container_of(ptp, struct etsects, caps);
|
||||
unsigned long flags;
|
||||
u32 bit, mask;
|
||||
|
||||
switch (rq->type) {
|
||||
case PTP_CLK_REQ_EXTTS:
|
||||
switch (rq->extts.index) {
|
||||
case 0:
|
||||
bit = ETS1EN;
|
||||
break;
|
||||
case 1:
|
||||
bit = ETS2EN;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
spin_lock_irqsave(&etsects->lock, flags);
|
||||
mask = gfar_read(&etsects->regs->tmr_temask);
|
||||
if (on)
|
||||
mask |= bit;
|
||||
else
|
||||
mask &= ~bit;
|
||||
gfar_write(&etsects->regs->tmr_temask, mask);
|
||||
spin_unlock_irqrestore(&etsects->lock, flags);
|
||||
return 0;
|
||||
|
||||
case PTP_CLK_REQ_PPS:
|
||||
spin_lock_irqsave(&etsects->lock, flags);
|
||||
mask = gfar_read(&etsects->regs->tmr_temask);
|
||||
if (on)
|
||||
mask |= PP1EN;
|
||||
else
|
||||
mask &= ~PP1EN;
|
||||
gfar_write(&etsects->regs->tmr_temask, mask);
|
||||
spin_unlock_irqrestore(&etsects->lock, flags);
|
||||
return 0;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
static struct ptp_clock_info ptp_gianfar_caps = {
|
||||
.owner = THIS_MODULE,
|
||||
.name = "gianfar clock",
|
||||
.max_adj = 512000,
|
||||
.n_alarm = N_ALARM,
|
||||
.n_ext_ts = N_EXT_TS,
|
||||
.n_per_out = 0,
|
||||
.pps = 1,
|
||||
.adjfreq = ptp_gianfar_adjfreq,
|
||||
.adjtime = ptp_gianfar_adjtime,
|
||||
.gettime = ptp_gianfar_gettime,
|
||||
.settime = ptp_gianfar_settime,
|
||||
.enable = ptp_gianfar_enable,
|
||||
};
|
||||
|
||||
/* OF device tree */
|
||||
|
||||
static int get_of_u32(struct device_node *node, char *str, u32 *val)
|
||||
{
|
||||
int plen;
|
||||
const u32 *prop = of_get_property(node, str, &plen);
|
||||
|
||||
if (!prop || plen != sizeof(*prop))
|
||||
return -1;
|
||||
*val = *prop;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gianfar_ptp_probe(struct platform_device *dev)
|
||||
{
|
||||
struct device_node *node = dev->dev.of_node;
|
||||
struct etsects *etsects;
|
||||
struct timespec now;
|
||||
int err = -ENOMEM;
|
||||
u32 tmr_ctrl;
|
||||
unsigned long flags;
|
||||
|
||||
etsects = kzalloc(sizeof(*etsects), GFP_KERNEL);
|
||||
if (!etsects)
|
||||
goto no_memory;
|
||||
|
||||
err = -ENODEV;
|
||||
|
||||
etsects->caps = ptp_gianfar_caps;
|
||||
etsects->cksel = DEFAULT_CKSEL;
|
||||
|
||||
if (get_of_u32(node, "fsl,tclk-period", &etsects->tclk_period) ||
|
||||
get_of_u32(node, "fsl,tmr-prsc", &etsects->tmr_prsc) ||
|
||||
get_of_u32(node, "fsl,tmr-add", &etsects->tmr_add) ||
|
||||
get_of_u32(node, "fsl,tmr-fiper1", &etsects->tmr_fiper1) ||
|
||||
get_of_u32(node, "fsl,tmr-fiper2", &etsects->tmr_fiper2) ||
|
||||
get_of_u32(node, "fsl,max-adj", &etsects->caps.max_adj)) {
|
||||
pr_err("device tree node missing required elements\n");
|
||||
goto no_node;
|
||||
}
|
||||
|
||||
etsects->irq = platform_get_irq(dev, 0);
|
||||
|
||||
if (etsects->irq == NO_IRQ) {
|
||||
pr_err("irq not in device tree\n");
|
||||
goto no_node;
|
||||
}
|
||||
if (request_irq(etsects->irq, isr, 0, DRIVER, etsects)) {
|
||||
pr_err("request_irq failed\n");
|
||||
goto no_node;
|
||||
}
|
||||
|
||||
etsects->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
|
||||
if (!etsects->rsrc) {
|
||||
pr_err("no resource\n");
|
||||
goto no_resource;
|
||||
}
|
||||
if (request_resource(&ioport_resource, etsects->rsrc)) {
|
||||
pr_err("resource busy\n");
|
||||
goto no_resource;
|
||||
}
|
||||
|
||||
spin_lock_init(&etsects->lock);
|
||||
|
||||
etsects->regs = ioremap(etsects->rsrc->start,
|
||||
1 + etsects->rsrc->end - etsects->rsrc->start);
|
||||
if (!etsects->regs) {
|
||||
pr_err("ioremap ptp registers failed\n");
|
||||
goto no_ioremap;
|
||||
}
|
||||
getnstimeofday(&now);
|
||||
ptp_gianfar_settime(&etsects->caps, &now);
|
||||
|
||||
tmr_ctrl =
|
||||
(etsects->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
|
||||
(etsects->cksel & CKSEL_MASK) << CKSEL_SHIFT;
|
||||
|
||||
spin_lock_irqsave(&etsects->lock, flags);
|
||||
|
||||
gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl);
|
||||
gfar_write(&etsects->regs->tmr_add, etsects->tmr_add);
|
||||
gfar_write(&etsects->regs->tmr_prsc, etsects->tmr_prsc);
|
||||
gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
|
||||
gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
|
||||
set_alarm(etsects);
|
||||
gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl|FS|RTPE|TE);
|
||||
|
||||
spin_unlock_irqrestore(&etsects->lock, flags);
|
||||
|
||||
etsects->clock = ptp_clock_register(&etsects->caps);
|
||||
if (IS_ERR(etsects->clock)) {
|
||||
err = PTR_ERR(etsects->clock);
|
||||
goto no_clock;
|
||||
}
|
||||
|
||||
dev_set_drvdata(&dev->dev, etsects);
|
||||
|
||||
return 0;
|
||||
|
||||
no_clock:
|
||||
no_ioremap:
|
||||
release_resource(etsects->rsrc);
|
||||
no_resource:
|
||||
free_irq(etsects->irq, etsects);
|
||||
no_node:
|
||||
kfree(etsects);
|
||||
no_memory:
|
||||
return err;
|
||||
}
|
||||
|
||||
static int gianfar_ptp_remove(struct platform_device *dev)
|
||||
{
|
||||
struct etsects *etsects = dev_get_drvdata(&dev->dev);
|
||||
|
||||
gfar_write(&etsects->regs->tmr_temask, 0);
|
||||
gfar_write(&etsects->regs->tmr_ctrl, 0);
|
||||
|
||||
ptp_clock_unregister(etsects->clock);
|
||||
iounmap(etsects->regs);
|
||||
release_resource(etsects->rsrc);
|
||||
free_irq(etsects->irq, etsects);
|
||||
kfree(etsects);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct of_device_id match_table[] = {
|
||||
{ .compatible = "fsl,etsec-ptp" },
|
||||
{},
|
||||
};
|
||||
|
||||
static struct platform_driver gianfar_ptp_driver = {
|
||||
.driver = {
|
||||
.name = "gianfar_ptp",
|
||||
.of_match_table = match_table,
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = gianfar_ptp_probe,
|
||||
.remove = gianfar_ptp_remove,
|
||||
};
|
||||
|
||||
/* module operations */
|
||||
|
||||
static int __init ptp_gianfar_init(void)
|
||||
{
|
||||
return platform_driver_register(&gianfar_ptp_driver);
|
||||
}
|
||||
|
||||
module_init(ptp_gianfar_init);
|
||||
|
||||
static void __exit ptp_gianfar_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&gianfar_ptp_driver);
|
||||
}
|
||||
|
||||
module_exit(ptp_gianfar_exit);
|
||||
|
||||
MODULE_AUTHOR("Richard Cochran <richard.cochran@omicron.at>");
|
||||
MODULE_DESCRIPTION("PTP clock using the eTSEC");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -27,4 +27,17 @@ config PTP_1588_CLOCK
|
|||
To compile this driver as a module, choose M here: the module
|
||||
will be called ptp.
|
||||
|
||||
config PTP_1588_CLOCK_GIANFAR
|
||||
tristate "Freescale eTSEC as PTP clock"
|
||||
depends on PTP_1588_CLOCK
|
||||
depends on GIANFAR
|
||||
help
|
||||
This driver adds support for using the eTSEC as a PTP
|
||||
clock. This clock is only useful if your PTP programs are
|
||||
getting hardware time stamps on the PTP Ethernet packets
|
||||
using the SO_TIMESTAMPING API.
|
||||
|
||||
To compile this driver as a module, choose M here: the module
|
||||
will be called gianfar_ptp.
|
||||
|
||||
endmenu
|
||||
|
|
|
|||
Loading…
Reference in a new issue