[ARM] Orion: programable address map support
The Orion has fully programable address map. There's a separate address map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB, Gigabit Ethernet, DMA/XOR engines, etc. Signed-off-by: Tzachi Perelstein <tzachi@marvell.com> Reviewed-by: Nicolas Pitre <nico@marvell.com> Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
This commit is contained in:
Tzachi Perelstein
Russell King
parent
038ee0832e
commit
c67de5b3c0
4 changed files with 564 additions and 1 deletions
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@ -1 +1 @@
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obj-y += common.o pci.o
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obj-y += common.o addr-map.o pci.o
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482
arch/arm/mach-orion/addr-map.c
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482
arch/arm/mach-orion/addr-map.c
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@ -0,0 +1,482 @@
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/*
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* arch/arm/mach-orion/addr-map.c
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*
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* Address map functions for Marvell Orion System On Chip
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/hardware.h>
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#include "common.h"
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/*
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* The Orion has fully programable address map. There's a separate address
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* map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB,
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* Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
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* address decode windows that allow it to access any of the Orion resources.
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*
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* CPU address decoding --
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* Linux assumes that it is the boot loader that already setup the access to
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* DDR and internal registers.
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* Setup access to PCI and PCI-E IO/MEM space is issued by core.c.
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* Setup access to various devices located on the device bus interface (e.g.
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* flashes, RTC, etc) should be issued by machine-setup.c according to
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* specific board population (by using orion_setup_cpu_win()).
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*
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* Non-CPU Masters address decoding --
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* Unlike the CPU, we setup the access from Orion's master interfaces to DDR
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* banks only (the typical use case).
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* Setup access for each master to DDR is issued by common.c.
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*
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* Note: although orion_setbits() and orion_clrbits() are not atomic
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* no locking is necessary here since code in this file is only called
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* at boot time when there is no concurrency issues.
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*/
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/*
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* Generic Address Decode Windows bit settings
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*/
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#define TARGET_DDR 0
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#define TARGET_PCI 3
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#define TARGET_PCIE 4
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#define TARGET_DEV_BUS 1
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#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \
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((n) == 1) ? 0xd : \
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((n) == 2) ? 0xb : \
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((n) == 3) ? 0x7 : 0xf)
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#define ATTR_PCIE_MEM 0x59
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#define ATTR_PCIE_IO 0x51
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#define ATTR_PCI_MEM 0x59
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#define ATTR_PCI_IO 0x51
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#define ATTR_DEV_CS0 0x1e
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#define ATTR_DEV_CS1 0x1d
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#define ATTR_DEV_CS2 0x1b
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#define ATTR_DEV_BOOT 0xf
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#define WIN_EN 1
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/*
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* Helpers to get DDR banks info
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*/
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#define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8))
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#define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8))
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#define DDR_MAX_CS 4
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#define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1)
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#define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000)
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#define DDR_BANK_EN 1
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/*
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* CPU Address Decode Windows registers
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*/
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#define CPU_WIN_CTRL(n) ORION_BRIDGE_REG(0x000 | ((n) << 4))
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#define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4))
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#define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4))
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#define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4))
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#define CPU_MAX_WIN 8
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/*
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* Use this CPU address decode windows allocation
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*/
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#define CPU_WIN_PCIE_IO 0
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#define CPU_WIN_PCI_IO 1
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#define CPU_WIN_PCIE_MEM 2
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#define CPU_WIN_PCI_MEM 3
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#define CPU_WIN_DEV_BOOT 4
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#define CPU_WIN_DEV_CS0 5
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#define CPU_WIN_DEV_CS1 6
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#define CPU_WIN_DEV_CS2 7
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/*
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* PCIE Address Decode Windows registers
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*/
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#define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4))
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#define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8))
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#define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8))
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#define PCIE_WIN_CTRL(n) ORION_PCIE_REG(0x1820 + ((n) << 4))
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#define PCIE_WIN_BASE(n) ORION_PCIE_REG(0x1824 + ((n) << 4))
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#define PCIE_WIN_REMAP(n) ORION_PCIE_REG(0x182c + ((n) << 4))
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#define PCIE_DEFWIN_CTRL ORION_PCIE_REG(0x18b0)
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#define PCIE_EXPROM_WIN_CTRL ORION_PCIE_REG(0x18c0)
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#define PCIE_EXPROM_WIN_REMP ORION_PCIE_REG(0x18c4)
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#define PCIE_MAX_BARS 3
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#define PCIE_MAX_WINS 5
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/*
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* Use PCIE BAR '1' for all DDR banks
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*/
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#define PCIE_DRAM_BAR 1
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/*
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* PCI Address Decode Windows registers
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*/
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#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \
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((n) == 1) ? ORION_PCI_REG(0xd08) : \
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((n) == 2) ? ORION_PCI_REG(0xc0c) : \
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((n) == 3) ? ORION_PCI_REG(0xd0c) : 0)
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#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \
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((n) == 1) ? ORION_PCI_REG(0xd48) : \
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((n) == 2) ? ORION_PCI_REG(0xc4c) : \
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((n) == 3) ? ORION_PCI_REG(0xd4c) : 0)
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#define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c)
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#define PCI_CTRL_BASE_LO(n) ORION_PCI_REG(0x1e00 | ((n) << 4))
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#define PCI_CTRL_BASE_HI(n) ORION_PCI_REG(0x1e04 | ((n) << 4))
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#define PCI_CTRL_SIZE(n) ORION_PCI_REG(0x1e08 | ((n) << 4))
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#define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c)
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/*
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* PCI configuration heleprs for BAR settings
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*/
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#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
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#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
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#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
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/*
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* Gigabit Ethernet Address Decode Windows registers
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*/
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#define ETH_WIN_BASE(win) ORION_ETH_REG(0x200 + ((win) * 8))
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#define ETH_WIN_SIZE(win) ORION_ETH_REG(0x204 + ((win) * 8))
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#define ETH_WIN_REMAP(win) ORION_ETH_REG(0x280 + ((win) * 4))
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#define ETH_WIN_EN ORION_ETH_REG(0x290)
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#define ETH_WIN_PROT ORION_ETH_REG(0x294)
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#define ETH_MAX_WIN 6
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#define ETH_MAX_REMAP_WIN 4
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/*
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* USB Address Decode Windows registers
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*/
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#define USB_WIN_CTRL(i, w) ((i == 0) ? ORION_USB0_REG(0x320 + ((w) << 4)) \
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: ORION_USB1_REG(0x320 + ((w) << 4)))
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#define USB_WIN_BASE(i, w) ((i == 0) ? ORION_USB0_REG(0x324 + ((w) << 4)) \
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: ORION_USB1_REG(0x324 + ((w) << 4)))
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#define USB_MAX_WIN 4
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/*
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* SATA Address Decode Windows registers
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*/
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#define SATA_WIN_CTRL(win) ORION_SATA_REG(0x30 + ((win) * 0x10))
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#define SATA_WIN_BASE(win) ORION_SATA_REG(0x34 + ((win) * 0x10))
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#define SATA_MAX_WIN 4
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static int __init orion_cpu_win_can_remap(u32 win)
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{
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u32 dev, rev;
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orion_pcie_id(&dev, &rev);
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if ((dev == MV88F5281_DEV_ID && win < 4) || (dev == MV88F5182_DEV_ID && win < 2))
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return 1;
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return 0;
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}
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void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap)
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{
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u32 win, attr, ctrl;
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switch (target) {
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case ORION_PCIE_IO:
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target = TARGET_PCIE;
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attr = ATTR_PCIE_IO;
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win = CPU_WIN_PCIE_IO;
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break;
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case ORION_PCI_IO:
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target = TARGET_PCI;
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attr = ATTR_PCI_IO;
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win = CPU_WIN_PCI_IO;
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break;
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case ORION_PCIE_MEM:
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target = TARGET_PCIE;
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attr = ATTR_PCIE_MEM;
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win = CPU_WIN_PCIE_MEM;
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break;
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case ORION_PCI_MEM:
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target = TARGET_PCI;
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attr = ATTR_PCI_MEM;
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win = CPU_WIN_PCI_MEM;
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break;
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case ORION_DEV_BOOT:
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target = TARGET_DEV_BUS;
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attr = ATTR_DEV_BOOT;
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win = CPU_WIN_DEV_BOOT;
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break;
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case ORION_DEV0:
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target = TARGET_DEV_BUS;
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attr = ATTR_DEV_CS0;
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win = CPU_WIN_DEV_CS0;
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break;
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case ORION_DEV1:
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target = TARGET_DEV_BUS;
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attr = ATTR_DEV_CS1;
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win = CPU_WIN_DEV_CS1;
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break;
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case ORION_DEV2:
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target = TARGET_DEV_BUS;
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attr = ATTR_DEV_CS2;
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win = CPU_WIN_DEV_CS2;
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break;
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case ORION_DDR:
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case ORION_REGS:
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/*
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* Must be mapped by bootloader.
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*/
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default:
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target = attr = win = -1;
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BUG();
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}
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base &= 0xffff0000;
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ctrl = (((size - 1) & 0xffff0000) | (attr << 8) |
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(target << 4) | WIN_EN);
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orion_write(CPU_WIN_BASE(win), base);
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orion_write(CPU_WIN_CTRL(win), ctrl);
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if (orion_cpu_win_can_remap(win)) {
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if (remap >= 0) {
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orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
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orion_write(CPU_WIN_REMAP_HI(win), 0);
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} else {
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orion_write(CPU_WIN_REMAP_LO(win), base);
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orion_write(CPU_WIN_REMAP_HI(win), 0);
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}
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}
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}
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void __init orion_setup_cpu_wins(void)
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{
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int i;
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/*
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* First, disable and clear windows
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*/
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for (i = 0; i < CPU_MAX_WIN; i++) {
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orion_write(CPU_WIN_BASE(i), 0);
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orion_write(CPU_WIN_CTRL(i), 0);
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if (orion_cpu_win_can_remap(i)) {
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orion_write(CPU_WIN_REMAP_LO(i), 0);
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orion_write(CPU_WIN_REMAP_HI(i), 0);
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}
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}
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/*
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* Setup windows for PCI+PCIE IO+MAM space
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*/
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orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_BASE,
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ORION_PCIE_IO_SIZE, ORION_PCIE_IO_REMAP);
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orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_BASE,
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ORION_PCI_IO_SIZE, ORION_PCI_IO_REMAP);
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orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_BASE,
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ORION_PCIE_MEM_SIZE, -1);
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orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_BASE,
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ORION_PCI_MEM_SIZE, -1);
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}
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/*
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* Setup PCIE BARs and Address Decode Wins:
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* BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
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* WIN[0-3] -> DRAM bank[0-3]
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*/
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void __init orion_setup_pcie_wins(void)
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{
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u32 base, size, i;
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/*
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* First, disable and clear BARs and windows
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*/
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for (i = 1; i < PCIE_MAX_BARS; i++) {
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orion_write(PCIE_BAR_CTRL(i), 0);
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orion_write(PCIE_BAR_LO(i), 0);
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orion_write(PCIE_BAR_HI(i), 0);
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}
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for (i = 0; i < PCIE_MAX_WINS; i++) {
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orion_write(PCIE_WIN_CTRL(i), 0);
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orion_write(PCIE_WIN_BASE(i), 0);
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orion_write(PCIE_WIN_REMAP(i), 0);
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}
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/*
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* Setup windows for DDR banks. Count total DDR size on the fly.
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*/
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base = DDR_REG_TO_BASE(orion_read(DDR_BASE_CS(0)));
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size = 0;
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for (i = 0; i < DDR_MAX_CS; i++) {
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u32 bank_base, bank_size;
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bank_size = orion_read(DDR_SIZE_CS(i));
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bank_base = orion_read(DDR_BASE_CS(i));
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if (bank_size & DDR_BANK_EN) {
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bank_size = DDR_REG_TO_SIZE(bank_size);
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bank_base = DDR_REG_TO_BASE(bank_base);
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orion_write(PCIE_WIN_BASE(i), bank_base & 0xffff0000);
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orion_write(PCIE_WIN_REMAP(i), 0);
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orion_write(PCIE_WIN_CTRL(i),
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((bank_size-1) & 0xffff0000) |
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(ATTR_DDR_CS(i) << 8) |
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(TARGET_DDR << 4) |
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(PCIE_DRAM_BAR << 1) | WIN_EN);
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size += bank_size;
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}
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}
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/*
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* Setup BAR[1] to all DRAM banks
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*/
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orion_write(PCIE_BAR_LO(PCIE_DRAM_BAR), base & 0xffff0000);
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orion_write(PCIE_BAR_HI(PCIE_DRAM_BAR), 0);
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orion_write(PCIE_BAR_CTRL(PCIE_DRAM_BAR),
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((size - 1) & 0xffff0000) | WIN_EN);
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}
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void __init orion_setup_pci_wins(void)
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{
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u32 base, size, i;
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/*
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* First, disable windows
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*/
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orion_write(PCI_BAR_ENABLE, 0xffffffff);
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/*
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* Setup windows for DDR banks.
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*/
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for (i = 0; i < DDR_MAX_CS; i++) {
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base = orion_read(DDR_BASE_CS(i));
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size = orion_read(DDR_SIZE_CS(i));
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if (size & DDR_BANK_EN) {
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u32 bus, dev, func, reg, val;
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size = DDR_REG_TO_SIZE(size);
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base = DDR_REG_TO_BASE(base);
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bus = orion_pci_local_bus_nr();
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dev = orion_pci_local_dev_nr();
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func = PCI_CONF_FUNC_BAR_CS(i);
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reg = PCI_CONF_REG_BAR_LO_CS(i);
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orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val);
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orion_pci_hw_wr_conf(bus, dev, func, reg, 4,
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(base & 0xfffff000) | (val & 0xfff));
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reg = PCI_CONF_REG_BAR_HI_CS(i);
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orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0);
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orion_write(PCI_BAR_SIZE_DDR_CS(i),
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(size - 1) & 0xfffff000);
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orion_write(PCI_BAR_REMAP_DDR_CS(i),
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base & 0xfffff000);
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orion_clrbits(PCI_BAR_ENABLE, (1 << i));
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}
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}
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/*
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* Disable automatic update of address remaping when writing to BARs
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*/
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orion_setbits(PCI_ADDR_DECODE_CTRL, 1);
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}
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void __init orion_setup_usb_wins(void)
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{
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int i;
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u32 usb_if, dev, rev;
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u32 max_usb_if = 1;
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orion_pcie_id(&dev, &rev);
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if (dev == MV88F5182_DEV_ID)
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max_usb_if = 2;
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for (usb_if = 0; usb_if < max_usb_if; usb_if++) {
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/*
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* First, disable and clear windows
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*/
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for (i = 0; i < USB_MAX_WIN; i++) {
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orion_write(USB_WIN_BASE(usb_if, i), 0);
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orion_write(USB_WIN_CTRL(usb_if, i), 0);
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}
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/*
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* Setup windows for DDR banks.
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*/
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for (i = 0; i < DDR_MAX_CS; i++) {
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u32 base, size;
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size = orion_read(DDR_SIZE_CS(i));
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base = orion_read(DDR_BASE_CS(i));
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if (size & DDR_BANK_EN) {
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base = DDR_REG_TO_BASE(base);
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size = DDR_REG_TO_SIZE(size);
|
||||
orion_write(USB_WIN_CTRL(usb_if, i),
|
||||
((size-1) & 0xffff0000) |
|
||||
(ATTR_DDR_CS(i) << 8) |
|
||||
(TARGET_DDR << 4) | WIN_EN);
|
||||
orion_write(USB_WIN_BASE(usb_if, i),
|
||||
base & 0xffff0000);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void __init orion_setup_eth_wins(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/*
|
||||
* First, disable and clear windows
|
||||
*/
|
||||
for (i = 0; i < ETH_MAX_WIN; i++) {
|
||||
orion_write(ETH_WIN_BASE(i), 0);
|
||||
orion_write(ETH_WIN_SIZE(i), 0);
|
||||
orion_setbits(ETH_WIN_EN, 1 << i);
|
||||
orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
|
||||
if (i < ETH_MAX_REMAP_WIN)
|
||||
orion_write(ETH_WIN_REMAP(i), 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup windows for DDR banks.
|
||||
*/
|
||||
for (i = 0; i < DDR_MAX_CS; i++) {
|
||||
u32 base, size;
|
||||
size = orion_read(DDR_SIZE_CS(i));
|
||||
base = orion_read(DDR_BASE_CS(i));
|
||||
if (size & DDR_BANK_EN) {
|
||||
base = DDR_REG_TO_BASE(base);
|
||||
size = DDR_REG_TO_SIZE(size);
|
||||
orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
|
||||
orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
|
||||
(ATTR_DDR_CS(i) << 8) |
|
||||
TARGET_DDR);
|
||||
orion_clrbits(ETH_WIN_EN, 1 << i);
|
||||
orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void __init orion_setup_sata_wins(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/*
|
||||
* First, disable and clear windows
|
||||
*/
|
||||
for (i = 0; i < SATA_MAX_WIN; i++) {
|
||||
orion_write(SATA_WIN_BASE(i), 0);
|
||||
orion_write(SATA_WIN_CTRL(i), 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup windows for DDR banks.
|
||||
*/
|
||||
for (i = 0; i < DDR_MAX_CS; i++) {
|
||||
u32 base, size;
|
||||
size = orion_read(DDR_SIZE_CS(i));
|
||||
base = orion_read(DDR_BASE_CS(i));
|
||||
if (size & DDR_BANK_EN) {
|
||||
base = DDR_REG_TO_BASE(base);
|
||||
size = DDR_REG_TO_SIZE(size);
|
||||
orion_write(SATA_WIN_CTRL(i),
|
||||
((size-1) & 0xffff0000) |
|
||||
(ATTR_DDR_CS(i) << 8) |
|
||||
(TARGET_DDR << 4) | WIN_EN);
|
||||
orion_write(SATA_WIN_BASE(i),
|
||||
base & 0xffff0000);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -13,6 +13,7 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/timex.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/arch/orion.h>
|
||||
#include "common.h"
|
||||
|
|
@ -51,3 +52,53 @@ void __init orion_map_io(void)
|
|||
{
|
||||
iotable_init(orion_io_desc, ARRAY_SIZE(orion_io_desc));
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* General
|
||||
****************************************************************************/
|
||||
|
||||
/*
|
||||
* Identify device ID and rev from PCIE configuration header space '0'.
|
||||
*/
|
||||
static void orion_id(u32 *dev, u32 *rev, char **dev_name)
|
||||
{
|
||||
orion_pcie_id(dev, rev);
|
||||
|
||||
if (*dev == MV88F5281_DEV_ID) {
|
||||
if (*rev == MV88F5281_REV_D2) {
|
||||
*dev_name = "MV88F5281-D2";
|
||||
} else if (*rev == MV88F5281_REV_D1) {
|
||||
*dev_name = "MV88F5281-D1";
|
||||
} else {
|
||||
*dev_name = "MV88F5281-Rev-Unsupported";
|
||||
}
|
||||
} else if (*dev == MV88F5182_DEV_ID) {
|
||||
if (*rev == MV88F5182_REV_A2) {
|
||||
*dev_name = "MV88F5182-A2";
|
||||
} else {
|
||||
*dev_name = "MV88F5182-Rev-Unsupported";
|
||||
}
|
||||
} else {
|
||||
*dev_name = "Device-Unknown";
|
||||
}
|
||||
}
|
||||
|
||||
void __init orion_init(void)
|
||||
{
|
||||
char *dev_name;
|
||||
u32 dev, rev;
|
||||
|
||||
orion_id(&dev, &rev, &dev_name);
|
||||
printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION_TCLK);
|
||||
|
||||
/*
|
||||
* Setup Orion address map
|
||||
*/
|
||||
orion_setup_cpu_wins();
|
||||
orion_setup_usb_wins();
|
||||
orion_setup_eth_wins();
|
||||
orion_setup_pci_wins();
|
||||
orion_setup_pcie_wins();
|
||||
if (dev == MV88F5182_DEV_ID)
|
||||
orion_setup_sata_wins();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,7 +4,37 @@
|
|||
/*
|
||||
* Basic Orion init functions used early by machine-setup.
|
||||
*/
|
||||
|
||||
void __init orion_map_io(void);
|
||||
void __init orion_init(void);
|
||||
|
||||
/*
|
||||
* Enumerations and functions for Orion windows mapping. Used by Orion core
|
||||
* functions to map its interfaces and by the machine-setup to map its on-
|
||||
* board devices. Details in /mach-orion/addr-map.c
|
||||
*/
|
||||
|
||||
enum orion_target {
|
||||
ORION_DEV_BOOT = 0,
|
||||
ORION_DEV0,
|
||||
ORION_DEV1,
|
||||
ORION_DEV2,
|
||||
ORION_PCIE_MEM,
|
||||
ORION_PCIE_IO,
|
||||
ORION_PCI_MEM,
|
||||
ORION_PCI_IO,
|
||||
ORION_DDR,
|
||||
ORION_REGS,
|
||||
ORION_MAX_TARGETS
|
||||
};
|
||||
|
||||
void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap);
|
||||
void orion_setup_cpu_wins(void);
|
||||
void orion_setup_eth_wins(void);
|
||||
void orion_setup_usb_wins(void);
|
||||
void orion_setup_pci_wins(void);
|
||||
void orion_setup_pcie_wins(void);
|
||||
void orion_setup_sata_wins(void);
|
||||
|
||||
/*
|
||||
* Shared code used internally by other Orion core functions.
|
||||
|
|
|
|||
Loading…
Reference in a new issue