arm64: KVM: Fix decoding of Rt/Rt2 when trapping AArch32 CP accesses
Our 32bit CP14/15 handling inherited some of the ARMv7 code for handling the trapped system registers, completely missing the fact that the fields for Rt and Rt2 are now 5 bit wide, and not 4... Let's fix it, and provide an accessor for the most common Rt case. Cc: stable@vger.kernel.org Reviewed-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@linaro.org>
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2 changed files with 10 additions and 4 deletions
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@ -240,6 +240,12 @@ static inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)
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return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC_TYPE;
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}
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static inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)
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{
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u32 esr = kvm_vcpu_get_hsr(vcpu);
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return (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
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}
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static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
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{
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return vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
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@ -1529,8 +1529,8 @@ static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
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{
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struct sys_reg_params params;
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u32 hsr = kvm_vcpu_get_hsr(vcpu);
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int Rt = (hsr >> 5) & 0xf;
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int Rt2 = (hsr >> 10) & 0xf;
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int Rt = kvm_vcpu_sys_get_rt(vcpu);
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int Rt2 = (hsr >> 10) & 0x1f;
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params.is_aarch32 = true;
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params.is_32bit = false;
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@ -1586,7 +1586,7 @@ static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
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{
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struct sys_reg_params params;
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u32 hsr = kvm_vcpu_get_hsr(vcpu);
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int Rt = (hsr >> 5) & 0xf;
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int Rt = kvm_vcpu_sys_get_rt(vcpu);
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params.is_aarch32 = true;
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params.is_32bit = true;
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@ -1688,7 +1688,7 @@ int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
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{
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struct sys_reg_params params;
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unsigned long esr = kvm_vcpu_get_hsr(vcpu);
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int Rt = (esr >> 5) & 0x1f;
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int Rt = kvm_vcpu_sys_get_rt(vcpu);
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int ret;
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trace_kvm_handle_sys_reg(esr);
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