V4L/DVB (8914): cx18: Throttle mmio to/from the CX23418 so boards work in older systems
cx18: Throttle mmio to/from the CX23418 so boards work in older systems. The CX23418 couldn't reliably handle mmio at the rate at which the cx18 driver was attempting to access the chip. The PCI bridge arrangements and settings on modern motherboards still allowed the CX23418 to work OK, but it didn't work well on many older motherboards: mysterious I2C errors, firmware loading errors, etc. This patch adds a throttle to *all* mmio access to the CX23418. It defaults to a delay of 31 ns, but is adjustable by the mmio_ndelay module parm. My HVR-1600 and Raptor PAL/SECAM card now function for analog capture on a motherboard with an Intel 82810E Northbridge and 82801AA Southbridge. Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Andy Walls
Mauro Carvalho Chehab
parent
b1526421ea
commit
c641d09c60
6 changed files with 168 additions and 88 deletions
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@ -4,6 +4,7 @@
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* Derived from ivtv-driver.c
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*
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* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
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* Copyright (C) 2008 Andy Walls <awalls@radix.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -74,10 +75,14 @@ static int radio[CX18_MAX_CARDS] = { -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1 };
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static int mmio_ndelay[CX18_MAX_CARDS] = { -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1 };
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static unsigned cardtype_c = 1;
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static unsigned tuner_c = 1;
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static unsigned radio_c = 1;
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static int mmio_ndelay_c = 1;
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static char pal[] = "--";
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static char secam[] = "--";
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static char ntsc[] = "-";
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@ -96,6 +101,7 @@ int cx18_debug;
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module_param_array(tuner, int, &tuner_c, 0644);
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module_param_array(radio, bool, &radio_c, 0644);
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module_param_array(cardtype, int, &cardtype_c, 0644);
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module_param_array(mmio_ndelay, int, &mmio_ndelay_c, 0644);
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module_param_string(pal, pal, sizeof(pal), 0644);
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module_param_string(secam, secam, sizeof(secam), 0644);
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module_param_string(ntsc, ntsc, sizeof(ntsc), 0644);
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@ -141,6 +147,11 @@ MODULE_PARM_DESC(debug,
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MODULE_PARM_DESC(cx18_pci_latency,
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"Change the PCI latency to 64 if lower: 0 = No, 1 = Yes,\n"
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"\t\t\tDefault: Yes");
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MODULE_PARM_DESC(mmio_ndelay,
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"Delay (ns) for each CX23418 memory mapped IO access.\n"
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"\t\t\tTry larger values that are close to a multiple of the\n"
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"\t\t\tPCI clock period, 30.3 ns, if your card doesn't work.\n"
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"\t\t\tDefault: " __stringify(CX18_DEFAULT_MMIO_NDELAY));
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MODULE_PARM_DESC(enc_mpg_buffers,
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"Encoder MPG Buffers (in MB)\n"
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"\t\t\tDefault: " __stringify(CX18_DEFAULT_ENC_MPG_BUFFERS));
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@ -357,6 +368,11 @@ static void cx18_process_options(struct cx18 *cx)
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cx->options.tuner = tuner[cx->num];
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cx->options.radio = radio[cx->num];
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if (mmio_ndelay[cx->num] < 0)
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cx->options.mmio_ndelay = CX18_DEFAULT_MMIO_NDELAY;
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else
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cx->options.mmio_ndelay = mmio_ndelay[cx->num];
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cx->std = cx18_parse_std(cx);
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if (cx->options.cardtype == -1) {
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CX18_INFO("Ignore card\n");
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@ -63,6 +63,9 @@
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# error "This driver requires kernel PCI support."
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#endif
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/* Default delay to throttle mmio access to the CX23418 so it doesn't choke */
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#define CX18_DEFAULT_MMIO_NDELAY 31 /* 30.3 ns = 1 PCI clock(s) / 33 MHz */
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#define CX18_MEM_OFFSET 0x00000000
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#define CX18_MEM_SIZE 0x04000000
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#define CX18_REG_OFFSET 0x02000000
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@ -176,6 +179,7 @@ struct cx18_options {
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int cardtype; /* force card type on load */
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int tuner; /* set tuner on load */
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int radio; /* enable/disable radio */
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unsigned long mmio_ndelay; /* delay in ns after every PCI mmio access */
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};
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/* per-buffer bit flags */
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@ -21,76 +21,69 @@
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*/
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#include "cx18-driver.h"
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#include "cx18-io.h"
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#include "cx18-irq.h"
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void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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__raw_writel(val, addr);
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}
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u32 cx18_raw_readl(struct cx18 *cx, const void __iomem *addr)
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{
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return __raw_readl(addr);
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}
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u32 cx18_write_sync(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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writel(val, addr);
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return readl(addr);
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}
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void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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writel(val, addr);
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}
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u32 cx18_readl(struct cx18 *cx, const void __iomem *addr)
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{
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return readl(addr);
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}
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/* Access "register" region of CX23418 memory mapped I/O */
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u32 cx18_read_reg(struct cx18 *cx, u32 reg)
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{
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return readl(cx->reg_mem + reg);
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}
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void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg)
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{
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writel(val, cx->reg_mem + reg);
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}
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u32 cx18_write_reg_sync(struct cx18 *cx, u32 val, u32 reg)
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{
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return cx18_write_sync(cx, val, cx->reg_mem + reg);
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}
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/* Access "encoder memory" region of CX23418 memory mapped I/O */
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u32 cx18_read_enc(struct cx18 *cx, u32 addr)
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{
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return readl(cx->enc_mem + addr);
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}
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void cx18_write_enc(struct cx18 *cx, u32 val, u32 addr)
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{
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writel(val, cx->enc_mem + addr);
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}
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u32 cx18_write_enc_sync(struct cx18 *cx, u32 val, u32 addr)
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{
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return cx18_write_sync(cx, val, cx->enc_mem + addr);
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}
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void cx18_memcpy_fromio(struct cx18 *cx, void *to,
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const void __iomem *from, unsigned int len)
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{
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memcpy_fromio(to, from, len);
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/* Align reads on the CX23418's addresses */
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if ((len > 0) && ((unsigned)from & 1)) {
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*((u8 *)to) = cx18_readb(cx, from);
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len--;
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to++;
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from++;
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}
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if ((len > 1) && ((unsigned)from & 2)) {
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*((u16 *)to) = cx18_raw_readw(cx, from);
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len -= 2;
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to += 2;
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from += 2;
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}
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while (len > 3) {
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*((u32 *)to) = cx18_raw_readl(cx, from);
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len -= 4;
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to += 4;
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from += 4;
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}
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if (len > 1) {
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*((u16 *)to) = cx18_raw_readw(cx, from);
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len -= 2;
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to += 2;
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from += 2;
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}
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if (len > 0)
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*((u8 *)to) = cx18_readb(cx, from);
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}
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void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
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{
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memset_io(addr, val, count);
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u16 val2 = val | (val << 8);
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u32 val4 = val2 | (val2 << 16);
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/* Align writes on the CX23418's addresses */
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if ((count > 0) && ((unsigned)addr & 1)) {
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cx18_writeb(cx, (u8) val, addr);
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count--;
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addr++;
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}
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if ((count > 1) && ((unsigned)addr & 2)) {
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cx18_writew(cx, val2, addr);
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count -= 2;
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addr += 2;
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}
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while (count > 3) {
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cx18_writel(cx, val4, addr);
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count -= 4;
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addr += 4;
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}
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if (count > 1) {
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cx18_writew(cx, val2, addr);
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count -= 2;
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addr += 2;
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}
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if (count > 0)
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cx18_writeb(cx, (u8) val, addr);
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}
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void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
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@ -25,38 +25,109 @@
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#include "cx18-driver.h"
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/* This is a PCI post thing, where if the pci register is not read, then
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the write doesn't always take effect right away. By reading back the
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register any pending PCI writes will be performed (in order), and so
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you can be sure that the writes are guaranteed to be done.
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static inline void cx18_io_delay(struct cx18 *cx)
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{
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if (cx->options.mmio_ndelay)
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ndelay(cx->options.mmio_ndelay);
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}
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Rarely needed, only in some timing sensitive cases.
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Apparently if this is not done some motherboards seem
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to kill the firmware and get into the broken state until computer is
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rebooted. */
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u32 cx18_write_sync(struct cx18 *cx, u32 val, void __iomem *addr);
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/* Non byteswapping memory mapped IO */
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static inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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__raw_writel(val, addr);
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cx18_io_delay(cx);
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}
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void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr);
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u32 cx18_readl(struct cx18 *cx, const void __iomem *addr);
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static inline u32 cx18_raw_readl(struct cx18 *cx, const void __iomem *addr)
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{
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u32 ret = __raw_readl(addr);
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cx18_io_delay(cx);
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return ret;
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}
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/* No endiannes conversion calls */
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void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr);
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u32 cx18_raw_readl(struct cx18 *cx, const void __iomem *addr);
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static inline u16 cx18_raw_readw(struct cx18 *cx, const void __iomem *addr)
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{
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u16 ret = __raw_readw(addr);
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cx18_io_delay(cx);
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return ret;
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}
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/* Access "register" region of CX23418 memory mapped I/O */
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u32 cx18_read_reg(struct cx18 *cx, u32 reg);
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void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg);
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u32 cx18_write_reg_sync(struct cx18 *cx, u32 val, u32 reg);
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/* Normal memory mapped IO */
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static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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writel(val, addr);
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cx18_io_delay(cx);
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}
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/* Access "encoder memory" region of CX23418 memory mapped I/O */
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u32 cx18_read_enc(struct cx18 *cx, u32 addr);
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void cx18_write_enc(struct cx18 *cx, u32 val, u32 addr);
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u32 cx18_write_enc_sync(struct cx18 *cx, u32 val, u32 addr);
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static inline void cx18_writew(struct cx18 *cx, u16 val, void __iomem *addr)
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{
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writew(val, addr);
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cx18_io_delay(cx);
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}
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static inline void cx18_writeb(struct cx18 *cx, u8 val, void __iomem *addr)
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{
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writeb(val, addr);
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cx18_io_delay(cx);
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}
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static inline u32 cx18_readl(struct cx18 *cx, const void __iomem *addr)
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{
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u32 ret = readl(addr);
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cx18_io_delay(cx);
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return ret;
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}
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static inline u8 cx18_readb(struct cx18 *cx, const void __iomem *addr)
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{
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u8 ret = readb(addr);
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cx18_io_delay(cx);
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return ret;
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}
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static inline u32 cx18_write_sync(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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cx18_writel(cx, val, addr);
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return cx18_readl(cx, addr);
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}
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void cx18_memcpy_fromio(struct cx18 *cx, void *to,
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const void __iomem *from, unsigned int len);
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void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count);
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/* Access "register" region of CX23418 memory mapped I/O */
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static inline void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg)
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{
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cx18_writel(cx, val, cx->reg_mem + reg);
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}
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static inline u32 cx18_read_reg(struct cx18 *cx, u32 reg)
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{
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return cx18_readl(cx, cx->reg_mem + reg);
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}
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static inline u32 cx18_write_reg_sync(struct cx18 *cx, u32 val, u32 reg)
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{
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return cx18_write_sync(cx, val, cx->reg_mem + reg);
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}
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/* Access "encoder memory" region of CX23418 memory mapped I/O */
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static inline void cx18_write_enc(struct cx18 *cx, u32 val, u32 addr)
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{
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cx18_writel(cx, val, cx->enc_mem + addr);
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}
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static inline u32 cx18_read_enc(struct cx18 *cx, u32 addr)
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{
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return cx18_readl(cx, cx->enc_mem + addr);
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}
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static inline u32 cx18_write_enc_sync(struct cx18 *cx, u32 val, u32 addr)
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{
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return cx18_write_sync(cx, val, cx->enc_mem + addr);
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}
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void cx18_sw1_irq_enable(struct cx18 *cx, u32 val);
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void cx18_sw1_irq_disable(struct cx18 *cx, u32 val);
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void cx18_sw2_irq_enable(struct cx18 *cx, u32 val);
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@ -170,7 +170,6 @@ int cx18_stream_alloc(struct cx18_stream *s)
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}
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buf->id = cx->buffer_id++;
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INIT_LIST_HEAD(&buf->list);
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/* FIXME - check for mmio */
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buf->dma_handle = pci_map_single(s->cx->dev,
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buf->buf, s->buf_size, s->dma);
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cx18_buf_sync_for_cpu(s, buf);
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@ -194,7 +193,6 @@ void cx18_stream_free(struct cx18_stream *s)
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/* empty q_free */
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while ((buf = cx18_dequeue(s, &s->q_free))) {
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/* FIXME - check for mmio */
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pci_unmap_single(s->cx->dev, buf->dma_handle,
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s->buf_size, s->dma);
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kfree(buf->buf);
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@ -28,7 +28,6 @@
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static inline void cx18_buf_sync_for_cpu(struct cx18_stream *s,
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struct cx18_buffer *buf)
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{
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/* FIXME check IO transfers */
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pci_dma_sync_single_for_cpu(s->cx->dev, buf->dma_handle,
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s->buf_size, s->dma);
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}
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@ -36,7 +35,6 @@ static inline void cx18_buf_sync_for_cpu(struct cx18_stream *s,
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static inline void cx18_buf_sync_for_device(struct cx18_stream *s,
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struct cx18_buffer *buf)
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{
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/* FIXME check IO transfers */
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pci_dma_sync_single_for_device(s->cx->dev, buf->dma_handle,
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s->buf_size, s->dma);
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}
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