[IA64] Remove duplicated members in iosapic_rte_info
Remove duplicated members in iosapic_rte_info in iosapic.c. This patch has no functional changes. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Yasuaki Ishimatsu <isimatu.yasuaki@jp.fujitsu.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
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1 changed files with 24 additions and 36 deletions
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@ -117,16 +117,22 @@ static DEFINE_SPINLOCK(iosapic_lock);
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* These tables map IA-64 vectors to the IOSAPIC pin that generates this
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* vector.
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*/
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static struct iosapic {
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char __iomem *addr; /* base address of IOSAPIC */
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unsigned int gsi_base; /* GSI base */
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unsigned short num_rte; /* # of RTEs on this IOSAPIC */
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int rtes_inuse; /* # of RTEs in use on this IOSAPIC */
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#ifdef CONFIG_NUMA
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unsigned short node; /* numa node association via pxm */
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#endif
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} iosapic_lists[NR_IOSAPICS];
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struct iosapic_rte_info {
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struct list_head rte_list; /* node in list of RTEs sharing the
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* same vector */
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char __iomem *addr; /* base address of IOSAPIC */
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unsigned int gsi_base; /* first GSI assigned to this
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* IOSAPIC */
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struct list_head rte_list; /* RTEs sharing the same vector */
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char rte_index; /* IOSAPIC RTE index */
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int refcnt; /* reference counter */
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unsigned int flags; /* flags */
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struct iosapic *iosapic;
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} ____cacheline_aligned;
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static struct iosapic_intr_info {
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@ -142,17 +148,6 @@ static struct iosapic_intr_info {
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unsigned char trigger : 1; /* trigger mode (see iosapic.h) */
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} iosapic_intr_info[IA64_NUM_VECTORS];
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static struct iosapic {
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char __iomem *addr; /* base address of IOSAPIC */
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unsigned int gsi_base; /* first GSI assigned to this
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* IOSAPIC */
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unsigned short num_rte; /* # of RTEs on this IOSAPIC */
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int rtes_inuse; /* # of RTEs in use on this IOSAPIC */
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#ifdef CONFIG_NUMA
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unsigned short node; /* numa node association via pxm */
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#endif
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} iosapic_lists[NR_IOSAPICS];
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static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */
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static int iosapic_kmalloc_ok;
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@ -184,7 +179,7 @@ _gsi_to_vector (unsigned int gsi)
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for (info = iosapic_intr_info; info <
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iosapic_intr_info + IA64_NUM_VECTORS; ++info)
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list_for_each_entry(rte, &info->rtes, rte_list)
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if (rte->gsi_base + rte->rte_index == gsi)
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if (rte->iosapic->gsi_base + rte->rte_index == gsi)
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return info - iosapic_intr_info;
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return -1;
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}
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@ -221,7 +216,7 @@ static struct iosapic_rte_info *gsi_vector_to_rte(unsigned int gsi,
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struct iosapic_rte_info *rte;
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list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list)
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if (rte->gsi_base + rte->rte_index == gsi)
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if (rte->iosapic->gsi_base + rte->rte_index == gsi)
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return rte;
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return NULL;
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}
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@ -243,7 +238,7 @@ set_rte (unsigned int gsi, unsigned int vector, unsigned int dest, int mask)
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return; /* not an IOSAPIC interrupt */
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rte_index = rte->rte_index;
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addr = rte->addr;
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addr = rte->iosapic->addr;
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pol = iosapic_intr_info[vector].polarity;
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trigger = iosapic_intr_info[vector].trigger;
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dmode = iosapic_intr_info[vector].dmode;
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@ -297,10 +292,10 @@ kexec_disable_iosapic(void)
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iosapic_intr_info + IA64_NUM_VECTORS; ++info, ++vec) {
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list_for_each_entry(rte, &info->rtes,
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rte_list) {
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iosapic_write(rte->addr,
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iosapic_write(rte->iosapic->addr,
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IOSAPIC_RTE_LOW(rte->rte_index),
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IOSAPIC_MASK|vec);
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iosapic_eoi(rte->addr, vec);
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iosapic_eoi(rte->iosapic->addr, vec);
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}
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}
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}
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@ -323,7 +318,7 @@ mask_irq (unsigned int irq)
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/* set only the mask bit */
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low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK;
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list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
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addr = rte->addr;
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addr = rte->iosapic->addr;
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rte_index = rte->rte_index;
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iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
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}
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@ -346,7 +341,7 @@ unmask_irq (unsigned int irq)
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spin_lock_irqsave(&iosapic_lock, flags);
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low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK;
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list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
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addr = rte->addr;
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addr = rte->iosapic->addr;
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rte_index = rte->rte_index;
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iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
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}
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@ -394,7 +389,7 @@ iosapic_set_affinity (unsigned int irq, cpumask_t mask)
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iosapic_intr_info[vec].low32 = low32;
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iosapic_intr_info[vec].dest = dest;
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list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
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addr = rte->addr;
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addr = rte->iosapic->addr;
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rte_index = rte->rte_index;
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iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32);
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iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
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@ -422,7 +417,7 @@ iosapic_end_level_irq (unsigned int irq)
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move_native_irq(irq);
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list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list)
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iosapic_eoi(rte->addr, vec);
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iosapic_eoi(rte->iosapic->addr, vec);
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}
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#define iosapic_shutdown_level_irq mask_irq
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@ -614,10 +609,7 @@ register_intr (unsigned int gsi, int vector, unsigned char delivery,
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{
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irq_desc_t *idesc;
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struct hw_interrupt_type *irq_type;
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int rte_index;
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int index;
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unsigned long gsi_base;
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void __iomem *iosapic_address;
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struct iosapic_rte_info *rte;
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index = find_iosapic(gsi);
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@ -627,9 +619,6 @@ register_intr (unsigned int gsi, int vector, unsigned char delivery,
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return -ENODEV;
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}
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iosapic_address = iosapic_lists[index].addr;
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gsi_base = iosapic_lists[index].gsi_base;
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rte = gsi_vector_to_rte(gsi, vector);
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if (!rte) {
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rte = iosapic_alloc_rte();
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@ -639,10 +628,8 @@ register_intr (unsigned int gsi, int vector, unsigned char delivery,
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return -ENOMEM;
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}
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rte_index = gsi - gsi_base;
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rte->rte_index = rte_index;
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rte->addr = iosapic_address;
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rte->gsi_base = gsi_base;
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rte->iosapic = &iosapic_lists[index];
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rte->rte_index = gsi - rte->iosapic->gsi_base;
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rte->refcnt++;
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list_add_tail(&rte->rte_list, &iosapic_intr_info[vector].rtes);
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iosapic_intr_info[vector].count++;
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@ -877,7 +864,8 @@ iosapic_unregister_intr (unsigned int gsi)
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/* Mask the interrupt */
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low32 = iosapic_intr_info[vector].low32 | IOSAPIC_MASK;
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iosapic_write(rte->addr, IOSAPIC_RTE_LOW(rte->rte_index), low32);
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iosapic_write(rte->iosapic->addr,
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IOSAPIC_RTE_LOW(rte->rte_index), low32);
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/* Remove the rte entry from the list */
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list_del(&rte->rte_list);
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