pinctrl: tegra20: Provide CDEV1/2 clock muxes
Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks. Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so that main clk-controller driver could get an actual parent clock for the CDEV1/2 clocks. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marc Dietrich <marvin24@gmx.de> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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3 changed files with 40 additions and 12 deletions
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@ -33,17 +33,6 @@
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#include "../pinctrl-utils.h"
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#include "../pinctrl-utils.h"
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#include "pinctrl-tegra.h"
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#include "pinctrl-tegra.h"
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struct tegra_pmx {
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struct device *dev;
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struct pinctrl_dev *pctl;
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const struct tegra_pinctrl_soc_data *soc;
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const char **group_pins;
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int nbanks;
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void __iomem **regs;
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};
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static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
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static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
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{
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{
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return readl(pmx->regs[bank] + reg);
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return readl(pmx->regs[bank] + reg);
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@ -16,6 +16,17 @@
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#ifndef __PINMUX_TEGRA_H__
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#ifndef __PINMUX_TEGRA_H__
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#define __PINMUX_TEGRA_H__
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#define __PINMUX_TEGRA_H__
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struct tegra_pmx {
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struct device *dev;
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struct pinctrl_dev *pctl;
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const struct tegra_pinctrl_soc_data *soc;
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const char **group_pins;
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int nbanks;
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void __iomem **regs;
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};
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enum tegra_pinconf_param {
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enum tegra_pinconf_param {
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/* argument: tegra_pinconf_pull */
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/* argument: tegra_pinconf_pull */
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TEGRA_PINCONF_PARAM_PULL,
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TEGRA_PINCONF_PARAM_PULL,
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@ -19,6 +19,7 @@
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* more details.
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* more details.
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*/
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*/
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#include <linux/clk-provider.h>
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/platform_device.h>
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@ -2231,9 +2232,36 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
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.drvtype_in_mux = false,
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.drvtype_in_mux = false,
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};
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};
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static const char *cdev1_parents[] = {
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"dev1_osc_div", "pll_a_out0", "pll_m_out1", "audio",
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};
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static const char *cdev2_parents[] = {
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"dev2_osc_div", "hclk", "pclk", "pll_p_out4",
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};
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static void tegra20_pinctrl_register_clock_muxes(struct platform_device *pdev)
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{
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struct tegra_pmx *pmx = platform_get_drvdata(pdev);
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clk_register_mux(NULL, "cdev1_mux", cdev1_parents, 4, 0,
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pmx->regs[1] + 0x8, 2, 2, CLK_MUX_READ_ONLY, NULL);
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clk_register_mux(NULL, "cdev2_mux", cdev2_parents, 4, 0,
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pmx->regs[1] + 0x8, 4, 2, CLK_MUX_READ_ONLY, NULL);
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}
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static int tegra20_pinctrl_probe(struct platform_device *pdev)
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static int tegra20_pinctrl_probe(struct platform_device *pdev)
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{
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{
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return tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
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int err;
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err = tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
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if (err)
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return err;
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tegra20_pinctrl_register_clock_muxes(pdev);
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return 0;
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}
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}
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static const struct of_device_id tegra20_pinctrl_of_match[] = {
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static const struct of_device_id tegra20_pinctrl_of_match[] = {
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