x86/oprofile: use 64 bit values in IBS functions
The IBS code internally uses 32 bit values (a low and a high value) to represent a 64 bit value. This patch changes this and now 64 bit values are used instead. 64 bit MSR functions can be used now. No functional changes. Signed-off-by: Robert Richter <robert.richter@amd.com>
This commit is contained in:
Robert Richter
parent
1a245c4534
commit
c572ae4efd
1 changed files with 61 additions and 70 deletions
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@ -35,16 +35,18 @@ static unsigned long reset_value[NUM_COUNTERS];
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#ifdef CONFIG_OPROFILE_IBS
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/* IbsFetchCtl bits/masks */
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#define IBS_FETCH_HIGH_VALID_BIT (1UL << 17) /* bit 49 */
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#define IBS_FETCH_HIGH_ENABLE (1UL << 16) /* bit 48 */
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#define IBS_FETCH_LOW_MAX_CNT_MASK 0x0000FFFFUL /* MaxCnt mask */
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#define IBS_FETCH_RAND_EN (1ULL<<57)
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#define IBS_FETCH_VAL (1ULL<<49)
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#define IBS_FETCH_ENABLE (1ULL<<48)
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#define IBS_FETCH_CNT_MASK 0xFFFF0000ULL
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/*IbsOpCtl bits */
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#define IBS_OP_LOW_VALID_BIT (1ULL<<18) /* bit 18 */
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#define IBS_OP_LOW_ENABLE (1ULL<<17) /* bit 17 */
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#define IBS_OP_CNT_CTL (1ULL<<19)
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#define IBS_OP_VAL (1ULL<<18)
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#define IBS_OP_ENABLE (1ULL<<17)
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#define IBS_FETCH_SIZE 6
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#define IBS_OP_SIZE 12
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#define IBS_FETCH_SIZE 6
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#define IBS_OP_SIZE 12
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static int has_ibs; /* AMD Family10h and later */
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@ -126,66 +128,63 @@ static inline int
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op_amd_handle_ibs(struct pt_regs * const regs,
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struct op_msrs const * const msrs)
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{
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u32 low, high;
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u64 msr;
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u64 val, ctl;
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struct op_entry entry;
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if (!has_ibs)
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return 1;
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if (ibs_config.fetch_enabled) {
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rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
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if (high & IBS_FETCH_HIGH_VALID_BIT) {
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rdmsrl(MSR_AMD64_IBSFETCHLINAD, msr);
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oprofile_write_reserve(&entry, regs, msr,
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rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
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if (ctl & IBS_FETCH_VAL) {
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rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
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oprofile_write_reserve(&entry, regs, val,
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IBS_FETCH_CODE, IBS_FETCH_SIZE);
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oprofile_add_data(&entry, (u32)msr);
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oprofile_add_data(&entry, (u32)(msr >> 32));
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oprofile_add_data(&entry, low);
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oprofile_add_data(&entry, high);
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rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, msr);
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oprofile_add_data(&entry, (u32)msr);
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oprofile_add_data(&entry, (u32)(msr >> 32));
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oprofile_add_data(&entry, (u32)val);
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oprofile_add_data(&entry, (u32)(val >> 32));
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oprofile_add_data(&entry, (u32)ctl);
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oprofile_add_data(&entry, (u32)(ctl >> 32));
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rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
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oprofile_add_data(&entry, (u32)val);
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oprofile_add_data(&entry, (u32)(val >> 32));
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oprofile_write_commit(&entry);
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/* reenable the IRQ */
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high &= ~IBS_FETCH_HIGH_VALID_BIT;
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high |= IBS_FETCH_HIGH_ENABLE;
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low &= IBS_FETCH_LOW_MAX_CNT_MASK;
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wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
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ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT_MASK);
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ctl |= IBS_FETCH_ENABLE;
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wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
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}
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}
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if (ibs_config.op_enabled) {
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rdmsr(MSR_AMD64_IBSOPCTL, low, high);
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if (low & IBS_OP_LOW_VALID_BIT) {
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rdmsrl(MSR_AMD64_IBSOPRIP, msr);
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oprofile_write_reserve(&entry, regs, msr,
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rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
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if (ctl & IBS_OP_VAL) {
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rdmsrl(MSR_AMD64_IBSOPRIP, val);
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oprofile_write_reserve(&entry, regs, val,
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IBS_OP_CODE, IBS_OP_SIZE);
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oprofile_add_data(&entry, (u32)msr);
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oprofile_add_data(&entry, (u32)(msr >> 32));
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rdmsrl(MSR_AMD64_IBSOPDATA, msr);
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oprofile_add_data(&entry, (u32)msr);
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oprofile_add_data(&entry, (u32)(msr >> 32));
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rdmsrl(MSR_AMD64_IBSOPDATA2, msr);
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oprofile_add_data(&entry, (u32)msr);
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oprofile_add_data(&entry, (u32)(msr >> 32));
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rdmsrl(MSR_AMD64_IBSOPDATA3, msr);
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oprofile_add_data(&entry, (u32)msr);
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oprofile_add_data(&entry, (u32)(msr >> 32));
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rdmsrl(MSR_AMD64_IBSDCLINAD, msr);
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oprofile_add_data(&entry, (u32)msr);
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oprofile_add_data(&entry, (u32)(msr >> 32));
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rdmsrl(MSR_AMD64_IBSDCPHYSAD, msr);
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oprofile_add_data(&entry, (u32)msr);
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oprofile_add_data(&entry, (u32)(msr >> 32));
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oprofile_add_data(&entry, (u32)val);
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oprofile_add_data(&entry, (u32)(val >> 32));
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rdmsrl(MSR_AMD64_IBSOPDATA, val);
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oprofile_add_data(&entry, (u32)val);
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oprofile_add_data(&entry, (u32)(val >> 32));
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rdmsrl(MSR_AMD64_IBSOPDATA2, val);
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oprofile_add_data(&entry, (u32)val);
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oprofile_add_data(&entry, (u32)(val >> 32));
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rdmsrl(MSR_AMD64_IBSOPDATA3, val);
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oprofile_add_data(&entry, (u32)val);
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oprofile_add_data(&entry, (u32)(val >> 32));
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rdmsrl(MSR_AMD64_IBSDCLINAD, val);
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oprofile_add_data(&entry, (u32)val);
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oprofile_add_data(&entry, (u32)(val >> 32));
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rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
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oprofile_add_data(&entry, (u32)val);
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oprofile_add_data(&entry, (u32)(val >> 32));
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oprofile_write_commit(&entry);
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/* reenable the IRQ */
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high = 0;
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low &= ~IBS_OP_LOW_VALID_BIT;
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low |= IBS_OP_LOW_ENABLE;
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wrmsr(MSR_AMD64_IBSOPCTL, low, high);
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ctl &= ~IBS_OP_VAL & 0xFFFFFFFF;
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ctl |= IBS_OP_ENABLE;
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wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
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}
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}
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@ -194,39 +193,31 @@ op_amd_handle_ibs(struct pt_regs * const regs,
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static inline void op_amd_start_ibs(void)
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{
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unsigned int low, high;
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u64 val;
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if (has_ibs && ibs_config.fetch_enabled) {
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low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
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high = ((ibs_config.rand_en & 0x1) << 25) /* bit 57 */
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+ IBS_FETCH_HIGH_ENABLE;
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wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
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val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
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val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
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val |= IBS_FETCH_ENABLE;
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wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
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}
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if (has_ibs && ibs_config.op_enabled) {
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low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF)
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+ ((ibs_config.dispatched_ops & 0x1) << 19) /* bit 19 */
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+ IBS_OP_LOW_ENABLE;
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high = 0;
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wrmsr(MSR_AMD64_IBSOPCTL, low, high);
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val = (ibs_config.max_cnt_op >> 4) & 0xFFFF;
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val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0;
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val |= IBS_OP_ENABLE;
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wrmsrl(MSR_AMD64_IBSOPCTL, val);
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}
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}
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static void op_amd_stop_ibs(void)
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{
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unsigned int low, high;
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if (has_ibs && ibs_config.fetch_enabled) {
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if (has_ibs && ibs_config.fetch_enabled)
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/* clear max count and enable */
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low = 0;
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high = 0;
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wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
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}
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wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
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if (has_ibs && ibs_config.op_enabled) {
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if (has_ibs && ibs_config.op_enabled)
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/* clear max count and enable */
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low = 0;
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high = 0;
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wrmsr(MSR_AMD64_IBSOPCTL, low, high);
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}
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wrmsrl(MSR_AMD64_IBSOPCTL, 0);
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}
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#else
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