drm/i915: always set FDI composite sync bit
It's needed for 3 pipe support as well as just regular functionality (e.g. DisplayPort). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Adam Jackson <ajax@redhat.com> Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: Keith Packard <keithp@keithp.com>
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2 changed files with 3 additions and 0 deletions
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@ -3189,6 +3189,7 @@
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#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
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/* both Tx and Rx */
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#define FDI_COMPOSITE_SYNC (1<<11)
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#define FDI_LINK_TRAIN_AUTO (1<<10)
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#define FDI_SCRAMBLING_ENABLE (0<<7)
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#define FDI_SCRAMBLING_DISABLE (1<<7)
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@ -2601,6 +2601,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
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temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
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temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
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temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
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temp |= FDI_COMPOSITE_SYNC;
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I915_WRITE(reg, temp | FDI_TX_ENABLE);
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reg = FDI_RX_CTL(pipe);
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@ -2608,6 +2609,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
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temp &= ~FDI_LINK_TRAIN_AUTO;
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temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
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temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
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temp |= FDI_COMPOSITE_SYNC;
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I915_WRITE(reg, temp | FDI_RX_ENABLE);
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POSTING_READ(reg);
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