Techwizz/kernel-fxtec-pro1x
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

skge: fix transmitter flow control

Browse source 
It looks like the skge driver inherited another bug from the sk98lin code.
If I send from 1000mbit port to a machine on 100mbit port, the switch should
be doing hardware flow control, but no pause frames show up in the statistics.

This is the analog of the recent sky2 fixes. The device needs to listen
for multicast pause frames and then not discard them.

Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Stephen Hemminger 2007-02-23 14:03:00 -08:00 committed by Jeff Garzik
parent 9dc6f0e789
commit c4cd29d205
2 changed files with 33 additions and 13 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

43
drivers/net/skge.c
View file

@ -2767,6 +2767,17 @@ static int skge_change_mtu(struct net_device *dev, int new_mtu)
return err;
}
static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
static void genesis_add_filter(u8 filter[8], const u8 *addr)
{
u32 crc, bit;
crc = ether_crc_le(ETH_ALEN, addr);
bit = ~crc & 0x3f;
filter[bit/8] |= 1 << (bit%8);
}
static void genesis_set_multicast(struct net_device *dev)
{
struct skge_port *skge = netdev_priv(dev);
@ -2788,24 +2799,33 @@ static void genesis_set_multicast(struct net_device *dev)
memset(filter, 0xff, sizeof(filter));
else {
memset(filter, 0, sizeof(filter));
for (i = 0; list && i < count; i++, list = list->next) {
u32 crc, bit;
crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
bit = ~crc & 0x3f;
filter[bit/8] |= 1 << (bit%8);
}
if (skge->flow_status == FLOW_STAT_REM_SEND
|| skge->flow_status == FLOW_STAT_SYMMETRIC)
genesis_add_filter(filter, pause_mc_addr);
for (i = 0; list && i < count; i++, list = list->next)
genesis_add_filter(filter, list->dmi_addr);
}
xm_write32(hw, port, XM_MODE, mode);
xm_outhash(hw, port, XM_HSM, filter);
}
static void yukon_add_filter(u8 filter[8], const u8 *addr)
{
u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
filter[bit/8] |= 1 << (bit%8);
}
static void yukon_set_multicast(struct net_device *dev)
{
struct skge_port *skge = netdev_priv(dev);
struct skge_hw *hw = skge->hw;
int port = skge->port;
struct dev_mc_list *list = dev->mc_list;
int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
|| skge->flow_status == FLOW_STAT_SYMMETRIC);
u16 reg;
u8 filter[8];
@ -2818,16 +2838,17 @@ static void yukon_set_multicast(struct net_device *dev)
reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
else if (dev->flags & IFF_ALLMULTI) /* all multicast */
memset(filter, 0xff, sizeof(filter));
else if (dev->mc_count == 0) /* no multicast */
else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
reg &= ~GM_RXCR_MCF_ENA;
else {
int i;
reg |= GM_RXCR_MCF_ENA;
for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
filter[bit/8] |= 1 << (bit%8);
}
if (rx_pause)
yukon_add_filter(filter, pause_mc_addr);
for (i = 0; list && i < dev->mc_count; i++, list = list->next)
yukon_add_filter(filter, list->dmi_addr);
}

3
drivers/net/skge.h
View file

@ -1849,8 +1849,7 @@ enum {
GMR_FS_JABBER,
/* Rx GMAC FIFO Flush Mask (default) */
RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
GMR_FS_BAD_FC | GMR_FS_GOOD_FC | GMR_FS_UN_SIZE |
GMR_FS_JABBER,
GMR_FS_BAD_FC | GMR_FS_UN_SIZE | GMR_FS_JABBER,
};
/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */