clk: mvebu: armada 370/XP add clock gating control provider for DT
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
This commit is contained in:
Gregory CLEMENT
Thomas Petazzoni
parent
f97d0d7aa8
commit
c4c34d6084
2 changed files with 116 additions and 1 deletions
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@ -6,6 +6,49 @@ the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to
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the corresponding clock gating control bit in HW to ease manual clock lookup
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in datasheet.
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The following is a list of provided IDs for Armada 370:
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ID Clock Peripheral
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-----------------------------------
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0 Audio AC97 Cntrl
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1 pex0_en PCIe 0 Clock out
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2 pex1_en PCIe 1 Clock out
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3 ge1 Gigabit Ethernet 1
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4 ge0 Gigabit Ethernet 0
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5 pex0 PCIe Cntrl 0
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9 pex1 PCIe Cntrl 1
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15 sata0 SATA Host 0
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17 sdio SDHCI Host
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25 tdm Time Division Mplx
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28 ddr DDR Cntrl
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30 sata1 SATA Host 0
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The following is a list of provided IDs for Armada XP:
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ID Clock Peripheral
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-----------------------------------
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0 audio Audio Cntrl
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1 ge3 Gigabit Ethernet 3
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2 ge2 Gigabit Ethernet 2
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3 ge1 Gigabit Ethernet 1
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4 ge0 Gigabit Ethernet 0
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5 pex0 PCIe Cntrl 0
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6 pex1 PCIe Cntrl 1
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7 pex2 PCIe Cntrl 2
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8 pex3 PCIe Cntrl 3
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13 bp
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14 sata0lnk
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15 sata0 SATA Host 0
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16 lcd LCD Cntrl
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17 sdio SDHCI Host
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18 usb0 USB Host 0
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19 usb1 USB Host 1
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20 usb2 USB Host 2
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22 xor0 XOR DMA 0
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23 crypto CESA engine
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25 tdm Time Division Mplx
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28 xor1 XOR DMA 1
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29 sata1lnk
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30 sata1 SATA Host 0
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The following is a list of provided IDs for Dove:
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ID Clock Peripheral
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-----------------------------------
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@ -88,10 +88,21 @@ static void __init mvebu_clk_gating_setup(
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}
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for (n = 0; n < ctrl->num_gates; n++) {
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u8 flags = 0;
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const char *parent =
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(descr[n].parent) ? descr[n].parent : default_parent;
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/*
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* On Armada 370, the DDR clock is a special case: it
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* isn't taken by any driver, but should anyway be
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* kept enabled, so we mark it as IGNORE_UNUSED for
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* now.
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*/
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if (!strcmp(descr[n].name, "ddr"))
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flags |= CLK_IGNORE_UNUSED;
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ctrl->gates[n] = clk_register_gate(NULL, descr[n].name, parent,
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0, base, descr[n].bit_idx, 0, &ctrl->lock);
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flags, base, descr[n].bit_idx, 0, &ctrl->lock);
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WARN_ON(IS_ERR(ctrl->gates[n]));
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}
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of_clk_add_provider(np, mvebu_clk_gating_get_src, ctrl);
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@ -101,6 +112,53 @@ static void __init mvebu_clk_gating_setup(
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* SoC specific clock gating control
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*/
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#ifdef CONFIG_MACH_ARMADA_370
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static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
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{ "audio", NULL, 0 },
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{ "pex0_en", NULL, 1 },
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{ "pex1_en", NULL, 2 },
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{ "ge1", NULL, 3 },
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{ "ge0", NULL, 4 },
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{ "pex0", NULL, 5 },
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{ "pex1", NULL, 9 },
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{ "sata0", NULL, 15 },
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{ "sdio", NULL, 17 },
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{ "tdm", NULL, 25 },
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{ "ddr", NULL, 28 },
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{ "sata1", NULL, 30 },
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{ }
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};
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#endif
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#ifdef CONFIG_MACH_ARMADA_XP
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static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
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{ "audio", NULL, 0 },
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{ "ge3", NULL, 1 },
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{ "ge2", NULL, 2 },
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{ "ge1", NULL, 3 },
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{ "ge0", NULL, 4 },
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{ "pex0", NULL, 5 },
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{ "pex1", NULL, 6 },
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{ "pex2", NULL, 7 },
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{ "pex3", NULL, 8 },
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{ "bp", NULL, 13 },
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{ "sata0lnk", NULL, 14 },
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{ "sata0", "sata0lnk", 15 },
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{ "lcd", NULL, 16 },
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{ "sdio", NULL, 17 },
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{ "usb0", NULL, 18 },
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{ "usb1", NULL, 19 },
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{ "usb2", NULL, 20 },
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{ "xor0", NULL, 22 },
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{ "crypto", NULL, 23 },
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{ "tdm", NULL, 25 },
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{ "xor1", NULL, 28 },
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{ "sata1lnk", NULL, 29 },
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{ "sata1", "sata1lnk", 30 },
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{ }
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};
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#endif
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#ifdef CONFIG_ARCH_DOVE
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static const struct mvebu_soc_descr __initconst dove_gating_descr[] = {
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{ "usb0", NULL, 0 },
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@ -147,6 +205,20 @@ static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
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#endif
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static const __initdata struct of_device_id clk_gating_match[] = {
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#ifdef CONFIG_MACH_ARMADA_370
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{
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.compatible = "marvell,armada-370-gating-clock",
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.data = armada_370_gating_descr,
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},
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#endif
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#ifdef CONFIG_MACH_ARMADA_XP
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{
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.compatible = "marvell,armada-xp-gating-clock",
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.data = armada_xp_gating_descr,
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},
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#endif
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#ifdef CONFIG_ARCH_DOVE
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{
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.compatible = "marvell,dove-gating-clock",
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