kernel: Merge LA.UM.9.15.r1-05300-KAMORTA.0

Android.bp

@@ -9,9 +9,9 @@ cc_binary_host {
 genrule {
     name: "gen-headers_install.sh",
     srcs: ["scripts/headers_install.sh"],
-    tools: ["unifdef"],
     out: ["headers_install.sh"],
-    cmd: "sed 's+scripts/unifdef+$(location unifdef)+g' $(in) > $(out)",
+    // (Ie3b8c36b7d60bd950c28bac566e04f43de78cf98,b/178500203)
+    cmd: "sed 's+scripts/unifdef+$$LOC_UNIFDEF+g' $(in) > $(out)",
 }
 
 cc_prebuilt_binary {

Documentation/admin-guide/kernel-parameters.txt

@@ -483,16 +483,21 @@
 	ccw_timeout_log	[S390]
 			See Documentation/s390/CommonIO for details.
 
-	cgroup_disable=	[KNL] Disable a particular controller
+	cgroup_disable=	[KNL] Disable a particular controller or optional feature
-			Format: {name of the controller(s) to disable}
+			Format: {name of the controller(s) or feature(s) to disable}
 			The effects of cgroup_disable=foo are:
 			- foo isn't auto-mounted if you mount all cgroups in
 			  a single hierarchy
 			- foo isn't visible as an individually mountable
 			  subsystem
+			- if foo is an optional feature then the feature is
+			  disabled and corresponding cgroup files are not
+			  created
 			{Currently only "memory" controller deal with this and
 			cut the overhead, others just disable the usage. So
 			only cgroup_disable=memory is actually worthy}
+			Specifying "pressure" disables per-cgroup pressure
+			stall information accounting feature
 
 	cgroup_no_v1=	[KNL] Disable cgroup controllers and named hierarchies in v1
 			Format: { { controller | "all" | "named" }

Documentation/sysctl/kernel.txt

@@ -720,8 +720,7 @@ allowed to execute.
 perf_event_paranoid:
 
 Controls use of the performance events system by unprivileged
-users (without CAP_SYS_ADMIN).  The default value is 3 if
+users (without CAP_SYS_ADMIN).  The default value is 2.
-CONFIG_SECURITY_PERF_EVENTS_RESTRICT is set, or 2 otherwise.
 
  -1: Allow use of (almost) all events by all users
      Ignore mlock limit after perf_event_mlock_kb without CAP_IPC_LOCK
@@ -729,7 +728,6 @@ CONFIG_SECURITY_PERF_EVENTS_RESTRICT is set, or 2 otherwise.
      Disallow raw tracepoint access by users without CAP_SYS_ADMIN
 >=1: Disallow CPU event access by users without CAP_SYS_ADMIN
 >=2: Disallow kernel profiling by users without CAP_SYS_ADMIN
->=3: Disallow all event access by users without CAP_SYS_ADMIN
 
 ==============================================================
 

MAINTAINERS

@@ -6611,6 +6611,12 @@ F:	drivers/hid/
 F:	include/linux/hid*
 F:	include/uapi/linux/hid*
 
+HID PLAYSTATION DRIVER
+M:	Roderick Colenbrander <roderick.colenbrander@sony.com>
+L:	linux-input@vger.kernel.org
+S:	Supported
+F:	drivers/hid/hid-playstation.c
+
 HID SENSOR HUB DRIVERS
 M:	Jiri Kosina <jikos@kernel.org>
 M:	Jonathan Cameron <jic23@kernel.org>

Makefile

@@ -581,8 +581,12 @@ KBUILD_MODULES :=
 KBUILD_BUILTIN := 1
 
 # If we have only "make modules", don't compile built-in objects.
+# When we're building modules with modversions, we need to consider
+# the built-in objects during the descend as well, in order to
+# make sure the checksums are up to date before we record them.
+
 ifeq ($(MAKECMDGOALS),modules)
-  KBUILD_BUILTIN :=
+  KBUILD_BUILTIN := $(if $(CONFIG_MODVERSIONS),1)
 endif
 
 # If we have "make <whatever> modules", compile modules
@@ -1385,13 +1389,6 @@ ifdef CONFIG_MODULES
 
 all: modules
 
-# When we're building modules with modversions, we need to consider
-# the built-in objects during the descend as well, in order to
-# make sure the checksums are up to date before we record them.
-ifdef CONFIG_MODVERSIONS
-  KBUILD_BUILTIN := 1
-endif
-
 # Build modules
 #
 # A module can be listed more than once in obj-m resulting in

arch/arm/Kconfig

@@ -2128,6 +2128,17 @@ config AUTO_ZRELADDR
 config EFI_STUB
 	bool
 
+config ARM_DECOMPRESSOR_LIMIT
+        hex "Limit the decompressor memory area"
+        default 0x3200000
+        help
+          Allows overriding of the memory size that decompressor maps with
+          read, write and execute permissions to avoid speculative prefetch.
+
+          By default ARM_DECOMPRESSOR_LIMIT maps first 1GB of memory
+          with read, write and execute permissions and reset of the memory
+          as strongly ordered.
+
 config EFI
 	bool "UEFI runtime support"
 	depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL

arch/arm/boot/compressed/head.S

@@ -703,7 +703,7 @@ __setup_mmu:	sub	r3, r4, #16384		@ Page directory size
 		mov	r0, r3
 		mov	r9, r0, lsr #18
 		mov	r9, r9, lsl #18		@ start of RAM
-		add	r10, r9, #0x10000000	@ a reasonable RAM size
+		add	r10, r9, #CONFIG_ARM_DECOMPRESSOR_LIMIT
 		mov	r1, #0x12		@ XN|U + section mapping
 		orr	r1, r1, #3 << 10	@ AP=11
 		add	r2, r3, #16384

arch/arm/configs/vendor/bengal-perf_defconfig

@@ -51,6 +51,8 @@ CONFIG_NR_CPUS=8
 CONFIG_ARM_PSCI=y
 CONFIG_HIGHMEM=y
 CONFIG_SECCOMP=y
+CONFIG_CMDLINE="cgroup_disable=pressure"
+CONFIG_CMDLINE_EXTEND=y
 CONFIG_CPU_FREQ_TIMES=y
 CONFIG_CPU_FREQ_GOV_POWERSAVE=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
@@ -585,7 +587,6 @@ CONFIG_SDCARD_FS=y
 # CONFIG_NETWORK_FILESYSTEMS is not set
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
 CONFIG_SECURITY=y
 CONFIG_LSM_MMAP_MIN_ADDR=4096
 CONFIG_HARDENED_USERCOPY=y

arch/arm/configs/vendor/bengal_defconfig

@@ -54,6 +54,8 @@ CONFIG_NR_CPUS=8
 CONFIG_ARM_PSCI=y
 CONFIG_HIGHMEM=y
 CONFIG_SECCOMP=y
+CONFIG_CMDLINE="cgroup_disable=pressure"
+CONFIG_CMDLINE_EXTEND=y
 CONFIG_EFI=y
 CONFIG_CPU_FREQ_TIMES=y
 CONFIG_CPU_FREQ_GOV_POWERSAVE=y
@@ -638,7 +640,6 @@ CONFIG_SDCARD_FS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
 CONFIG_SECURITY=y
 CONFIG_LSM_MMAP_MIN_ADDR=4096
 CONFIG_HARDENED_USERCOPY=y

arch/arm/configs/vendor/msm8937-perf_defconfig

@@ -0,0 +1,687 @@
+CONFIG_LOCALVERSION="-perf"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_AUDIT=y
+# CONFIG_AUDITSYSCALL is not set
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_SCHED_WALT=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_PSI=y
+CONFIG_RCU_EXPERT=y
+CONFIG_RCU_FAST_NO_HZ=y
+CONFIG_RCU_NOCB_CPU=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKHEADERS=y
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=17
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_BPF=y
+CONFIG_SCHED_CORE_CTL=y
+CONFIG_NAMESPACES=y
+# CONFIG_PID_NS is not set
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_SCHED_TUNE=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+# CONFIG_FHANDLE is not set
+CONFIG_KALLSYMS_ALL=y
+CONFIG_BPF_SYSCALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_ARCH_QCOM=y
+CONFIG_ARCH_QM215=y
+CONFIG_ARCH_MSM8917=y
+CONFIG_ARCH_MSM8937=y
+CONFIG_ARCH_SDM439=y
+CONFIG_ARCH_SDM429=y
+# CONFIG_VDSO is not set
+CONFIG_SMP=y
+CONFIG_SCHED_MC=y
+CONFIG_NR_CPUS=8
+CONFIG_ARM_PSCI=y
+CONFIG_HIGHMEM=y
+CONFIG_SECCOMP=y
+CONFIG_CMDLINE="cgroup_disable=pressure"
+CONFIG_CMDLINE_EXTEND=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TIMES=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_BOOST=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_MSM=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_PM_WAKELOCKS=y
+CONFIG_PM_WAKELOCKS_LIMIT=0
+# CONFIG_PM_WAKELOCKS_GC is not set
+CONFIG_ENERGY_MODEL=y
+CONFIG_MSM_TZ_LOG=y
+CONFIG_ARM_CRYPTO=y
+CONFIG_CRYPTO_SHA1_ARM_NEON=y
+CONFIG_CRYPTO_SHA2_ARM_CE=y
+CONFIG_CRYPTO_AES_ARM_BS=y
+CONFIG_CRYPTO_AES_ARM_CE=y
+CONFIG_CRYPTO_GHASH_ARM_CE=y
+CONFIG_ARCH_MMAP_RND_BITS=16
+CONFIG_PANIC_ON_REFCOUNT_ERROR=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SIG=y
+CONFIG_MODULE_SIG_FORCE=y
+CONFIG_MODULE_SIG_SHA512=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_BLK_DEV_ZONED=y
+CONFIG_BLK_INLINE_ENCRYPTION=y
+CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_CFQ_GROUP_IOSCHED=y
+CONFIG_IOSCHED_BFQ=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_CLEANCACHE=y
+CONFIG_CMA=y
+CONFIG_CMA_DEBUGFS=y
+CONFIG_ZSMALLOC=y
+CONFIG_HAVE_USERSPACE_LOW_MEMORY_KILLER=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_XFRM_INTERFACE=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_NET_IPGRE_DEMUX=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_UDP_DIAG=y
+CONFIG_INET_DIAG_DESTROY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_IPV6_VTI=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_LOG=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_TEE=y
+CONFIG_NETFILTER_XT_TARGET_TPROXY=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_SECMARK=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_BPF=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+# CONFIG_NETFILTER_XT_MATCH_L2TP is not set
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+CONFIG_NETFILTER_XT_MATCH_SOCKET=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_RPFILTER=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_SECURITY=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_RPFILTER=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_BRIDGE_NF_EBTABLES=y
+CONFIG_BRIDGE_EBT_BROUTE=y
+CONFIG_IP_SCTP=y
+CONFIG_L2TP=y
+CONFIG_L2TP_DEBUGFS=y
+CONFIG_L2TP_V3=y
+CONFIG_L2TP_IP=y
+CONFIG_L2TP_ETH=y
+CONFIG_BRIDGE=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_INGRESS=y
+CONFIG_NET_CLS_FW=y
+CONFIG_NET_CLS_U32=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_FLOW=y
+CONFIG_NET_CLS_BPF=y
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_CMP=y
+CONFIG_NET_EMATCH_NBYTE=y
+CONFIG_NET_EMATCH_U32=y
+CONFIG_NET_EMATCH_META=y
+CONFIG_NET_EMATCH_TEXT=y
+CONFIG_NET_CLS_ACT=y
+CONFIG_DNS_RESOLVER=y
+CONFIG_QRTR=y
+CONFIG_QRTR_SMD=y
+CONFIG_BPF_JIT=y
+CONFIG_BT=y
+# CONFIG_BT_BREDR is not set
+# CONFIG_BT_LE is not set
+CONFIG_MSM_BT_POWER=y
+CONFIG_BTFM_SLIM_WCN3990=y
+CONFIG_CFG80211=y
+CONFIG_CFG80211_INTERNAL_REGDB=y
+# CONFIG_CFG80211_CRDA_SUPPORT is not set
+CONFIG_RFKILL=y
+CONFIG_NFC_NQ=y
+CONFIG_FW_LOADER_USER_HELPER=y
+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
+# CONFIG_FW_CACHE is not set
+CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y
+CONFIG_DMA_CMA=y
+CONFIG_ZRAM=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=16
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_HDCP_QSEECOM=y
+CONFIG_QSEECOM=y
+CONFIG_UID_SYS_STATS=y
+CONFIG_FPR_FPC=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_UFSHCD=y
+CONFIG_SCSI_UFSHCD_PLATFORM=y
+CONFIG_SCSI_UFS_QCOM=y
+CONFIG_SCSI_UFS_CRYPTO=y
+CONFIG_SCSI_UFS_CRYPTO_QTI=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=y
+CONFIG_DM_DEFAULT_KEY=y
+CONFIG_DM_SNAPSHOT=y
+CONFIG_DM_UEVENT=y
+CONFIG_DM_VERITY=y
+CONFIG_DM_VERITY_FEC=y
+CONFIG_DM_ANDROID_VERITY=y
+CONFIG_DM_BOW=y
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+CONFIG_TUN=y
+CONFIG_VETH=y
+# CONFIG_NET_VENDOR_AMAZON is not set
+CONFIG_MSM_RMNET_BAM=y
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+CONFIG_RMNET=y
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+CONFIG_PPP=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=y
+CONFIG_PPTP=y
+CONFIG_PPPOL2TP=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_RTL8152=y
+CONFIG_USB_USBNET=y
+# CONFIG_WLAN_VENDOR_ADMTEK is not set
+# CONFIG_WLAN_VENDOR_ATH is not set
+# CONFIG_WLAN_VENDOR_ATMEL is not set
+# CONFIG_WLAN_VENDOR_BROADCOM is not set
+# CONFIG_WLAN_VENDOR_CISCO is not set
+# CONFIG_WLAN_VENDOR_INTEL is not set
+# CONFIG_WLAN_VENDOR_INTERSIL is not set
+# CONFIG_WLAN_VENDOR_MARVELL is not set
+# CONFIG_WLAN_VENDOR_MEDIATEK is not set
+# CONFIG_WLAN_VENDOR_RALINK is not set
+# CONFIG_WLAN_VENDOR_REALTEK is not set
+# CONFIG_WLAN_VENDOR_RSI is not set
+# CONFIG_WLAN_VENDOR_ST is not set
+# CONFIG_WLAN_VENDOR_TI is not set
+# CONFIG_WLAN_VENDOR_ZYDAS is not set
+CONFIG_WCNSS_MEM_PRE_ALLOC=y
+CONFIG_CLD_LL_CORE=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_JOYSTICK_XPAD=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_HBTP_INPUT=y
+CONFIG_INPUT_QPNP_POWER_ON=y
+CONFIG_INPUT_UINPUT=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVMEM is not set
+CONFIG_SERIAL_MSM_HS=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MSM_LEGACY=y
+CONFIG_MSM_SMD_PKT=y
+CONFIG_DIAG_CHAR=y
+CONFIG_MSM_ADSPRPC=y
+CONFIG_MSM_RDBG=m
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MSM_V2=y
+CONFIG_SPI=y
+CONFIG_SPI_QUP=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SPMI=y
+CONFIG_PINCTRL_MSM8937=y
+CONFIG_PINCTRL_MSM8917=y
+CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_QCOM=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_QPNP_SMB5=y
+CONFIG_QPNP_VM_BMS=y
+CONFIG_QPNP_LINEAR_CHARGER=y
+CONFIG_SMB1351_USB_CHARGER=y
+CONFIG_SMB1360_CHARGER_FG=y
+CONFIG_SMB1355_SLAVE_CHARGER=y
+CONFIG_QPNP_QG=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_GOV_LOW_LIMITS=y
+CONFIG_CPU_THERMAL=y
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_QCOM_SPMI_TEMP_ALARM=y
+CONFIG_THERMAL_QPNP_ADC_TM=y
+CONFIG_THERMAL_TSENS=y
+CONFIG_QTI_ADC_TM=y
+CONFIG_QTI_VIRTUAL_SENSOR=y
+CONFIG_QTI_BCL_PMIC5=y
+CONFIG_QTI_BCL_SOC_DRIVER=y
+CONFIG_QTI_QMI_COOLING_DEVICE=y
+CONFIG_REGULATOR_COOLING_DEVICE=y
+CONFIG_MFD_I2C_PMIC=y
+CONFIG_MFD_SPMI_PMIC=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_PROXY_CONSUMER=y
+CONFIG_REGULATOR_QPNP_LABIBB=y
+CONFIG_REGULATOR_QPNP_LCDB=y
+CONFIG_REGULATOR_MEM_ACC=y
+CONFIG_REGULATOR_CPR=y
+CONFIG_REGULATOR_RPM_SMD=y
+CONFIG_REGULATOR_SPM=y
+CONFIG_REGULATOR_STUB=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_MSM_VIDC_3X_GOVERNORS=y
+CONFIG_MSM_VIDC_3X_V4L2=y
+CONFIG_MSM_CAMERA=y
+CONFIG_MSMB_CAMERA=y
+CONFIG_MSM_CAMERA_SENSOR=y
+CONFIG_MSM_CPP=y
+CONFIG_MSM_CCI=y
+CONFIG_MSM_CSI20_HEADER=y
+CONFIG_MSM_CSI22_HEADER=y
+CONFIG_MSM_CSI30_HEADER=y
+CONFIG_MSM_CSI31_HEADER=y
+CONFIG_MSM_CSIPHY=y
+CONFIG_MSM_CSID=y
+CONFIG_MSM_EEPROM=y
+CONFIG_MSM_ISPIF_V2=y
+CONFIG_IMX134=y
+CONFIG_IMX132=y
+CONFIG_OV9724=y
+CONFIG_OV5648=y
+CONFIG_GC0339=y
+CONFIG_OV8825=y
+CONFIG_OV8865=y
+CONFIG_s5k4e1=y
+CONFIG_OV12830=y
+CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y
+CONFIG_MSMB_JPEG=y
+CONFIG_MSM_FD=y
+CONFIG_RADIO_IRIS=y
+CONFIG_RADIO_IRIS_TRANSPORT=y
+CONFIG_FB=y
+CONFIG_FB_MSM=y
+CONFIG_FB_MSM_MDSS=y
+CONFIG_FB_MSM_MDSS_WRITEBACK=y
+CONFIG_FB_MSM_MDSS_DSI_CTRL_STATUS=y
+CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_UHID=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_ELECOM=y
+CONFIG_HID_MAGICMOUSE=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MULTITOUCH=y
+CONFIG_HID_SONY=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_MON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_EHCI_MSM=y
+CONFIG_USB_ACM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_ISD200=y
+CONFIG_USB_STORAGE_USBAT=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_USB_STORAGE_ALAUDA=y
+CONFIG_USB_STORAGE_ONETOUCH=y
+CONFIG_USB_STORAGE_KARMA=y
+CONFIG_USB_STORAGE_CYPRESS_ATACB=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_EHSET_TEST_FIXTURE=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_USB_CI13XXX_MSM=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_UEVENT=y
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_RMNET_BAM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_ACC=y
+CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y
+CONFIG_USB_CONFIGFS_F_MIDI=y
+CONFIG_USB_CONFIGFS_F_HID=y
+CONFIG_USB_CONFIGFS_F_DIAG=y
+CONFIG_USB_CONFIGFS_F_CDEV=y
+CONFIG_USB_CONFIGFS_F_CCID=y
+CONFIG_USB_CONFIGFS_F_QDSS=y
+CONFIG_USB_CONFIGFS_F_MTP=y
+CONFIG_USB_CONFIGFS_F_PTP=y
+CONFIG_TYPEC=y
+CONFIG_MMC=y
+# CONFIG_PWRSEQ_EMMC is not set
+# CONFIG_PWRSEQ_SIMPLE is not set
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_BLOCK_DEFERRED_RESUME=y
+CONFIG_MMC_IPC_LOGGING=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_MSM=y
+CONFIG_MMC_CQHCI_CRYPTO=y
+CONFIG_MMC_CQHCI_CRYPTO_QTI=y
+CONFIG_LEDS_QTI_TRI_LED=y
+CONFIG_LEDS_QPNP_FLASH_V2=y
+CONFIG_LEDS_QPNP_VIBRATOR_LDO=y
+CONFIG_LEDS_QPNP_VIBRATOR=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_EDAC=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PM8XXX=y
+CONFIG_DMADEVICES=y
+CONFIG_QCOM_SPS_DMA=y
+CONFIG_UIO=y
+CONFIG_UIO_MSM_SHAREDMEM=y
+CONFIG_STAGING=y
+CONFIG_ASHMEM=y
+CONFIG_ION=y
+CONFIG_ION_POOL_AUTO_REFILL=y
+CONFIG_QPNP_REVID=y
+CONFIG_SPS=y
+CONFIG_SPS_SUPPORT_NDP_BAM=y
+CONFIG_IPA=y
+CONFIG_RMNET_IPA=y
+CONFIG_RNDIS_IPA=y
+CONFIG_USB_BAM=y
+CONFIG_MDSS_PLL=y
+CONFIG_QCOM_CLK_SMD_RPM=y
+CONFIG_SDM_GCC_429W=y
+CONFIG_SDM_DEBUGCC_429W=y
+CONFIG_CLOCK_CPU_SDM=y
+CONFIG_SDM_DEBUGCC_439=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_QCOM=y
+CONFIG_MAILBOX=y
+CONFIG_ARM_SMMU=y
+CONFIG_QCOM_LAZY_MAPPING=y
+CONFIG_RPMSG_CHAR=y
+CONFIG_RPMSG_QCOM_GLINK_RPM=y
+CONFIG_RPMSG_QCOM_GLINK_SMEM=y
+CONFIG_RPMSG_QCOM_SMD=y
+CONFIG_MSM_RPM_SMD=y
+CONFIG_QCOM_CPUSS_DUMP=y
+CONFIG_QCOM_RUN_QUEUE_STATS=y
+CONFIG_QCOM_QMI_HELPERS=y
+CONFIG_QCOM_SMEM=y
+CONFIG_QCOM_SMD_RPM=y
+CONFIG_MSM_SPM=y
+CONFIG_MSM_L2_SPM=y
+CONFIG_QCOM_EARLY_RANDOM=y
+CONFIG_QCOM_MEMORY_DUMP_V2=y
+CONFIG_QCOM_SMP2P=y
+CONFIG_QCOM_SMSM=y
+CONFIG_MSM_PIL_MSS_QDSP6V5=y
+CONFIG_QCOM_SECURE_BUFFER=y
+CONFIG_MSM_TZ_SMMU=y
+CONFIG_MSM_SUBSYSTEM_RESTART=y
+CONFIG_MSM_PIL=y
+CONFIG_MSM_SYSMON_QMI_COMM=y
+CONFIG_MSM_PIL_SSR_GENERIC=y
+CONFIG_MSM_BOOT_STATS=y
+CONFIG_MSM_CORE_HANG_DETECT=y
+CONFIG_QCOM_WATCHDOG_V2=y
+CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
+CONFIG_QCOM_BUS_SCALING=y
+CONFIG_QCOM_GLINK=y
+CONFIG_MSM_EVENT_TIMER=y
+CONFIG_MSM_PM=y
+CONFIG_QCOM_DCC=y
+CONFIG_QTI_RPM_STATS_LOG=y
+CONFIG_QTEE_SHM_BRIDGE=y
+CONFIG_MEM_SHARE_QMI_SERVICE=y
+CONFIG_MSM_PERFORMANCE=y
+CONFIG_QTI_CRYPTO_COMMON=y
+CONFIG_QTI_CRYPTO_TZ=y
+CONFIG_MSM_BAM_DMUX=y
+CONFIG_WCNSS_CORE=y
+CONFIG_WCNSS_CORE_PRONTO=y
+CONFIG_WCNSS_REGISTER_DUMP_ON_BITE=y
+CONFIG_DEVFREQ_GOV_PASSIVE=y
+CONFIG_QCOM_BIMC_BWMON=y
+CONFIG_ARM_MEMLAT_MON=y
+CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y
+CONFIG_DEVFREQ_GOV_MEMLAT=y
+CONFIG_DEVFREQ_SIMPLE_DEV=y
+CONFIG_QCOM_DEVFREQ_DEVBW=y
+CONFIG_IIO=y
+CONFIG_QCOM_SPMI_ADC5=y
+CONFIG_QCOM_SPMI_VADC=y
+CONFIG_PWM=y
+CONFIG_PWM_QTI_LPG=y
+CONFIG_QCOM_SHOW_RESUME_IRQ=y
+CONFIG_QCOM_MPM=y
+CONFIG_RAS=y
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_BINDERFS=y
+CONFIG_QCOM_QFPROM=y
+CONFIG_SLIMBUS_MSM_NGD=y
+CONFIG_SENSORS_SSC=y
+CONFIG_QCOM_KGSL=y
+CONFIG_LEGACY_ENERGY_MODEL_DT=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXT4_ENCRYPTION=y
+CONFIG_F2FS_FS=y
+CONFIG_F2FS_FS_SECURITY=y
+CONFIG_F2FS_FS_ENCRYPTION=y
+CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
+CONFIG_FS_VERITY=y
+CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+CONFIG_QFMT_V2=y
+CONFIG_FUSE_FS=y
+CONFIG_OVERLAY_FS=y
+CONFIG_INCREMENTAL_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_SDCARD_FS=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_SECURITY=y
+CONFIG_LSM_MMAP_MIN_ADDR=4096
+CONFIG_HARDENED_USERCOPY=y
+CONFIG_HARDENED_USERCOPY_PAGESPAN=y
+CONFIG_FORTIFY_SOURCE=y
+CONFIG_STATIC_USERMODEHELPER=y
+CONFIG_STATIC_USERMODEHELPER_PATH=""
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SMACK=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_XCBC=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_LZ4=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_DEV_QCE=y
+CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y
+CONFIG_CRYPTO_DEV_QCRYPTO=y
+CONFIG_CRYPTO_DEV_QCEDEV=y
+CONFIG_CRYPTO_DEV_QCOM_ICE=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+CONFIG_FRAME_WARN=2048
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_WQ_WATCHDOG=y
+CONFIG_PANIC_ON_OOPS=y
+CONFIG_PANIC_TIMEOUT=5
+CONFIG_SCHEDSTATS=y
+CONFIG_SCHED_STACK_END_CHECK=y
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_FAULT_INJECTION=y
+CONFIG_FAIL_PAGE_ALLOC=y
+CONFIG_IPC_LOGGING=y
+# CONFIG_FTRACE is not set
+CONFIG_LKDTM=m
+CONFIG_BUG_ON_DATA_CORRUPTION=y
+CONFIG_CORESIGHT=y
+CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
+CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
+CONFIG_CORESIGHT_STM=y
+CONFIG_CORESIGHT_CTI=y
+CONFIG_CORESIGHT_TPDA=y
+CONFIG_CORESIGHT_TPDM=y
+CONFIG_CORESIGHT_HWEVENT=y
+CONFIG_CORESIGHT_DUMMY=y
+CONFIG_CORESIGHT_REMOTE_ETM=y
+CONFIG_CORESIGHT_TGU=y

arch/arm/configs/vendor/msm8937_32go-perf_defconfig

@@ -1,7 +1,6 @@
 CONFIG_LOCALVERSION="-perf"
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_AUDIT=y
-# CONFIG_AUDITSYSCALL is not set
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
@@ -16,18 +15,17 @@ CONFIG_RCU_FAST_NO_HZ=y
 CONFIG_RCU_NOCB_CPU=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
+CONFIG_IKHEADERS=y
 CONFIG_LOG_CPU_MAX_BUF_SHIFT=17
 CONFIG_MEMCG=y
 CONFIG_MEMCG_SWAP=y
 CONFIG_BLK_CGROUP=y
-CONFIG_RT_GROUP_SCHED=y
 CONFIG_CGROUP_FREEZER=y
 CONFIG_CPUSETS=y
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_CGROUP_BPF=y
 CONFIG_SCHED_CORE_CTL=y
 CONFIG_NAMESPACES=y
-# CONFIG_UTS_NS is not set
 # CONFIG_PID_NS is not set
 CONFIG_SCHED_AUTOGROUP=y
 CONFIG_SCHED_TUNE=y
@@ -37,7 +35,6 @@ CONFIG_BLK_DEV_INITRD=y
 # CONFIG_RD_XZ is not set
 # CONFIG_RD_LZO is not set
 # CONFIG_RD_LZ4 is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 # CONFIG_FHANDLE is not set
 # CONFIG_BASE_FULL is not set
 CONFIG_KALLSYMS_ALL=y
@@ -49,6 +46,9 @@ CONFIG_PROFILING=y
 CONFIG_ARCH_QCOM=y
 CONFIG_ARCH_QM215=y
 CONFIG_ARCH_MSM8917=y
+CONFIG_ARCH_MSM8937=y
+CONFIG_ARCH_SDM439=y
+CONFIG_ARCH_SDM429=y
 # CONFIG_VDSO is not set
 CONFIG_SMP=y
 CONFIG_SCHED_MC=y
@@ -56,7 +56,8 @@ CONFIG_NR_CPUS=8
 CONFIG_ARM_PSCI=y
 CONFIG_HIGHMEM=y
 CONFIG_SECCOMP=y
-CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y
+CONFIG_CMDLINE="cgroup_disable=pressure"
+CONFIG_CMDLINE_EXTEND=y
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_TIMES=y
 CONFIG_CPU_FREQ_GOV_POWERSAVE=y
@@ -80,26 +81,22 @@ CONFIG_CRYPTO_SHA1_ARM_NEON=y
 CONFIG_CRYPTO_SHA2_ARM_CE=y
 CONFIG_CRYPTO_AES_ARM_BS=y
 CONFIG_CRYPTO_AES_ARM_CE=y
-CONFIG_CRYPTO_GHASH_ARM_CE=y
 CONFIG_ARCH_MMAP_RND_BITS=16
 CONFIG_PANIC_ON_REFCOUNT_ERROR=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SIG=y
 CONFIG_MODULE_SIG_FORCE=y
 CONFIG_MODULE_SIG_SHA512=y
-# CONFIG_BLK_DEV_BSG is not set
 CONFIG_BLK_DEV_ZONED=y
 CONFIG_BLK_INLINE_ENCRYPTION=y
 CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y
 CONFIG_PARTITION_ADVANCED=y
 # CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_CFQ_GROUP_IOSCHED=y
 CONFIG_IOSCHED_BFQ=y
+CONFIG_BFQ_GROUP_IOSCHED=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_CLEANCACHE=y
 CONFIG_CMA=y
 CONFIG_CMA_DEBUGFS=y
 CONFIG_ZSMALLOC=y
@@ -239,9 +236,9 @@ CONFIG_NET_EMATCH_U32=y
 CONFIG_NET_EMATCH_META=y
 CONFIG_NET_EMATCH_TEXT=y
 CONFIG_NET_CLS_ACT=y
-CONFIG_DNS_RESOLVER=y
 CONFIG_QRTR=y
 CONFIG_QRTR_SMD=y
+CONFIG_BPF_JIT=y
 CONFIG_BT=y
 # CONFIG_BT_BREDR is not set
 # CONFIG_BT_LE is not set
@@ -280,6 +277,8 @@ CONFIG_SCSI_UFS_CRYPTO_QTI=y
 CONFIG_MD=y
 CONFIG_BLK_DEV_DM=y
 CONFIG_DM_CRYPT=y
+CONFIG_DM_DEFAULT_KEY=y
+CONFIG_DM_SNAPSHOT=y
 CONFIG_DM_UEVENT=y
 CONFIG_DM_VERITY=y
 CONFIG_DM_VERITY_FEC=y
@@ -289,11 +288,14 @@ CONFIG_DM_BOW=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
 CONFIG_TUN=y
+CONFIG_VETH=y
 # CONFIG_NET_VENDOR_AMAZON is not set
+CONFIG_MSM_RMNET_BAM=y
 # CONFIG_NET_VENDOR_EZCHIP is not set
 # CONFIG_NET_VENDOR_HISILICON is not set
 # CONFIG_NET_VENDOR_MARVELL is not set
 # CONFIG_NET_VENDOR_NETRONOME is not set
+CONFIG_RMNET=y
 # CONFIG_NET_VENDOR_ROCKER is not set
 # CONFIG_NET_VENDOR_SYNOPSYS is not set
 CONFIG_PPP=y
@@ -330,6 +332,7 @@ CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_JOYSTICK=y
+CONFIG_JOYSTICK_XPAD=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_HBTP_INPUT=y
 CONFIG_INPUT_QPNP_POWER_ON=y
@@ -358,9 +361,11 @@ CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_QCOM=y
-CONFIG_POWER_RESET_SYSCON=y
 CONFIG_QPNP_SMB5=y
+CONFIG_QPNP_VM_BMS=y
+CONFIG_QPNP_LINEAR_CHARGER=y
 CONFIG_SMB1351_USB_CHARGER=y
+CONFIG_SMB1360_CHARGER_FG=y
 CONFIG_SMB1355_SLAVE_CHARGER=y
 CONFIG_QPNP_QG=y
 CONFIG_THERMAL=y
@@ -369,7 +374,10 @@ CONFIG_THERMAL_GOV_USER_SPACE=y
 CONFIG_THERMAL_GOV_LOW_LIMITS=y
 CONFIG_CPU_THERMAL=y
 CONFIG_DEVFREQ_THERMAL=y
+CONFIG_QCOM_SPMI_TEMP_ALARM=y
+CONFIG_THERMAL_QPNP_ADC_TM=y
 CONFIG_THERMAL_TSENS=y
+CONFIG_QTI_ADC_TM=y
 CONFIG_QTI_VIRTUAL_SENSOR=y
 CONFIG_QTI_BCL_PMIC5=y
 CONFIG_QTI_BCL_SOC_DRIVER=y
@@ -421,6 +429,8 @@ CONFIG_OV12830=y
 CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y
 CONFIG_MSMB_JPEG=y
 CONFIG_MSM_FD=y
+CONFIG_RADIO_IRIS=y
+CONFIG_RADIO_IRIS_TRANSPORT=y
 CONFIG_FB=y
 CONFIG_FB_MSM=y
 CONFIG_FB_MSM_MDSS=y
@@ -441,9 +451,9 @@ CONFIG_HID_ELECOM=y
 CONFIG_HID_MAGICMOUSE=y
 CONFIG_HID_MICROSOFT=y
 CONFIG_HID_MULTITOUCH=y
+CONFIG_HID_NINTENDO=y
 CONFIG_HID_SONY=y
 CONFIG_USB_HIDDEV=y
-CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_MON=y
 CONFIG_USB_EHCI_HCD=y
@@ -494,7 +504,6 @@ CONFIG_MMC=y
 # CONFIG_PWRSEQ_SIMPLE is not set
 CONFIG_MMC_BLOCK_MINORS=32
 CONFIG_MMC_BLOCK_DEFERRED_RESUME=y
-CONFIG_MMC_IPC_LOGGING=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_MSM=y
@@ -503,9 +512,11 @@ CONFIG_MMC_CQHCI_CRYPTO_QTI=y
 CONFIG_LEDS_QTI_TRI_LED=y
 CONFIG_LEDS_QPNP_FLASH_V2=y
 CONFIG_LEDS_QPNP_VIBRATOR_LDO=y
+CONFIG_LEDS_QPNP_VIBRATOR=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_EDAC=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PM8XXX=y
 CONFIG_DMADEVICES=y
 CONFIG_QCOM_SPS_DMA=y
 CONFIG_UIO=y
@@ -520,11 +531,13 @@ CONFIG_SPS_SUPPORT_NDP_BAM=y
 CONFIG_IPA=y
 CONFIG_RMNET_IPA=y
 CONFIG_RNDIS_IPA=y
+CONFIG_USB_BAM=y
 CONFIG_MDSS_PLL=y
 CONFIG_QCOM_CLK_SMD_RPM=y
 CONFIG_SDM_GCC_429W=y
 CONFIG_SDM_DEBUGCC_429W=y
 CONFIG_CLOCK_CPU_SDM=y
+CONFIG_SDM_DEBUGCC_439=y
 CONFIG_HWSPINLOCK=y
 CONFIG_HWSPINLOCK_QCOM=y
 CONFIG_MAILBOX=y
@@ -535,7 +548,6 @@ CONFIG_RPMSG_QCOM_GLINK_RPM=y
 CONFIG_RPMSG_QCOM_GLINK_SMEM=y
 CONFIG_RPMSG_QCOM_SMD=y
 CONFIG_MSM_RPM_SMD=y
-CONFIG_QCOM_CPUSS_DUMP=y
 CONFIG_QCOM_RUN_QUEUE_STATS=y
 CONFIG_QCOM_QMI_HELPERS=y
 CONFIG_QCOM_SMEM=y
@@ -548,28 +560,29 @@ CONFIG_QCOM_SMP2P=y
 CONFIG_QCOM_SMSM=y
 CONFIG_MSM_PIL_MSS_QDSP6V5=y
 CONFIG_QCOM_SECURE_BUFFER=y
+CONFIG_MSM_TZ_SMMU=y
 CONFIG_MSM_SUBSYSTEM_RESTART=y
 CONFIG_MSM_PIL=y
+CONFIG_MSM_SYSMON_QMI_COMM=y
 CONFIG_MSM_PIL_SSR_GENERIC=y
 CONFIG_MSM_BOOT_STATS=y
-CONFIG_QCOM_DCC_V2=y
-CONFIG_MSM_CORE_HANG_DETECT=y
 CONFIG_QCOM_WATCHDOG_V2=y
 CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
 CONFIG_QCOM_BUS_SCALING=y
 CONFIG_QCOM_GLINK=y
 CONFIG_MSM_EVENT_TIMER=y
 CONFIG_MSM_PM=y
+CONFIG_QCOM_DCC=y
 CONFIG_QTI_RPM_STATS_LOG=y
 CONFIG_QTEE_SHM_BRIDGE=y
 CONFIG_MEM_SHARE_QMI_SERVICE=y
 CONFIG_MSM_PERFORMANCE=y
 CONFIG_QTI_CRYPTO_COMMON=y
 CONFIG_QTI_CRYPTO_TZ=y
+CONFIG_MSM_BAM_DMUX=y
 CONFIG_WCNSS_CORE=y
 CONFIG_WCNSS_CORE_PRONTO=y
 CONFIG_WCNSS_REGISTER_DUMP_ON_BITE=y
-CONFIG_DEVFREQ_GOV_PASSIVE=y
 CONFIG_QCOM_BIMC_BWMON=y
 CONFIG_ARM_MEMLAT_MON=y
 CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y
@@ -577,6 +590,8 @@ CONFIG_DEVFREQ_GOV_MEMLAT=y
 CONFIG_DEVFREQ_SIMPLE_DEV=y
 CONFIG_QCOM_DEVFREQ_DEVBW=y
 CONFIG_IIO=y
+CONFIG_QCOM_SPMI_ADC5=y
+CONFIG_QCOM_SPMI_VADC=y
 CONFIG_PWM=y
 CONFIG_PWM_QTI_LPG=y
 CONFIG_QCOM_SHOW_RESUME_IRQ=y
@@ -616,23 +631,18 @@ CONFIG_SQUASHFS_LZ4=y
 # CONFIG_NETWORK_FILESYSTEMS is not set
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
 CONFIG_SECURITY=y
 CONFIG_LSM_MMAP_MIN_ADDR=4096
 CONFIG_HARDENED_USERCOPY=y
-CONFIG_HARDENED_USERCOPY_PAGESPAN=y
-CONFIG_FORTIFY_SOURCE=y
 CONFIG_STATIC_USERMODEHELPER=y
 CONFIG_STATIC_USERMODEHELPER_PATH=""
 CONFIG_SECURITY_SELINUX=y
 CONFIG_SECURITY_SMACK=y
 CONFIG_CRYPTO_GCM=y
 CONFIG_CRYPTO_XCBC=y
-CONFIG_CRYPTO_MD4=y
 CONFIG_CRYPTO_TWOFISH=y
 CONFIG_CRYPTO_LZ4=y
 CONFIG_CRYPTO_ANSI_CPRNG=y
-CONFIG_CRYPTO_DEV_QCE=y
 CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y
 CONFIG_CRYPTO_DEV_QCRYPTO=y
 CONFIG_CRYPTO_DEV_QCEDEV=y
@@ -642,14 +652,19 @@ CONFIG_DEBUG_INFO=y
 CONFIG_FRAME_WARN=2048
 CONFIG_DEBUG_FS=y
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_WQ_WATCHDOG=y
-CONFIG_PANIC_ON_OOPS=y
 CONFIG_PANIC_TIMEOUT=5
 CONFIG_SCHED_STACK_END_CHECK=y
 # CONFIG_DEBUG_PREEMPT is not set
-CONFIG_FAULT_INJECTION=y
-CONFIG_FAIL_PAGE_ALLOC=y
 CONFIG_IPC_LOGGING=y
 # CONFIG_FTRACE is not set
-CONFIG_LKDTM=m
 CONFIG_BUG_ON_DATA_CORRUPTION=y
+CONFIG_CORESIGHT=y
+CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
+CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
+CONFIG_CORESIGHT_STM=y
+CONFIG_CORESIGHT_TPDA=y
+CONFIG_CORESIGHT_TPDM=y
+CONFIG_CORESIGHT_HWEVENT=y
+CONFIG_CORESIGHT_DUMMY=y
+CONFIG_CORESIGHT_REMOTE_ETM=y
+CONFIG_CORESIGHT_TGU=y

arch/arm/configs/vendor/msm8937_32go_defconfig

@@ -1,6 +1,5 @@
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_AUDIT=y
-# CONFIG_AUDITSYSCALL is not set
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
@@ -16,12 +15,11 @@ CONFIG_RCU_FAST_NO_HZ=y
 CONFIG_RCU_NOCB_CPU=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
+CONFIG_IKHEADERS=y
 CONFIG_LOG_CPU_MAX_BUF_SHIFT=17
 CONFIG_MEMCG=y
 CONFIG_MEMCG_SWAP=y
 CONFIG_BLK_CGROUP=y
-CONFIG_DEBUG_BLK_CGROUP=y
-CONFIG_RT_GROUP_SCHED=y
 CONFIG_CGROUP_FREEZER=y
 CONFIG_CPUSETS=y
 CONFIG_CGROUP_CPUACCT=y
@@ -29,7 +27,6 @@ CONFIG_CGROUP_BPF=y
 CONFIG_CGROUP_DEBUG=y
 CONFIG_SCHED_CORE_CTL=y
 CONFIG_NAMESPACES=y
-# CONFIG_UTS_NS is not set
 # CONFIG_PID_NS is not set
 CONFIG_SCHED_AUTOGROUP=y
 CONFIG_SCHED_TUNE=y
@@ -39,7 +36,6 @@ CONFIG_BLK_DEV_INITRD=y
 # CONFIG_RD_XZ is not set
 # CONFIG_RD_LZO is not set
 # CONFIG_RD_LZ4 is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 # CONFIG_FHANDLE is not set
 # CONFIG_BASE_FULL is not set
 CONFIG_KALLSYMS_ALL=y
@@ -50,6 +46,9 @@ CONFIG_PROFILING=y
 CONFIG_ARCH_QCOM=y
 CONFIG_ARCH_QM215=y
 CONFIG_ARCH_MSM8917=y
+CONFIG_ARCH_MSM8937=y
+CONFIG_ARCH_SDM439=y
+CONFIG_ARCH_SDM429=y
 # CONFIG_VDSO is not set
 CONFIG_SMP=y
 CONFIG_SCHED_MC=y
@@ -57,7 +56,8 @@ CONFIG_NR_CPUS=8
 CONFIG_ARM_PSCI=y
 CONFIG_HIGHMEM=y
 CONFIG_SECCOMP=y
-CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y
+CONFIG_CMDLINE="cgroup_disable=pressure"
+CONFIG_CMDLINE_EXTEND=y
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_TIMES=y
 CONFIG_CPU_FREQ_GOV_POWERSAVE=y
@@ -82,28 +82,24 @@ CONFIG_CRYPTO_SHA1_ARM_NEON=y
 CONFIG_CRYPTO_SHA2_ARM_CE=y
 CONFIG_CRYPTO_AES_ARM_BS=y
 CONFIG_CRYPTO_AES_ARM_CE=y
-CONFIG_CRYPTO_GHASH_ARM_CE=y
 CONFIG_OPROFILE=m
 CONFIG_KPROBES=y
 CONFIG_ARCH_MMAP_RND_BITS=16
 CONFIG_PANIC_ON_REFCOUNT_ERROR=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SIG=y
 CONFIG_MODULE_SIG_FORCE=y
 CONFIG_MODULE_SIG_SHA512=y
-# CONFIG_BLK_DEV_BSG is not set
 CONFIG_BLK_DEV_ZONED=y
 CONFIG_BLK_INLINE_ENCRYPTION=y
 CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y
 CONFIG_PARTITION_ADVANCED=y
 # CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_CFQ_GROUP_IOSCHED=y
 CONFIG_IOSCHED_BFQ=y
+CONFIG_BFQ_GROUP_IOSCHED=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_CLEANCACHE=y
 CONFIG_CMA=y
 CONFIG_CMA_DEBUGFS=y
 CONFIG_ZSMALLOC=y
@@ -246,6 +242,7 @@ CONFIG_NET_CLS_ACT=y
 CONFIG_DNS_RESOLVER=y
 CONFIG_QRTR=y
 CONFIG_QRTR_SMD=y
+CONFIG_BPF_JIT=y
 CONFIG_BT=y
 # CONFIG_BT_BREDR is not set
 # CONFIG_BT_LE is not set
@@ -285,6 +282,8 @@ CONFIG_SCSI_UFS_CRYPTO_QTI=y
 CONFIG_MD=y
 CONFIG_BLK_DEV_DM=y
 CONFIG_DM_CRYPT=y
+CONFIG_DM_DEFAULT_KEY=y
+CONFIG_DM_SNAPSHOT=y
 CONFIG_DM_UEVENT=y
 CONFIG_DM_VERITY=y
 CONFIG_DM_VERITY_FEC=y
@@ -294,11 +293,14 @@ CONFIG_DM_BOW=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
 CONFIG_TUN=y
+CONFIG_VETH=y
 # CONFIG_NET_VENDOR_AMAZON is not set
+CONFIG_MSM_RMNET_BAM=y
 # CONFIG_NET_VENDOR_EZCHIP is not set
 # CONFIG_NET_VENDOR_HISILICON is not set
 # CONFIG_NET_VENDOR_MARVELL is not set
 # CONFIG_NET_VENDOR_NETRONOME is not set
+CONFIG_RMNET=y
 # CONFIG_NET_VENDOR_ROCKER is not set
 # CONFIG_NET_VENDOR_SYNOPSYS is not set
 CONFIG_PPP=y
@@ -335,6 +337,7 @@ CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_JOYSTICK=y
+CONFIG_JOYSTICK_XPAD=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_HBTP_INPUT=y
 CONFIG_INPUT_QPNP_POWER_ON=y
@@ -366,7 +369,10 @@ CONFIG_GPIO_SYSFS=y
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_QCOM=y
 CONFIG_QPNP_SMB5=y
+CONFIG_QPNP_VM_BMS=y
+CONFIG_QPNP_LINEAR_CHARGER=y
 CONFIG_SMB1351_USB_CHARGER=y
+CONFIG_SMB1360_CHARGER_FG=y
 CONFIG_SMB1355_SLAVE_CHARGER=y
 CONFIG_QPNP_QG=y
 CONFIG_THERMAL=y
@@ -375,7 +381,10 @@ CONFIG_THERMAL_GOV_USER_SPACE=y
 CONFIG_THERMAL_GOV_LOW_LIMITS=y
 CONFIG_CPU_THERMAL=y
 CONFIG_DEVFREQ_THERMAL=y
+CONFIG_QCOM_SPMI_TEMP_ALARM=y
+CONFIG_THERMAL_QPNP_ADC_TM=y
 CONFIG_THERMAL_TSENS=y
+CONFIG_QTI_ADC_TM=y
 CONFIG_QTI_VIRTUAL_SENSOR=y
 CONFIG_QTI_BCL_PMIC5=y
 CONFIG_QTI_BCL_SOC_DRIVER=y
@@ -427,6 +436,8 @@ CONFIG_OV12830=y
 CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y
 CONFIG_MSMB_JPEG=y
 CONFIG_MSM_FD=y
+CONFIG_RADIO_IRIS=y
+CONFIG_RADIO_IRIS_TRANSPORT=y
 CONFIG_FB=y
 CONFIG_FB_VIRTUAL=y
 CONFIG_FB_MSM=y
@@ -448,9 +459,9 @@ CONFIG_HID_ELECOM=y
 CONFIG_HID_MAGICMOUSE=y
 CONFIG_HID_MICROSOFT=y
 CONFIG_HID_MULTITOUCH=y
+CONFIG_HID_NINTENDO=y
 CONFIG_HID_SONY=y
 CONFIG_USB_HIDDEV=y
-CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_MON=y
 CONFIG_USB_EHCI_HCD=y
@@ -510,9 +521,11 @@ CONFIG_MMC_CQHCI_CRYPTO_QTI=y
 CONFIG_LEDS_QTI_TRI_LED=y
 CONFIG_LEDS_QPNP_FLASH_V2=y
 CONFIG_LEDS_QPNP_VIBRATOR_LDO=y
+CONFIG_LEDS_QPNP_VIBRATOR=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_EDAC=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PM8XXX=y
 CONFIG_DMADEVICES=y
 CONFIG_QCOM_SPS_DMA=y
 CONFIG_UIO=y
@@ -528,11 +541,13 @@ CONFIG_SPS_SUPPORT_NDP_BAM=y
 CONFIG_IPA=y
 CONFIG_RMNET_IPA=y
 CONFIG_RNDIS_IPA=y
+CONFIG_USB_BAM=y
 CONFIG_MDSS_PLL=y
 CONFIG_QCOM_CLK_SMD_RPM=y
 CONFIG_SDM_GCC_429W=y
 CONFIG_SDM_DEBUGCC_429W=y
 CONFIG_CLOCK_CPU_SDM=y
+CONFIG_SDM_DEBUGCC_439=y
 CONFIG_HWSPINLOCK=y
 CONFIG_HWSPINLOCK_QCOM=y
 CONFIG_MAILBOX=y
@@ -554,15 +569,17 @@ CONFIG_MSM_SPM=y
 CONFIG_MSM_L2_SPM=y
 CONFIG_QCOM_EARLY_RANDOM=y
 CONFIG_QCOM_MEMORY_DUMP_V2=y
+CONFIG_MSM_DEBUG_LAR_UNLOCK=y
 CONFIG_QCOM_SMP2P=y
 CONFIG_QCOM_SMSM=y
 CONFIG_MSM_PIL_MSS_QDSP6V5=y
 CONFIG_QCOM_SECURE_BUFFER=y
+CONFIG_MSM_TZ_SMMU=y
 CONFIG_MSM_SUBSYSTEM_RESTART=y
 CONFIG_MSM_PIL=y
+CONFIG_MSM_SYSMON_QMI_COMM=y
 CONFIG_MSM_PIL_SSR_GENERIC=y
 CONFIG_MSM_BOOT_STATS=y
-CONFIG_QCOM_DCC_V2=y
 CONFIG_MSM_CORE_HANG_DETECT=y
 CONFIG_QCOM_WATCHDOG_V2=y
 CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
@@ -570,16 +587,17 @@ CONFIG_QCOM_BUS_SCALING=y
 CONFIG_QCOM_GLINK=y
 CONFIG_MSM_EVENT_TIMER=y
 CONFIG_MSM_PM=y
+CONFIG_QCOM_DCC=y
 CONFIG_QTI_RPM_STATS_LOG=y
 CONFIG_QTEE_SHM_BRIDGE=y
 CONFIG_MEM_SHARE_QMI_SERVICE=y
 CONFIG_MSM_PERFORMANCE=y
 CONFIG_QTI_CRYPTO_COMMON=y
 CONFIG_QTI_CRYPTO_TZ=y
+CONFIG_MSM_BAM_DMUX=y
 CONFIG_WCNSS_CORE=y
 CONFIG_WCNSS_CORE_PRONTO=y
 CONFIG_WCNSS_REGISTER_DUMP_ON_BITE=y
-CONFIG_DEVFREQ_GOV_PASSIVE=y
 CONFIG_QCOM_BIMC_BWMON=y
 CONFIG_ARM_MEMLAT_MON=y
 CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y
@@ -587,6 +605,8 @@ CONFIG_DEVFREQ_GOV_MEMLAT=y
 CONFIG_DEVFREQ_SIMPLE_DEV=y
 CONFIG_QCOM_DEVFREQ_DEVBW=y
 CONFIG_IIO=y
+CONFIG_QCOM_SPMI_ADC5=y
+CONFIG_QCOM_SPMI_VADC=y
 CONFIG_PWM=y
 CONFIG_PWM_QTI_LPG=y
 CONFIG_QCOM_SHOW_RESUME_IRQ=y
@@ -596,7 +616,6 @@ CONFIG_ANDROID=y
 CONFIG_ANDROID_BINDER_IPC=y
 CONFIG_ANDROID_BINDERFS=y
 CONFIG_QCOM_QFPROM=y
-CONFIG_STM=y
 CONFIG_SLIMBUS_MSM_NGD=y
 CONFIG_SENSORS_SSC=y
 CONFIG_QCOM_KGSL=y
@@ -628,23 +647,18 @@ CONFIG_SQUASHFS_LZ4=y
 # CONFIG_NETWORK_FILESYSTEMS is not set
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
 CONFIG_SECURITY=y
 CONFIG_LSM_MMAP_MIN_ADDR=4096
 CONFIG_HARDENED_USERCOPY=y
-CONFIG_HARDENED_USERCOPY_PAGESPAN=y
-CONFIG_FORTIFY_SOURCE=y
 CONFIG_STATIC_USERMODEHELPER=y
 CONFIG_STATIC_USERMODEHELPER_PATH=""
 CONFIG_SECURITY_SELINUX=y
 CONFIG_SECURITY_SMACK=y
 CONFIG_CRYPTO_GCM=y
 CONFIG_CRYPTO_XCBC=y
-CONFIG_CRYPTO_MD4=y
 CONFIG_CRYPTO_TWOFISH=y
 CONFIG_CRYPTO_LZ4=y
 CONFIG_CRYPTO_ANSI_CPRNG=y
-CONFIG_CRYPTO_DEV_QCE=y
 CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y
 CONFIG_CRYPTO_DEV_QCRYPTO=y
 CONFIG_CRYPTO_DEV_QCEDEV=y
@@ -677,7 +691,6 @@ CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y
 CONFIG_DEBUG_STACK_USAGE=y
 CONFIG_DEBUG_MEMORY_INIT=y
 CONFIG_WQ_WATCHDOG=y
-CONFIG_PANIC_ON_OOPS=y
 CONFIG_PANIC_TIMEOUT=5
 CONFIG_PANIC_ON_SCHED_BUG=y
 CONFIG_PANIC_ON_RT_THROTTLING=y
@@ -708,4 +721,15 @@ CONFIG_BUG_ON_DATA_CORRUPTION=y
 CONFIG_PANIC_ON_DATA_CORRUPTION=y
 CONFIG_DEBUG_USER=y
 CONFIG_FORCE_PAGES=y
-CONFIG_PID_IN_CONTEXTIDR=y
+CONFIG_CORESIGHT=y
+CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
+CONFIG_CORESIGHT_SOURCE_ETM4X=y
+CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
+CONFIG_CORESIGHT_STM=y
+CONFIG_CORESIGHT_CTI=y
+CONFIG_CORESIGHT_TPDA=y
+CONFIG_CORESIGHT_TPDM=y
+CONFIG_CORESIGHT_HWEVENT=y
+CONFIG_CORESIGHT_DUMMY=y
+CONFIG_CORESIGHT_REMOTE_ETM=y
+CONFIG_CORESIGHT_TGU=y

arch/arm/configs/vendor/msm8937_defconfig

@@ -0,0 +1,745 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_AUDIT=y
+# CONFIG_AUDITSYSCALL is not set
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_SCHED_WALT=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_PSI=y
+CONFIG_RCU_EXPERT=y
+CONFIG_RCU_FAST_NO_HZ=y
+CONFIG_RCU_NOCB_CPU=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKHEADERS=y
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=17
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_BLK_CGROUP=y
+CONFIG_DEBUG_BLK_CGROUP=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_BPF=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_SCHED_CORE_CTL=y
+CONFIG_NAMESPACES=y
+# CONFIG_PID_NS is not set
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_SCHED_TUNE=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+# CONFIG_FHANDLE is not set
+CONFIG_KALLSYMS_ALL=y
+CONFIG_BPF_SYSCALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_ARCH_QCOM=y
+CONFIG_ARCH_QM215=y
+CONFIG_ARCH_MSM8917=y
+CONFIG_ARCH_MSM8937=y
+CONFIG_ARCH_SDM439=y
+CONFIG_ARCH_SDM429=y
+# CONFIG_VDSO is not set
+CONFIG_SMP=y
+CONFIG_SCHED_MC=y
+CONFIG_NR_CPUS=8
+CONFIG_ARM_PSCI=y
+CONFIG_HIGHMEM=y
+CONFIG_SECCOMP=y
+CONFIG_CMDLINE="cgroup_disable=pressure"
+CONFIG_CMDLINE_EXTEND=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TIMES=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_BOOST=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_MSM=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_PM_WAKELOCKS=y
+CONFIG_PM_WAKELOCKS_LIMIT=0
+# CONFIG_PM_WAKELOCKS_GC is not set
+CONFIG_PM_DEBUG=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_MSM_TZ_LOG=y
+CONFIG_ARM_CRYPTO=y
+CONFIG_CRYPTO_SHA1_ARM_NEON=y
+CONFIG_CRYPTO_SHA2_ARM_CE=y
+CONFIG_CRYPTO_AES_ARM_BS=y
+CONFIG_CRYPTO_AES_ARM_CE=y
+CONFIG_CRYPTO_GHASH_ARM_CE=y
+CONFIG_OPROFILE=m
+CONFIG_KPROBES=y
+CONFIG_ARCH_MMAP_RND_BITS=16
+CONFIG_PANIC_ON_REFCOUNT_ERROR=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SIG=y
+CONFIG_MODULE_SIG_FORCE=y
+CONFIG_MODULE_SIG_SHA512=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_BLK_DEV_ZONED=y
+CONFIG_BLK_INLINE_ENCRYPTION=y
+CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_CFQ_GROUP_IOSCHED=y
+CONFIG_IOSCHED_BFQ=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_CLEANCACHE=y
+CONFIG_CMA=y
+CONFIG_CMA_DEBUGFS=y
+CONFIG_ZSMALLOC=y
+CONFIG_HAVE_USERSPACE_LOW_MEMORY_KILLER=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_XFRM_INTERFACE=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_NET_IPGRE_DEMUX=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_UDP_DIAG=y
+CONFIG_INET_DIAG_DESTROY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_IPV6_VTI=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_LOG=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_TEE=y
+CONFIG_NETFILTER_XT_TARGET_TPROXY=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_SECMARK=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_BPF=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+# CONFIG_NETFILTER_XT_MATCH_L2TP is not set
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+CONFIG_NETFILTER_XT_MATCH_SOCKET=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_RPFILTER=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_SECURITY=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_RPFILTER=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_BRIDGE_NF_EBTABLES=y
+CONFIG_BRIDGE_EBT_BROUTE=y
+CONFIG_IP_SCTP=y
+CONFIG_L2TP=y
+CONFIG_L2TP_DEBUGFS=y
+CONFIG_L2TP_V3=y
+CONFIG_L2TP_IP=y
+CONFIG_L2TP_ETH=y
+CONFIG_BRIDGE=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_INGRESS=y
+CONFIG_NET_CLS_FW=y
+CONFIG_NET_CLS_U32=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_FLOW=y
+CONFIG_NET_CLS_BPF=y
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_CMP=y
+CONFIG_NET_EMATCH_NBYTE=y
+CONFIG_NET_EMATCH_U32=y
+CONFIG_NET_EMATCH_META=y
+CONFIG_NET_EMATCH_TEXT=y
+CONFIG_NET_CLS_ACT=y
+CONFIG_DNS_RESOLVER=y
+CONFIG_QRTR=y
+CONFIG_QRTR_SMD=y
+CONFIG_BPF_JIT=y
+CONFIG_BT=y
+# CONFIG_BT_BREDR is not set
+# CONFIG_BT_LE is not set
+CONFIG_MSM_BT_POWER=y
+CONFIG_BTFM_SLIM_WCN3990=y
+CONFIG_CFG80211=y
+CONFIG_CFG80211_INTERNAL_REGDB=y
+# CONFIG_CFG80211_CRDA_SUPPORT is not set
+CONFIG_RFKILL=y
+CONFIG_NFC_NQ=y
+CONFIG_FW_LOADER_USER_HELPER=y
+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
+# CONFIG_FW_CACHE is not set
+CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y
+CONFIG_DMA_CMA=y
+CONFIG_ZRAM=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=16
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_HDCP_QSEECOM=y
+CONFIG_QSEECOM=y
+CONFIG_UID_SYS_STATS=y
+CONFIG_FPR_FPC=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_UFSHCD=y
+CONFIG_SCSI_UFSHCD_PLATFORM=y
+CONFIG_SCSI_UFS_QCOM=y
+CONFIG_SCSI_UFSHCD_CMD_LOGGING=y
+CONFIG_SCSI_UFS_CRYPTO=y
+CONFIG_SCSI_UFS_CRYPTO_QTI=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=y
+CONFIG_DM_DEFAULT_KEY=y
+CONFIG_DM_SNAPSHOT=y
+CONFIG_DM_UEVENT=y
+CONFIG_DM_VERITY=y
+CONFIG_DM_VERITY_FEC=y
+CONFIG_DM_ANDROID_VERITY=y
+CONFIG_DM_BOW=y
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+CONFIG_TUN=y
+CONFIG_VETH=y
+# CONFIG_NET_VENDOR_AMAZON is not set
+CONFIG_MSM_RMNET_BAM=y
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+CONFIG_RMNET=y
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+CONFIG_PPP=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=y
+CONFIG_PPTP=y
+CONFIG_PPPOL2TP=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_RTL8152=y
+CONFIG_USB_USBNET=y
+# CONFIG_WLAN_VENDOR_ADMTEK is not set
+# CONFIG_WLAN_VENDOR_ATH is not set
+# CONFIG_WLAN_VENDOR_ATMEL is not set
+# CONFIG_WLAN_VENDOR_BROADCOM is not set
+# CONFIG_WLAN_VENDOR_CISCO is not set
+# CONFIG_WLAN_VENDOR_INTEL is not set
+# CONFIG_WLAN_VENDOR_INTERSIL is not set
+# CONFIG_WLAN_VENDOR_MARVELL is not set
+# CONFIG_WLAN_VENDOR_MEDIATEK is not set
+# CONFIG_WLAN_VENDOR_RALINK is not set
+# CONFIG_WLAN_VENDOR_REALTEK is not set
+# CONFIG_WLAN_VENDOR_RSI is not set
+# CONFIG_WLAN_VENDOR_ST is not set
+# CONFIG_WLAN_VENDOR_TI is not set
+# CONFIG_WLAN_VENDOR_ZYDAS is not set
+CONFIG_WCNSS_MEM_PRE_ALLOC=y
+CONFIG_CLD_LL_CORE=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_JOYSTICK_XPAD=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_HBTP_INPUT=y
+CONFIG_INPUT_QPNP_POWER_ON=y
+CONFIG_INPUT_UINPUT=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVMEM is not set
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
+CONFIG_SERIAL_MSM_HS=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MSM_LEGACY=y
+CONFIG_MSM_SMD_PKT=y
+CONFIG_DIAG_CHAR=y
+CONFIG_MSM_ADSPRPC=y
+CONFIG_MSM_RDBG=m
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MSM_V2=y
+CONFIG_SPI=y
+CONFIG_SPI_QUP=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SPMI=y
+CONFIG_PINCTRL_MSM8937=y
+CONFIG_PINCTRL_MSM8917=y
+CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_QCOM=y
+CONFIG_QPNP_SMB5=y
+CONFIG_QPNP_VM_BMS=y
+CONFIG_QPNP_LINEAR_CHARGER=y
+CONFIG_SMB1351_USB_CHARGER=y
+CONFIG_SMB1360_CHARGER_FG=y
+CONFIG_SMB1355_SLAVE_CHARGER=y
+CONFIG_QPNP_QG=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_GOV_LOW_LIMITS=y
+CONFIG_CPU_THERMAL=y
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_QCOM_SPMI_TEMP_ALARM=y
+CONFIG_THERMAL_QPNP_ADC_TM=y
+CONFIG_THERMAL_TSENS=y
+CONFIG_QTI_ADC_TM=y
+CONFIG_QTI_VIRTUAL_SENSOR=y
+CONFIG_QTI_BCL_PMIC5=y
+CONFIG_QTI_BCL_SOC_DRIVER=y
+CONFIG_QTI_QMI_COOLING_DEVICE=y
+CONFIG_REGULATOR_COOLING_DEVICE=y
+CONFIG_MFD_I2C_PMIC=y
+CONFIG_MFD_SPMI_PMIC=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_PROXY_CONSUMER=y
+CONFIG_REGULATOR_QPNP_LABIBB=y
+CONFIG_REGULATOR_QPNP_LCDB=y
+CONFIG_REGULATOR_MEM_ACC=y
+CONFIG_REGULATOR_CPR=y
+CONFIG_REGULATOR_RPM_SMD=y
+CONFIG_REGULATOR_SPM=y
+CONFIG_REGULATOR_STUB=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_MSM_VIDC_3X_GOVERNORS=y
+CONFIG_MSM_VIDC_3X_V4L2=y
+CONFIG_MSM_CAMERA=y
+CONFIG_MSM_CAMERA_DEBUG=y
+CONFIG_MSMB_CAMERA=y
+CONFIG_MSMB_CAMERA_DEBUG=y
+CONFIG_MSM_CAMERA_SENSOR=y
+CONFIG_MSM_CPP=y
+CONFIG_MSM_CCI=y
+CONFIG_MSM_CSI20_HEADER=y
+CONFIG_MSM_CSI22_HEADER=y
+CONFIG_MSM_CSI30_HEADER=y
+CONFIG_MSM_CSI31_HEADER=y
+CONFIG_MSM_CSIPHY=y
+CONFIG_MSM_CSID=y
+CONFIG_MSM_EEPROM=y
+CONFIG_MSM_ISPIF_V2=y
+CONFIG_IMX134=y
+CONFIG_IMX132=y
+CONFIG_OV9724=y
+CONFIG_OV5648=y
+CONFIG_GC0339=y
+CONFIG_OV8825=y
+CONFIG_OV8865=y
+CONFIG_s5k4e1=y
+CONFIG_OV12830=y
+CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y
+CONFIG_MSMB_JPEG=y
+CONFIG_MSM_FD=y
+CONFIG_RADIO_IRIS=y
+CONFIG_RADIO_IRIS_TRANSPORT=y
+CONFIG_FB=y
+CONFIG_FB_VIRTUAL=y
+CONFIG_FB_MSM=y
+CONFIG_FB_MSM_MDSS=y
+CONFIG_FB_MSM_MDSS_WRITEBACK=y
+CONFIG_FB_MSM_MDSS_DSI_CTRL_STATUS=y
+CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_UHID=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_ELECOM=y
+CONFIG_HID_MAGICMOUSE=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MULTITOUCH=y
+CONFIG_HID_SONY=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_MON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_EHCI_MSM=y
+CONFIG_USB_ACM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_ISD200=y
+CONFIG_USB_STORAGE_USBAT=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_USB_STORAGE_ALAUDA=y
+CONFIG_USB_STORAGE_ONETOUCH=y
+CONFIG_USB_STORAGE_KARMA=y
+CONFIG_USB_STORAGE_CYPRESS_ATACB=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_EHSET_TEST_FIXTURE=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_USB_CI13XXX_MSM=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_UEVENT=y
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_RMNET_BAM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_ACC=y
+CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y
+CONFIG_USB_CONFIGFS_F_MIDI=y
+CONFIG_USB_CONFIGFS_F_HID=y
+CONFIG_USB_CONFIGFS_F_DIAG=y
+CONFIG_USB_CONFIGFS_F_CDEV=y
+CONFIG_USB_CONFIGFS_F_CCID=y
+CONFIG_USB_CONFIGFS_F_QDSS=y
+CONFIG_USB_CONFIGFS_F_MTP=y
+CONFIG_USB_CONFIGFS_F_PTP=y
+CONFIG_TYPEC=y
+CONFIG_MMC=y
+# CONFIG_PWRSEQ_EMMC is not set
+# CONFIG_PWRSEQ_SIMPLE is not set
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_BLOCK_DEFERRED_RESUME=y
+CONFIG_MMC_IPC_LOGGING=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_MSM=y
+CONFIG_MMC_CQHCI_CRYPTO=y
+CONFIG_MMC_CQHCI_CRYPTO_QTI=y
+CONFIG_LEDS_QTI_TRI_LED=y
+CONFIG_LEDS_QPNP_FLASH_V2=y
+CONFIG_LEDS_QPNP_VIBRATOR_LDO=y
+CONFIG_LEDS_QPNP_VIBRATOR=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_EDAC=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PM8XXX=y
+CONFIG_DMADEVICES=y
+CONFIG_QCOM_SPS_DMA=y
+CONFIG_UIO=y
+CONFIG_UIO_MSM_SHAREDMEM=y
+CONFIG_STAGING=y
+CONFIG_ASHMEM=y
+CONFIG_ION=y
+CONFIG_ION_POOL_AUTO_REFILL=y
+CONFIG_MSM_EXT_DISPLAY=y
+CONFIG_QPNP_REVID=y
+CONFIG_SPS=y
+CONFIG_SPS_SUPPORT_NDP_BAM=y
+CONFIG_IPA=y
+CONFIG_RMNET_IPA=y
+CONFIG_RNDIS_IPA=y
+CONFIG_USB_BAM=y
+CONFIG_MDSS_PLL=y
+CONFIG_QCOM_CLK_SMD_RPM=y
+CONFIG_SDM_GCC_429W=y
+CONFIG_SDM_DEBUGCC_429W=y
+CONFIG_CLOCK_CPU_SDM=y
+CONFIG_SDM_DEBUGCC_439=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_QCOM=y
+CONFIG_MAILBOX=y
+CONFIG_ARM_SMMU=y
+CONFIG_QCOM_LAZY_MAPPING=y
+CONFIG_IOMMU_DEBUG=y
+CONFIG_IOMMU_TESTS=y
+CONFIG_RPMSG_CHAR=y
+CONFIG_RPMSG_QCOM_GLINK_RPM=y
+CONFIG_RPMSG_QCOM_GLINK_SMEM=y
+CONFIG_RPMSG_QCOM_SMD=y
+CONFIG_MSM_RPM_SMD=y
+CONFIG_QCOM_CPUSS_DUMP=y
+CONFIG_QCOM_RUN_QUEUE_STATS=y
+CONFIG_QCOM_QMI_HELPERS=y
+CONFIG_QCOM_SMEM=y
+CONFIG_QCOM_SMD_RPM=y
+CONFIG_MSM_SPM=y
+CONFIG_MSM_L2_SPM=y
+CONFIG_QCOM_EARLY_RANDOM=y
+CONFIG_QCOM_MEMORY_DUMP_V2=y
+CONFIG_MSM_DEBUG_LAR_UNLOCK=y
+CONFIG_QCOM_SMP2P=y
+CONFIG_QCOM_SMSM=y
+CONFIG_MSM_PIL_MSS_QDSP6V5=y
+CONFIG_QCOM_SECURE_BUFFER=y
+CONFIG_MSM_TZ_SMMU=y
+CONFIG_MSM_SUBSYSTEM_RESTART=y
+CONFIG_MSM_PIL=y
+CONFIG_MSM_SYSMON_QMI_COMM=y
+CONFIG_MSM_PIL_SSR_GENERIC=y
+CONFIG_MSM_BOOT_STATS=y
+CONFIG_MSM_CORE_HANG_DETECT=y
+CONFIG_QCOM_WATCHDOG_V2=y
+CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
+CONFIG_QCOM_BUS_SCALING=y
+CONFIG_QCOM_GLINK=y
+CONFIG_MSM_EVENT_TIMER=y
+CONFIG_MSM_PM=y
+CONFIG_QCOM_DCC=y
+CONFIG_QTI_RPM_STATS_LOG=y
+CONFIG_QTEE_SHM_BRIDGE=y
+CONFIG_MEM_SHARE_QMI_SERVICE=y
+CONFIG_MSM_PERFORMANCE=y
+CONFIG_QTI_CRYPTO_COMMON=y
+CONFIG_QTI_CRYPTO_TZ=y
+CONFIG_MSM_BAM_DMUX=y
+CONFIG_WCNSS_CORE=y
+CONFIG_WCNSS_CORE_PRONTO=y
+CONFIG_WCNSS_REGISTER_DUMP_ON_BITE=y
+CONFIG_DEVFREQ_GOV_PASSIVE=y
+CONFIG_QCOM_BIMC_BWMON=y
+CONFIG_ARM_MEMLAT_MON=y
+CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y
+CONFIG_DEVFREQ_GOV_MEMLAT=y
+CONFIG_DEVFREQ_SIMPLE_DEV=y
+CONFIG_QCOM_DEVFREQ_DEVBW=y
+CONFIG_IIO=y
+CONFIG_QCOM_SPMI_ADC5=y
+CONFIG_QCOM_SPMI_VADC=y
+CONFIG_PWM=y
+CONFIG_PWM_QTI_LPG=y
+CONFIG_QCOM_SHOW_RESUME_IRQ=y
+CONFIG_QCOM_MPM=y
+CONFIG_RAS=y
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_BINDERFS=y
+CONFIG_QCOM_QFPROM=y
+CONFIG_SLIMBUS_MSM_NGD=y
+CONFIG_SENSORS_SSC=y
+CONFIG_QCOM_KGSL=y
+CONFIG_LEGACY_ENERGY_MODEL_DT=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXT4_ENCRYPTION=y
+CONFIG_F2FS_FS=y
+CONFIG_F2FS_FS_SECURITY=y
+CONFIG_F2FS_CHECK_FS=y
+CONFIG_F2FS_FS_ENCRYPTION=y
+CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
+CONFIG_FS_VERITY=y
+CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+CONFIG_QFMT_V2=y
+CONFIG_FUSE_FS=y
+CONFIG_OVERLAY_FS=y
+CONFIG_INCREMENTAL_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_SDCARD_FS=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_SECURITY=y
+CONFIG_LSM_MMAP_MIN_ADDR=4096
+CONFIG_HARDENED_USERCOPY=y
+CONFIG_HARDENED_USERCOPY_PAGESPAN=y
+CONFIG_FORTIFY_SOURCE=y
+CONFIG_STATIC_USERMODEHELPER=y
+CONFIG_STATIC_USERMODEHELPER_PATH=""
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SMACK=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_XCBC=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_LZ4=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_DEV_QCE=y
+CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y
+CONFIG_CRYPTO_DEV_QCRYPTO=y
+CONFIG_CRYPTO_DEV_QCEDEV=y
+CONFIG_CRYPTO_DEV_QCOM_ICE=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_CONSOLE_UNHASHED_POINTERS=y
+CONFIG_DEBUG_MODULE_LOAD_INFO=y
+CONFIG_DEBUG_INFO=y
+CONFIG_FRAME_WARN=2048
+CONFIG_PAGE_OWNER=y
+CONFIG_PAGE_OWNER_ENABLE_DEFAULT=y
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_PAGEALLOC=y
+CONFIG_SLUB_DEBUG_PANIC_ON=y
+CONFIG_DEBUG_PANIC_ON_OOM=y
+CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y
+CONFIG_PAGE_POISONING=y
+CONFIG_PAGE_POISONING_ENABLE_DEFAULT=y
+CONFIG_DEBUG_OBJECTS=y
+CONFIG_DEBUG_OBJECTS_FREE=y
+CONFIG_DEBUG_OBJECTS_TIMERS=y
+CONFIG_DEBUG_OBJECTS_WORK=y
+CONFIG_DEBUG_OBJECTS_RCU_HEAD=y
+CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y
+CONFIG_DEBUG_KMEMLEAK=y
+CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=4000
+CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y
+CONFIG_DEBUG_STACK_USAGE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_WQ_WATCHDOG=y
+CONFIG_PANIC_ON_OOPS=y
+CONFIG_PANIC_TIMEOUT=5
+CONFIG_PANIC_ON_SCHED_BUG=y
+CONFIG_PANIC_ON_RT_THROTTLING=y
+CONFIG_SCHEDSTATS=y
+CONFIG_SCHED_STACK_END_CHECK=y
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+CONFIG_LOCK_TORTURE_TEST=m
+CONFIG_DEBUG_SG=y
+CONFIG_DEBUG_NOTIFIERS=y
+CONFIG_DEBUG_CREDENTIALS=y
+CONFIG_FAULT_INJECTION=y
+CONFIG_FAIL_PAGE_ALLOC=y
+CONFIG_FAULT_INJECTION_DEBUG_FS=y
+CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y
+CONFIG_IPC_LOGGING=y
+CONFIG_QCOM_RTB=y
+CONFIG_QCOM_RTB_SEPARATE_CPUS=y
+CONFIG_PREEMPTIRQ_EVENTS=y
+CONFIG_IRQSOFF_TRACER=y
+CONFIG_PREEMPT_TRACER=y
+CONFIG_BLK_DEV_IO_TRACE=y
+CONFIG_LKDTM=y
+CONFIG_ATOMIC64_SELFTEST=m
+CONFIG_MEMTEST=y
+CONFIG_BUG_ON_DATA_CORRUPTION=y
+CONFIG_PANIC_ON_DATA_CORRUPTION=y
+CONFIG_DEBUG_USER=y
+CONFIG_FORCE_PAGES=y
+CONFIG_CORESIGHT=y
+CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
+CONFIG_CORESIGHT_SOURCE_ETM4X=y
+CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
+CONFIG_CORESIGHT_STM=y
+CONFIG_CORESIGHT_CTI=y
+CONFIG_CORESIGHT_TPDA=y
+CONFIG_CORESIGHT_TPDM=y
+CONFIG_CORESIGHT_HWEVENT=y
+CONFIG_CORESIGHT_DUMMY=y
+CONFIG_CORESIGHT_REMOTE_ETM=y
+CONFIG_CORESIGHT_TGU=y

arch/arm/include/asm/etmv4x.h

@@ -0,0 +1,388 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2016, 2018, 2021, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ETMV4X_H
+#define __ASM_ETMV4X_H
+
+#include <linux/types.h>
+
+
+/* 32 bit register read for AArch32 */
+#define trc_readl(reg)			RSYSL_##reg()
+#define trc_readq(reg)			RSYSL_##reg()
+
+/* 32 bit register write for AArch32 */
+#define trc_write(val, reg)		WSYS_##reg(val)
+
+#define MRC(op0, op1, crn, crm, op2)					    \
+({									    \
+uint32_t val;								    \
+asm volatile("mrc p"#op0", "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
+val;									    \
+})
+
+#define MCR(val, op0, op1, crn, crm, op2)				    \
+({									    \
+asm volatile("mcr p"#op0", "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
+})
+
+/* Clock and Power Management Register */
+#define RSYSL_CPMR_EL1()		MRC(15, 7, c15, c0, 5)
+#define WSYS_CPMR_EL1(val)		MCR(val, 15, 7, c15, c0, 5)
+
+/*
+ * ETMv4 Registers
+ *
+ * Read only
+ * ETMAUTHSTATUS, ETMDEVARCH, ETMDEVID, ETMIDRn[0-13], ETMOSLSR, ETMSTATR
+ *
+ * Write only
+ * ETMOSLAR
+ */
+/* 32 bit registers */
+#define RSYSL_ETMAUTHSTATUS()		MRC(14, 1, c7, c14, 6)
+#define RSYSL_ETMAUXCTLR()		MRC(14, 1, c0, c6, 0)
+#define RSYSL_ETMCCCTLR()		MRC(14, 1, c0, c14, 0)
+#define RSYSL_ETMCIDCCTLR0()		MRC(14, 1, c3, c0, 2)
+#define RSYSL_ETMCNTCTLR0()		MRC(14, 1, c0, c4, 5)
+#define RSYSL_ETMCNTCTLR1()		MRC(14, 1, c0, c5, 5)
+#define RSYSL_ETMCNTCTLR2()		MRC(14, 1, c0, c6, 5)
+#define RSYSL_ETMCNTCTLR3()		MRC(14, 1, c0, c7, 5)
+#define RSYSL_ETMCNTRLDVR0()		MRC(14, 1, c0, c0, 5)
+#define RSYSL_ETMCNTRLDVR1()		MRC(14, 1, c0, c1, 5)
+#define RSYSL_ETMCNTRLDVR2()		MRC(14, 1, c0, c2, 5)
+#define RSYSL_ETMCNTRLDVR3()		MRC(14, 1, c0, c3, 5)
+#define RSYSL_ETMCNTVR0()		MRC(14, 1, c0, c8, 5)
+#define RSYSL_ETMCNTVR1()		MRC(14, 1, c0, c9, 5)
+#define RSYSL_ETMCNTVR2()		MRC(14, 1, c0, c10, 5)
+#define RSYSL_ETMCNTVR3()		MRC(14, 1, c0, c11, 5)
+#define RSYSL_ETMCONFIGR()		MRC(14, 1, c0, c4, 0)
+#define RSYSL_ETMDEVARCH()		MRC(14, 1, c7, c15, 6)
+#define RSYSL_ETMDEVID()		MRC(14, 1, c7, c2, 7)
+#define RSYSL_ETMEVENTCTL0R()		MRC(14, 1, c0, c8, 0)
+#define RSYSL_ETMEVENTCTL1R()		MRC(14, 1, c0, c9, 0)
+#define RSYSL_ETMEXTINSELR()		MRC(14, 1, c0, c8, 4)
+#define RSYSL_ETMIDR0()			MRC(14, 1, c0, c8, 7)
+#define RSYSL_ETMIDR1()			MRC(14, 1, c0, c9, 7)
+#define RSYSL_ETMIDR10()		MRC(14, 1, c0, c2, 6)
+#define RSYSL_ETMIDR11()		MRC(14, 1, c0, c3, 6)
+#define RSYSL_ETMIDR12()		MRC(14, 1, c0, c4, 6)
+#define RSYSL_ETMIDR13()		MRC(14, 1, c0, c5, 6)
+#define RSYSL_ETMIDR2()			MRC(14, 1, c0, c10, 7)
+#define RSYSL_ETMIDR3()			MRC(14, 1, c0, c11, 7)
+#define RSYSL_ETMIDR4()			MRC(14, 1, c0, c12, 7)
+#define RSYSL_ETMIDR5()			MRC(14, 1, c0, c13, 7)
+#define RSYSL_ETMIDR6()			MRC(14, 1, c0, c14, 7)
+#define RSYSL_ETMIDR7()			MRC(14, 1, c0, c15, 7)
+#define RSYSL_ETMIDR8()			MRC(14, 1, c0, c0, 6)
+#define RSYSL_ETMIDR9()			MRC(14, 1, c0, c1, 6)
+#define RSYSL_ETMIMSPEC0()		MRC(14, 1, c0, c0, 7)
+#define RSYSL_ETMOSLSR()		MRC(14, 1, c1, c1, 4)
+#define RSYSL_ETMPRGCTLR()		MRC(14, 1, c0, c1, 0)
+#define RSYSL_ETMRSCTLR10()		MRC(14, 1, c1, c10, 0)
+#define RSYSL_ETMRSCTLR11()		MRC(14, 1, c1, c11, 0)
+#define RSYSL_ETMRSCTLR12()		MRC(14, 1, c1, c12, 0)
+#define RSYSL_ETMRSCTLR13()		MRC(14, 1, c1, c13, 0)
+#define RSYSL_ETMRSCTLR14()		MRC(14, 1, c1, c14, 0)
+#define RSYSL_ETMRSCTLR15()		MRC(14, 1, c1, c15, 0)
+#define RSYSL_ETMRSCTLR2()		MRC(14, 1, c1, c2, 0)
+#define RSYSL_ETMRSCTLR3()		MRC(14, 1, c1, c3, 0)
+#define RSYSL_ETMRSCTLR4()		MRC(14, 1, c1, c4, 0)
+#define RSYSL_ETMRSCTLR5()		MRC(14, 1, c1, c5, 0)
+#define RSYSL_ETMRSCTLR6()		MRC(14, 1, c1, c6, 0)
+#define RSYSL_ETMRSCTLR7()		MRC(14, 1, c1, c7, 0)
+#define RSYSL_ETMRSCTLR8()		MRC(14, 1, c1, c8, 0)
+#define RSYSL_ETMRSCTLR9()		MRC(14, 1, c1, c9, 0)
+#define RSYSL_ETMRSCTLR16()		MRC(14, 1, c1, c0, 1)
+#define RSYSL_ETMRSCTLR17()		MRC(14, 1, c1, c1, 1)
+#define RSYSL_ETMRSCTLR18()		MRC(14, 1, c1, c2, 1)
+#define RSYSL_ETMRSCTLR19()		MRC(14, 1, c1, c3, 1)
+#define RSYSL_ETMRSCTLR20()		MRC(14, 1, c1, c4, 1)
+#define RSYSL_ETMRSCTLR21()		MRC(14, 1, c1, c5, 1)
+#define RSYSL_ETMRSCTLR22()		MRC(14, 1, c1, c6, 1)
+#define RSYSL_ETMRSCTLR23()		MRC(14, 1, c1, c7, 1)
+#define RSYSL_ETMRSCTLR24()		MRC(14, 1, c1, c8, 1)
+#define RSYSL_ETMRSCTLR25()		MRC(14, 1, c1, c9, 1)
+#define RSYSL_ETMRSCTLR26()		MRC(14, 1, c1, c10, 1)
+#define RSYSL_ETMRSCTLR27()		MRC(14, 1, c1, c11, 1)
+#define RSYSL_ETMRSCTLR28()		MRC(14, 1, c1, c12, 1)
+#define RSYSL_ETMRSCTLR29()		MRC(14, 1, c1, c13, 1)
+#define RSYSL_ETMRSCTLR30()		MRC(14, 1, c1, c14, 1)
+#define RSYSL_ETMRSCTLR31()		MRC(14, 1, c1, c15, 1)
+#define RSYSL_ETMSEQEVR0()		MRC(14, 1, c0, c0, 4)
+#define RSYSL_ETMSEQEVR1()		MRC(14, 1, c0, c1, 4)
+#define RSYSL_ETMSEQEVR2()		MRC(14, 1, c0, c2, 4)
+#define RSYSL_ETMSEQRSTEVR()		MRC(14, 1, c0, c6, 4)
+#define RSYSL_ETMSEQSTR()		MRC(14, 1, c0, c7, 4)
+#define RSYSL_ETMSTALLCTLR()		MRC(14, 1, c0, c11, 0)
+#define RSYSL_ETMSTATR()		MRC(14, 1, c0, c3, 0)
+#define RSYSL_ETMSYNCPR()		MRC(14, 1, c0, c13, 0)
+#define RSYSL_ETMTRACEIDR()		MRC(14, 1, c0, c0, 1)
+#define RSYSL_ETMTSCTLR()		MRC(14, 1, c0, c12, 0)
+#define RSYSL_ETMVICTLR()		MRC(14, 1, c0, c0, 2)
+#define RSYSL_ETMVIIECTLR()		MRC(14, 1, c0, c1, 2)
+#define RSYSL_ETMVISSCTLR()		MRC(14, 1, c0, c2, 2)
+#define RSYSL_ETMSSCCR0()		MRC(14, 1, c1, c0, 2)
+#define RSYSL_ETMSSCCR1()		MRC(14, 1, c1, c1, 2)
+#define RSYSL_ETMSSCCR2()		MRC(14, 1, c1, c2, 2)
+#define RSYSL_ETMSSCCR3()		MRC(14, 1, c1, c3, 2)
+#define RSYSL_ETMSSCCR4()		MRC(14, 1, c1, c4, 2)
+#define RSYSL_ETMSSCCR5()		MRC(14, 1, c1, c5, 2)
+#define RSYSL_ETMSSCCR6()		MRC(14, 1, c1, c6, 2)
+#define RSYSL_ETMSSCCR7()		MRC(14, 1, c1, c7, 2)
+#define RSYSL_ETMSSCSR0()		MRC(14, 1, c1, c8, 2)
+#define RSYSL_ETMSSCSR1()		MRC(14, 1, c1, c9, 2)
+#define RSYSL_ETMSSCSR2()		MRC(14, 1, c1, c10, 2)
+#define RSYSL_ETMSSCSR3()		MRC(14, 1, c1, c11, 2)
+#define RSYSL_ETMSSCSR4()		MRC(14, 1, c1, c12, 2)
+#define RSYSL_ETMSSCSR5()		MRC(14, 1, c1, c13, 2)
+#define RSYSL_ETMSSCSR6()		MRC(14, 1, c1, c14, 2)
+#define RSYSL_ETMSSCSR7()		MRC(14, 1, c1, c15, 2)
+#define RSYSL_ETMSSPCICR0()		MRC(14, 1, c1, c0, 3)
+#define RSYSL_ETMSSPCICR1()		MRC(14, 1, c1, c1, 3)
+#define RSYSL_ETMSSPCICR2()		MRC(14, 1, c1, c2, 3)
+#define RSYSL_ETMSSPCICR3()		MRC(14, 1, c1, c3, 3)
+#define RSYSL_ETMSSPCICR4()		MRC(14, 1, c1, c4, 3)
+#define RSYSL_ETMSSPCICR5()		MRC(14, 1, c1, c5, 3)
+#define RSYSL_ETMSSPCICR6()		MRC(14, 1, c1, c6, 3)
+#define RSYSL_ETMSSPCICR7()		MRC(14, 1, c1, c7, 3)
+
+/*
+ * 64 bit registers, ignore the upper 32bit
+ * A read from a 32-bit register location using a 64-bit access result
+ * in the upper 32bits being return as RES0.
+ */
+#define RSYSL_ETMACATR0()		MRC(14, 1, c2, c0, 2)
+#define RSYSL_ETMACATR1()		MRC(14, 1, c2, c2, 2)
+#define RSYSL_ETMACATR2()		MRC(14, 1, c2, c4, 2)
+#define RSYSL_ETMACATR3()		MRC(14, 1, c2, c6, 2)
+#define RSYSL_ETMACATR4()		MRC(14, 1, c2, c8, 2)
+#define RSYSL_ETMACATR5()		MRC(14, 1, c2, c10, 2)
+#define RSYSL_ETMACATR6()		MRC(14, 1, c2, c12, 2)
+#define RSYSL_ETMACATR7()		MRC(14, 1, c2, c14, 2)
+#define RSYSL_ETMACATR8()		MRC(14, 1, c2, c0, 3)
+#define RSYSL_ETMACATR9()		MRC(14, 1, c2, c2, 3)
+#define RSYSL_ETMACATR10()		MRC(14, 1, c2, c4, 3)
+#define RSYSL_ETMACATR11()		MRC(14, 1, c2, c6, 3)
+#define RSYSL_ETMACATR12()		MRC(14, 1, c2, c8, 3)
+#define RSYSL_ETMACATR13()		MRC(14, 1, c2, c10, 3)
+#define RSYSL_ETMACATR14()		MRC(14, 1, c2, c12, 3)
+#define RSYSL_ETMACATR15()		MRC(14, 1, c2, c14, 3)
+#define RSYSL_ETMCIDCVR0()		MRC(14, 1, c3, c0, 0)
+#define RSYSL_ETMCIDCVR1()		MRC(14, 1, c3, c2, 0)
+#define RSYSL_ETMCIDCVR2()		MRC(14, 1, c3, c4, 0)
+#define RSYSL_ETMCIDCVR3()		MRC(14, 1, c3, c6, 0)
+#define RSYSL_ETMCIDCVR4()		MRC(14, 1, c3, c8, 0)
+#define RSYSL_ETMCIDCVR5()		MRC(14, 1, c3, c10, 0)
+#define RSYSL_ETMCIDCVR6()		MRC(14, 1, c3, c12, 0)
+#define RSYSL_ETMCIDCVR7()		MRC(14, 1, c3, c14, 0)
+#define RSYSL_ETMACVR0()		MRC(14, 1, c2, c0, 0)
+#define RSYSL_ETMACVR1()		MRC(14, 1, c2, c2, 0)
+#define RSYSL_ETMACVR2()		MRC(14, 1, c2, c4, 0)
+#define RSYSL_ETMACVR3()		MRC(14, 1, c2, c6, 0)
+#define RSYSL_ETMACVR4()		MRC(14, 1, c2, c8, 0)
+#define RSYSL_ETMACVR5()		MRC(14, 1, c2, c10, 0)
+#define RSYSL_ETMACVR6()		MRC(14, 1, c2, c12, 0)
+#define RSYSL_ETMACVR7()		MRC(14, 1, c2, c14, 0)
+#define RSYSL_ETMACVR8()		MRC(14, 1, c2, c0, 1)
+#define RSYSL_ETMACVR9()		MRC(14, 1, c2, c2, 1)
+#define RSYSL_ETMACVR10()		MRC(14, 1, c2, c4, 1)
+#define RSYSL_ETMACVR11()		MRC(14, 1, c2, c6, 1)
+#define RSYSL_ETMACVR12()		MRC(14, 1, c2, c8, 1)
+#define RSYSL_ETMACVR13()		MRC(14, 1, c2, c10, 1)
+#define RSYSL_ETMACVR14()		MRC(14, 1, c2, c12, 1)
+#define RSYSL_ETMACVR15()		MRC(14, 1, c2, c14, 1)
+#define RSYSL_ETMVMIDCVR0()		MRC(14, 1, c3, c0, 1)
+#define RSYSL_ETMVMIDCVR1()		MRC(14, 1, c3, c2, 1)
+#define RSYSL_ETMVMIDCVR2()		MRC(14, 1, c3, c4, 1)
+#define RSYSL_ETMVMIDCVR3()		MRC(14, 1, c3, c6, 1)
+#define RSYSL_ETMVMIDCVR4()		MRC(14, 1, c3, c8, 1)
+#define RSYSL_ETMVMIDCVR5()		MRC(14, 1, c3, c10, 1)
+#define RSYSL_ETMVMIDCVR6()		MRC(14, 1, c3, c12, 1)
+#define RSYSL_ETMVMIDCVR7()		MRC(14, 1, c3, c14, 1)
+#define RSYSL_ETMDVCVR0()		MRC(14, 1, c2, c0, 4)
+#define RSYSL_ETMDVCVR1()		MRC(14, 1, c2, c4, 4)
+#define RSYSL_ETMDVCVR2()		MRC(14, 1, c2, c8, 4)
+#define RSYSL_ETMDVCVR3()		MRC(14, 1, c2, c12, 4)
+#define RSYSL_ETMDVCVR4()		MRC(14, 1, c2, c0, 5)
+#define RSYSL_ETMDVCVR5()		MRC(14, 1, c2, c4, 5)
+#define RSYSL_ETMDVCVR6()		MRC(14, 1, c2, c8, 5)
+#define RSYSL_ETMDVCVR7()		MRC(14, 1, c2, c12, 5)
+#define RSYSL_ETMDVCMR0()		MRC(14, 1, c2, c0, 6)
+#define RSYSL_ETMDVCMR1()		MRC(14, 1, c2, c4, 6)
+#define RSYSL_ETMDVCMR2()		MRC(14, 1, c2, c8, 6)
+#define RSYSL_ETMDVCMR3()		MRC(14, 1, c2, c12, 6)
+#define RSYSL_ETMDVCMR4()		MRC(14, 1, c2, c0, 7)
+#define RSYSL_ETMDVCMR5()		MRC(14, 1, c2, c4, 7)
+#define RSYSL_ETMDVCMR6()		MRC(14, 1, c2, c8, 7)
+#define RSYSL_ETMDVCMR7()		MRC(14, 1, c2, c12, 7)
+
+/*
+ * 32 and 64 bit registers
+ * A write to a 32-bit register location using a 64-bit access result
+ * in the upper 32bit of access
+ */
+#define WSYS_ETMAUXCTLR(val)		MCR(val, 14, 1, c0, c6, 0)
+#define WSYS_ETMACATR0(val)		MCR(val, 14, 1, c2, c0, 2)
+#define WSYS_ETMACATR1(val)		MCR(val, 14, 1, c2, c2, 2)
+#define WSYS_ETMACATR2(val)		MCR(val, 14, 1, c2, c4, 2)
+#define WSYS_ETMACATR3(val)		MCR(val, 14, 1, c2, c6, 2)
+#define WSYS_ETMACATR4(val)		MCR(val, 14, 1, c2, c8, 2)
+#define WSYS_ETMACATR5(val)		MCR(val, 14, 1, c2, c10, 2)
+#define WSYS_ETMACATR6(val)		MCR(val, 14, 1, c2, c12, 2)
+#define WSYS_ETMACATR7(val)		MCR(val, 14, 1, c2, c14, 2)
+#define WSYS_ETMACATR8(val)		MCR(val, 14, 1, c2, c0, 3)
+#define WSYS_ETMACATR9(val)		MCR(val, 14, 1, c2, c2, 3)
+#define WSYS_ETMACATR10(val)		MCR(val, 14, 1, c2, c4, 3)
+#define WSYS_ETMACATR11(val)		MCR(val, 14, 1, c2, c6, 3)
+#define WSYS_ETMACATR12(val)		MCR(val, 14, 1, c2, c8, 3)
+#define WSYS_ETMACATR13(val)		MCR(val, 14, 1, c2, c10, 3)
+#define WSYS_ETMACATR14(val)		MCR(val, 14, 1, c2, c12, 3)
+#define WSYS_ETMACATR15(val)		MCR(val, 14, 1, c2, c14, 3)
+#define WSYS_ETMACVR0(val)		MCR(val, 14, 1, c2, c0, 0)
+#define WSYS_ETMACVR1(val)		MCR(val, 14, 1, c2, c2, 0)
+#define WSYS_ETMACVR2(val)		MCR(val, 14, 1, c2, c4, 0)
+#define WSYS_ETMACVR3(val)		MCR(val, 14, 1, c2, c6, 0)
+#define WSYS_ETMACVR4(val)		MCR(val, 14, 1, c2, c8, 0)
+#define WSYS_ETMACVR5(val)		MCR(val, 14, 1, c2, c10, 0)
+#define WSYS_ETMACVR6(val)		MCR(val, 14, 1, c2, c12, 0)
+#define WSYS_ETMACVR7(val)		MCR(val, 14, 1, c2, c14, 0)
+#define WSYS_ETMACVR8(val)		MCR(val, 14, 1, c2, c0, 1)
+#define WSYS_ETMACVR9(val)		MCR(val, 14, 1, c2, c2, 1)
+#define WSYS_ETMACVR10(val)		MCR(val, 14, 1, c2, c4, 1)
+#define WSYS_ETMACVR11(val)		MCR(val, 14, 1, c2, c6, 1)
+#define WSYS_ETMACVR12(val)		MCR(val, 14, 1, c2, c8, 1)
+#define WSYS_ETMACVR13(val)		MCR(val, 14, 1, c2, c10, 1)
+#define WSYS_ETMACVR14(val)		MCR(val, 14, 1, c2, c12, 1)
+#define WSYS_ETMACVR15(val)		MCR(val, 14, 1, c2, c14, 1)
+#define WSYS_ETMCCCTLR(val)		MCR(val, 14, 1, c0, c14, 0)
+#define WSYS_ETMCIDCCTLR0(val)		MCR(val, 14, 1, c3, c0, 2)
+#define WSYS_ETMCIDCVR0(val)		MCR(val, 14, 1, c3, c0, 0)
+#define WSYS_ETMCIDCVR1(val)		MCR(val, 14, 1, c3, c2, 0)
+#define WSYS_ETMCIDCVR2(val)		MCR(val, 14, 1, c3, c4, 0)
+#define WSYS_ETMCIDCVR3(val)		MCR(val, 14, 1, c3, c6, 0)
+#define WSYS_ETMCIDCVR4(val)		MCR(val, 14, 1, c3, c8, 0)
+#define WSYS_ETMCIDCVR5(val)		MCR(val, 14, 1, c3, c10, 0)
+#define WSYS_ETMCIDCVR6(val)		MCR(val, 14, 1, c3, c12, 0)
+#define WSYS_ETMCIDCVR7(val)		MCR(val, 14, 1, c3, c14, 0)
+#define WSYS_ETMCNTCTLR0(val)		MCR(val, 14, 1, c0, c4, 5)
+#define WSYS_ETMCNTCTLR1(val)		MCR(val, 14, 1, c0, c5, 5)
+#define WSYS_ETMCNTCTLR2(val)		MCR(val, 14, 1, c0, c6, 5)
+#define WSYS_ETMCNTCTLR3(val)		MCR(val, 14, 1, c0, c7, 5)
+#define WSYS_ETMCNTRLDVR0(val)		MCR(val, 14, 1, c0, c0, 5)
+#define WSYS_ETMCNTRLDVR1(val)		MCR(val, 14, 1, c0, c1, 5)
+#define WSYS_ETMCNTRLDVR2(val)		MCR(val, 14, 1, c0, c2, 5)
+#define WSYS_ETMCNTRLDVR3(val)		MCR(val, 14, 1, c0, c3, 5)
+#define WSYS_ETMCNTVR0(val)		MCR(val, 14, 1, c0, c8, 5)
+#define WSYS_ETMCNTVR1(val)		MCR(val, 14, 1, c0, c9, 5)
+#define WSYS_ETMCNTVR2(val)		MCR(val, 14, 1, c0, c10, 5)
+#define WSYS_ETMCNTVR3(val)		MCR(val, 14, 1, c0, c11, 5)
+#define WSYS_ETMCONFIGR(val)		MCR(val, 14, 1, c0, c4, 0)
+#define WSYS_ETMEVENTCTL0R(val)		MCR(val, 14, 1, c0, c8, 0)
+#define WSYS_ETMEVENTCTL1R(val)		MCR(val, 14, 1, c0, c9, 0)
+#define WSYS_ETMEXTINSELR(val)		MCR(val, 14, 1, c0, c8, 4)
+#define WSYS_ETMIMSPEC0(val)		MCR(val, 14, 1, c0, c0, 7)
+#define WSYS_ETMOSLAR(val)		MCR(val, 14, 1, c1, c0, 4)
+#define WSYS_ETMPRGCTLR(val)		MCR(val, 14, 1, c0, c1, 0)
+#define WSYS_ETMRSCTLR10(val)		MCR(val, 14, 1, c1, c10, 0)
+#define WSYS_ETMRSCTLR11(val)		MCR(val, 14, 1, c1, c11, 0)
+#define WSYS_ETMRSCTLR12(val)		MCR(val, 14, 1, c1, c12, 0)
+#define WSYS_ETMRSCTLR13(val)		MCR(val, 14, 1, c1, c13, 0)
+#define WSYS_ETMRSCTLR14(val)		MCR(val, 14, 1, c1, c14, 0)
+#define WSYS_ETMRSCTLR15(val)		MCR(val, 14, 1, c1, c15, 0)
+#define WSYS_ETMRSCTLR2(val)		MCR(val, 14, 1, c1, c2, 0)
+#define WSYS_ETMRSCTLR3(val)		MCR(val, 14, 1, c1, c3, 0)
+#define WSYS_ETMRSCTLR4(val)		MCR(val, 14, 1, c1, c4, 0)
+#define WSYS_ETMRSCTLR5(val)		MCR(val, 14, 1, c1, c5, 0)
+#define WSYS_ETMRSCTLR6(val)		MCR(val, 14, 1, c1, c6, 0)
+#define WSYS_ETMRSCTLR7(val)		MCR(val, 14, 1, c1, c7, 0)
+#define WSYS_ETMRSCTLR8(val)		MCR(val, 14, 1, c1, c8, 0)
+#define WSYS_ETMRSCTLR9(val)		MCR(val, 14, 1, c1, c9, 0)
+#define WSYS_ETMRSCTLR16(val)		MCR(val, 14, 1, c1, c0, 1)
+#define WSYS_ETMRSCTLR17(val)		MCR(val, 14, 1, c1, c1, 1)
+#define WSYS_ETMRSCTLR18(val)		MCR(val, 14, 1, c1, c2, 1)
+#define WSYS_ETMRSCTLR19(val)		MCR(val, 14, 1, c1, c3, 1)
+#define WSYS_ETMRSCTLR20(val)		MCR(val, 14, 1, c1, c4, 1)
+#define WSYS_ETMRSCTLR21(val)		MCR(val, 14, 1, c1, c5, 1)
+#define WSYS_ETMRSCTLR22(val)		MCR(val, 14, 1, c1, c6, 1)
+#define WSYS_ETMRSCTLR23(val)		MCR(val, 14, 1, c1, c7, 1)
+#define WSYS_ETMRSCTLR24(val)		MCR(val, 14, 1, c1, c8, 1)
+#define WSYS_ETMRSCTLR25(val)		MCR(val, 14, 1, c1, c9, 1)
+#define WSYS_ETMRSCTLR26(val)		MCR(val, 14, 1, c1, c10, 1)
+#define WSYS_ETMRSCTLR27(val)		MCR(val, 14, 1, c1, c11, 1)
+#define WSYS_ETMRSCTLR28(val)		MCR(val, 14, 1, c1, c12, 1)
+#define WSYS_ETMRSCTLR29(val)		MCR(val, 14, 1, c1, c13, 1)
+#define WSYS_ETMRSCTLR30(val)		MCR(val, 14, 1, c1, c14, 1)
+#define WSYS_ETMRSCTLR31(val)		MCR(val, 14, 1, c1, c15, 1)
+#define WSYS_ETMSEQEVR0(val)		MCR(val, 14, 1, c0, c0, 4)
+#define WSYS_ETMSEQEVR1(val)		MCR(val, 14, 1, c0, c1, 4)
+#define WSYS_ETMSEQEVR2(val)		MCR(val, 14, 1, c0, c2, 4)
+#define WSYS_ETMSEQRSTEVR(val)		MCR(val, 14, 1, c0, c6, 4)
+#define WSYS_ETMSEQSTR(val)		MCR(val, 14, 1, c0, c7, 4)
+#define WSYS_ETMSTALLCTLR(val)		MCR(val, 14, 1, c0, c11, 0)
+#define WSYS_ETMSYNCPR(val)		MCR(val, 14, 1, c0, c13, 0)
+#define WSYS_ETMTRACEIDR(val)		MCR(val, 14, 1, c0, c0, 1)
+#define WSYS_ETMTSCTLR(val)		MCR(val, 14, 1, c0, c12, 0)
+#define WSYS_ETMVICTLR(val)		MCR(val, 14, 1, c0, c0, 2)
+#define WSYS_ETMVIIECTLR(val)		MCR(val, 14, 1, c0, c1, 2)
+#define WSYS_ETMVISSCTLR(val)		MCR(val, 14, 1, c0, c2, 2)
+#define WSYS_ETMVMIDCVR0(val)		MCR(val, 14, 1, c3, c0, 1)
+#define WSYS_ETMVMIDCVR1(val)		MCR(val, 14, 1, c3, c2, 1)
+#define WSYS_ETMVMIDCVR2(val)		MCR(val, 14, 1, c3, c4, 1)
+#define WSYS_ETMVMIDCVR3(val)		MCR(val, 14, 1, c3, c6, 1)
+#define WSYS_ETMVMIDCVR4(val)		MCR(val, 14, 1, c3, c8, 1)
+#define WSYS_ETMVMIDCVR5(val)		MCR(val, 14, 1, c3, c10, 1)
+#define WSYS_ETMVMIDCVR6(val)		MCR(val, 14, 1, c3, c12, 1)
+#define WSYS_ETMVMIDCVR7(val)		MCR(val, 14, 1, c3, c14, 1)
+#define WSYS_ETMDVCVR0(val)		MCR(val, 14, 1, c2, c0, 4)
+#define WSYS_ETMDVCVR1(val)		MCR(val, 14, 1, c2, c4, 4)
+#define WSYS_ETMDVCVR2(val)		MCR(val, 14, 1, c2, c8, 4)
+#define WSYS_ETMDVCVR3(val)		MCR(val, 14, 1, c2, c12, 4)
+#define WSYS_ETMDVCVR4(val)		MCR(val, 14, 1, c2, c0, 5)
+#define WSYS_ETMDVCVR5(val)		MCR(val, 14, 1, c2, c4, 5)
+#define WSYS_ETMDVCVR6(val)		MCR(val, 14, 1, c2, c8, 5)
+#define WSYS_ETMDVCVR7(val)		MCR(val, 14, 1, c2, c12, 5)
+#define WSYS_ETMDVCMR0(val)		MCR(val, 14, 1, c2, c0, 6)
+#define WSYS_ETMDVCMR1(val)		MCR(val, 14, 1, c2, c4, 6)
+#define WSYS_ETMDVCMR2(val)		MCR(val, 14, 1, c2, c8, 6)
+#define WSYS_ETMDVCMR3(val)		MCR(val, 14, 1, c2, c12, 6)
+#define WSYS_ETMDVCMR4(val)		MCR(val, 14, 1, c2, c0, 7)
+#define WSYS_ETMDVCMR5(val)		MCR(val, 14, 1, c2, c4, 7)
+#define WSYS_ETMDVCMR6(val)		MCR(val, 14, 1, c2, c8, 7)
+#define WSYS_ETMDVCMR7(val)		MCR(val, 14, 1, c2, c12, 7)
+#define WSYS_ETMSSCCR0(val)		MCR(val, 14, 1, c1, c0, 2)
+#define WSYS_ETMSSCCR1(val)		MCR(val, 14, 1, c1, c1, 2)
+#define WSYS_ETMSSCCR2(val)		MCR(val, 14, 1, c1, c2, 2)
+#define WSYS_ETMSSCCR3(val)		MCR(val, 14, 1, c1, c3, 2)
+#define WSYS_ETMSSCCR4(val)		MCR(val, 14, 1, c1, c4, 2)
+#define WSYS_ETMSSCCR5(val)		MCR(val, 14, 1, c1, c5, 2)
+#define WSYS_ETMSSCCR6(val)		MCR(val, 14, 1, c1, c6, 2)
+#define WSYS_ETMSSCCR7(val)		MCR(val, 14, 1, c1, c7, 2)
+#define WSYS_ETMSSCSR0(val)		MCR(val, 14, 1, c1, c8, 2)
+#define WSYS_ETMSSCSR1(val)		MCR(val, 14, 1, c1, c9, 2)
+#define WSYS_ETMSSCSR2(val)		MCR(val, 14, 1, c1, c10, 2)
+#define WSYS_ETMSSCSR3(val)		MCR(val, 14, 1, c1, c11, 2)
+#define WSYS_ETMSSCSR4(val)		MCR(val, 14, 1, c1, c12, 2)
+#define WSYS_ETMSSCSR5(val)		MCR(val, 14, 1, c1, c13, 2)
+#define WSYS_ETMSSCSR6(val)		MCR(val, 14, 1, c1, c14, 2)
+#define WSYS_ETMSSCSR7(val)		MCR(val, 14, 1, c1, c15, 2)
+#define WSYS_ETMSSPCICR0(val)		MCR(val, 14, 1, c1, c0, 3)
+#define WSYS_ETMSSPCICR1(val)		MCR(val, 14, 1, c1, c1, 3)
+#define WSYS_ETMSSPCICR2(val)		MCR(val, 14, 1, c1, c2, 3)
+#define WSYS_ETMSSPCICR3(val)		MCR(val, 14, 1, c1, c3, 3)
+#define WSYS_ETMSSPCICR4(val)		MCR(val, 14, 1, c1, c4, 3)
+#define WSYS_ETMSSPCICR5(val)		MCR(val, 14, 1, c1, c5, 3)
+#define WSYS_ETMSSPCICR6(val)		MCR(val, 14, 1, c1, c6, 3)
+#define WSYS_ETMSSPCICR7(val)		MCR(val, 14, 1, c1, c7, 3)
+
+#endif

arch/arm/include/asm/hardware/debugv8.h

@@ -0,0 +1,248 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2016, 2018, 2021, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_HARDWARE_DEBUGV8_H
+#define __ASM_HARDWARE_DEBUGV8_H
+
+#include <linux/types.h>
+
+/* Accessors for CP14 registers */
+#define dbg_read(reg)			RCP14_##reg()
+#define dbg_write(val, reg)		WCP14_##reg(val)
+
+/* MRC14 registers */
+#define MRC14(op1, crn, crm, op2)					\
+({									\
+uint32_t val;								\
+asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val));	\
+val;									\
+})
+
+/* MCR14 registers */
+#define MCR14(val, op1, crn, crm, op2)					\
+({									\
+asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
+})
+
+/*
+ * Debug Registers
+ *
+ * Read only
+ * DBGDIDR, DBGDSCRint, DBGDTRRXint, DBGDRAR, DBGOSLSR, DBGOSSRR, DBGDSAR,
+ * DBGAUTHSTATUS, DBGDEVID2, DBGDEVID1, DBGDEVID
+ *
+ * Write only
+ * DBGDTRTXint, DBGOSLAR
+ */
+#define RCP14_DBGDIDR()			MRC14(0, c0, c0, 0)
+#define RCP14_DBGDSCRint()		MRC14(0, c0, c1, 0)
+#define RCP14_DBGDCCINT()		MRC14(0, c0, c2, 0)
+#define RCP14_DBGDTRRXint()		MRC14(0, c0, c5, 0)
+#define RCP14_DBGWFAR()			MRC14(0, c0, c6, 0)
+#define RCP14_DBGVCR()			MRC14(0, c0, c7, 0)
+#define RCP14_DBGDTRRXext()		MRC14(0, c0, c0, 2)
+#define RCP14_DBGDSCRext()		MRC14(0, c0, c2, 2)
+#define RCP14_DBGDTRTXext()		MRC14(0, c0, c3, 2)
+#define RCP14_DBGOSECCR()		MRC14(0, c0, c6, 2)
+#define RCP14_DBGBVR0()			MRC14(0, c0, c0, 4)
+#define RCP14_DBGBVR1()			MRC14(0, c0, c1, 4)
+#define RCP14_DBGBVR2()			MRC14(0, c0, c2, 4)
+#define RCP14_DBGBVR3()			MRC14(0, c0, c3, 4)
+#define RCP14_DBGBVR4()			MRC14(0, c0, c4, 4)
+#define RCP14_DBGBVR5()			MRC14(0, c0, c5, 4)
+#define RCP14_DBGBVR6()			MRC14(0, c0, c6, 4)
+#define RCP14_DBGBVR7()			MRC14(0, c0, c7, 4)
+#define RCP14_DBGBVR8()			MRC14(0, c0, c8, 4)
+#define RCP14_DBGBVR9()			MRC14(0, c0, c9, 4)
+#define RCP14_DBGBVR10()		MRC14(0, c0, c10, 4)
+#define RCP14_DBGBVR11()		MRC14(0, c0, c11, 4)
+#define RCP14_DBGBVR12()		MRC14(0, c0, c12, 4)
+#define RCP14_DBGBVR13()		MRC14(0, c0, c13, 4)
+#define RCP14_DBGBVR14()		MRC14(0, c0, c14, 4)
+#define RCP14_DBGBVR15()		MRC14(0, c0, c15, 4)
+#define RCP14_DBGBCR0()			MRC14(0, c0, c0, 5)
+#define RCP14_DBGBCR1()			MRC14(0, c0, c1, 5)
+#define RCP14_DBGBCR2()			MRC14(0, c0, c2, 5)
+#define RCP14_DBGBCR3()			MRC14(0, c0, c3, 5)
+#define RCP14_DBGBCR4()			MRC14(0, c0, c4, 5)
+#define RCP14_DBGBCR5()			MRC14(0, c0, c5, 5)
+#define RCP14_DBGBCR6()			MRC14(0, c0, c6, 5)
+#define RCP14_DBGBCR7()			MRC14(0, c0, c7, 5)
+#define RCP14_DBGBCR8()			MRC14(0, c0, c8, 5)
+#define RCP14_DBGBCR9()			MRC14(0, c0, c9, 5)
+#define RCP14_DBGBCR10()		MRC14(0, c0, c10, 5)
+#define RCP14_DBGBCR11()		MRC14(0, c0, c11, 5)
+#define RCP14_DBGBCR12()		MRC14(0, c0, c12, 5)
+#define RCP14_DBGBCR13()		MRC14(0, c0, c13, 5)
+#define RCP14_DBGBCR14()		MRC14(0, c0, c14, 5)
+#define RCP14_DBGBCR15()		MRC14(0, c0, c15, 5)
+#define RCP14_DBGWVR0()			MRC14(0, c0, c0, 6)
+#define RCP14_DBGWVR1()			MRC14(0, c0, c1, 6)
+#define RCP14_DBGWVR2()			MRC14(0, c0, c2, 6)
+#define RCP14_DBGWVR3()			MRC14(0, c0, c3, 6)
+#define RCP14_DBGWVR4()			MRC14(0, c0, c4, 6)
+#define RCP14_DBGWVR5()			MRC14(0, c0, c5, 6)
+#define RCP14_DBGWVR6()			MRC14(0, c0, c6, 6)
+#define RCP14_DBGWVR7()			MRC14(0, c0, c7, 6)
+#define RCP14_DBGWVR8()			MRC14(0, c0, c8, 6)
+#define RCP14_DBGWVR9()			MRC14(0, c0, c9, 6)
+#define RCP14_DBGWVR10()		MRC14(0, c0, c10, 6)
+#define RCP14_DBGWVR11()		MRC14(0, c0, c11, 6)
+#define RCP14_DBGWVR12()		MRC14(0, c0, c12, 6)
+#define RCP14_DBGWVR13()		MRC14(0, c0, c13, 6)
+#define RCP14_DBGWVR14()		MRC14(0, c0, c14, 6)
+#define RCP14_DBGWVR15()		MRC14(0, c0, c15, 6)
+#define RCP14_DBGWCR0()			MRC14(0, c0, c0, 7)
+#define RCP14_DBGWCR1()			MRC14(0, c0, c1, 7)
+#define RCP14_DBGWCR2()			MRC14(0, c0, c2, 7)
+#define RCP14_DBGWCR3()			MRC14(0, c0, c3, 7)
+#define RCP14_DBGWCR4()			MRC14(0, c0, c4, 7)
+#define RCP14_DBGWCR5()			MRC14(0, c0, c5, 7)
+#define RCP14_DBGWCR6()			MRC14(0, c0, c6, 7)
+#define RCP14_DBGWCR7()			MRC14(0, c0, c7, 7)
+#define RCP14_DBGWCR8()			MRC14(0, c0, c8, 7)
+#define RCP14_DBGWCR9()			MRC14(0, c0, c9, 7)
+#define RCP14_DBGWCR10()		MRC14(0, c0, c10, 7)
+#define RCP14_DBGWCR11()		MRC14(0, c0, c11, 7)
+#define RCP14_DBGWCR12()		MRC14(0, c0, c12, 7)
+#define RCP14_DBGWCR13()		MRC14(0, c0, c13, 7)
+#define RCP14_DBGWCR14()		MRC14(0, c0, c14, 7)
+#define RCP14_DBGWCR15()		MRC14(0, c0, c15, 7)
+#define RCP14_DBGDRAR()			MRC14(0, c1, c0, 0)
+#define RCP14_DBGBXVR0()		MRC14(0, c1, c0, 1)
+#define RCP14_DBGBXVR1()		MRC14(0, c1, c1, 1)
+#define RCP14_DBGBXVR2()		MRC14(0, c1, c2, 1)
+#define RCP14_DBGBXVR3()		MRC14(0, c1, c3, 1)
+#define RCP14_DBGBXVR4()		MRC14(0, c1, c4, 1)
+#define RCP14_DBGBXVR5()		MRC14(0, c1, c5, 1)
+#define RCP14_DBGBXVR6()		MRC14(0, c1, c6, 1)
+#define RCP14_DBGBXVR7()		MRC14(0, c1, c7, 1)
+#define RCP14_DBGBXVR8()		MRC14(0, c1, c8, 1)
+#define RCP14_DBGBXVR9()		MRC14(0, c1, c9, 1)
+#define RCP14_DBGBXVR10()		MRC14(0, c1, c10, 1)
+#define RCP14_DBGBXVR11()		MRC14(0, c1, c11, 1)
+#define RCP14_DBGBXVR12()		MRC14(0, c1, c12, 1)
+#define RCP14_DBGBXVR13()		MRC14(0, c1, c13, 1)
+#define RCP14_DBGBXVR14()		MRC14(0, c1, c14, 1)
+#define RCP14_DBGBXVR15()		MRC14(0, c1, c15, 1)
+#define RCP14_DBGOSLSR()		MRC14(0, c1, c1, 4)
+#define RCP14_DBGOSSRR()		MRC14(0, c1, c2, 4)
+#define RCP14_DBGOSDLR()		MRC14(0, c1, c3, 4)
+#define RCP14_DBGPRCR()			MRC14(0, c1, c4, 4)
+#define RCP14_DBGPRSR()			MRC14(0, c1, c5, 4)
+#define RCP14_DBGDSAR()			MRC14(0, c2, c0, 0)
+#define RCP14_DBGITCTRL()		MRC14(0, c7, c0, 4)
+#define RCP14_DBGCLAIMSET()		MRC14(0, c7, c8, 6)
+#define RCP14_DBGCLAIMCLR()		MRC14(0, c7, c9, 6)
+#define RCP14_DBGAUTHSTATUS()		MRC14(0, c7, c14, 6)
+#define RCP14_DBGDEVID2()		MRC14(0, c7, c0, 7)
+#define RCP14_DBGDEVID1()		MRC14(0, c7, c1, 7)
+#define RCP14_DBGDEVID()		MRC14(0, c7, c2, 7)
+
+#define WCP14_DBGDCCINT(val)		MCR14(val, 0, c0, c2, 0)
+#define WCP14_DBGDTRTXint(val)		MCR14(val, 0, c0, c5, 0)
+#define WCP14_DBGWFAR(val)		MCR14(val, 0, c0, c6, 0)
+#define WCP14_DBGVCR(val)		MCR14(val, 0, c0, c7, 0)
+#define WCP14_DBGDTRRXext(val)		MCR14(val, 0, c0, c0, 2)
+#define WCP14_DBGDSCRext(val)		MCR14(val, 0, c0, c2, 2)
+#define WCP14_DBGDTRTXext(val)		MCR14(val, 0, c0, c3, 2)
+#define WCP14_DBGOSECCR(val)		MCR14(val, 0, c0, c6, 2)
+#define WCP14_DBGBVR0(val)		MCR14(val, 0, c0, c0, 4)
+#define WCP14_DBGBVR1(val)		MCR14(val, 0, c0, c1, 4)
+#define WCP14_DBGBVR2(val)		MCR14(val, 0, c0, c2, 4)
+#define WCP14_DBGBVR3(val)		MCR14(val, 0, c0, c3, 4)
+#define WCP14_DBGBVR4(val)		MCR14(val, 0, c0, c4, 4)
+#define WCP14_DBGBVR5(val)		MCR14(val, 0, c0, c5, 4)
+#define WCP14_DBGBVR6(val)		MCR14(val, 0, c0, c6, 4)
+#define WCP14_DBGBVR7(val)		MCR14(val, 0, c0, c7, 4)
+#define WCP14_DBGBVR8(val)		MCR14(val, 0, c0, c8, 4)
+#define WCP14_DBGBVR9(val)		MCR14(val, 0, c0, c9, 4)
+#define WCP14_DBGBVR10(val)		MCR14(val, 0, c0, c10, 4)
+#define WCP14_DBGBVR11(val)		MCR14(val, 0, c0, c11, 4)
+#define WCP14_DBGBVR12(val)		MCR14(val, 0, c0, c12, 4)
+#define WCP14_DBGBVR13(val)		MCR14(val, 0, c0, c13, 4)
+#define WCP14_DBGBVR14(val)		MCR14(val, 0, c0, c14, 4)
+#define WCP14_DBGBVR15(val)		MCR14(val, 0, c0, c15, 4)
+#define WCP14_DBGBCR0(val)		MCR14(val, 0, c0, c0, 5)
+#define WCP14_DBGBCR1(val)		MCR14(val, 0, c0, c1, 5)
+#define WCP14_DBGBCR2(val)		MCR14(val, 0, c0, c2, 5)
+#define WCP14_DBGBCR3(val)		MCR14(val, 0, c0, c3, 5)
+#define WCP14_DBGBCR4(val)		MCR14(val, 0, c0, c4, 5)
+#define WCP14_DBGBCR5(val)		MCR14(val, 0, c0, c5, 5)
+#define WCP14_DBGBCR6(val)		MCR14(val, 0, c0, c6, 5)
+#define WCP14_DBGBCR7(val)		MCR14(val, 0, c0, c7, 5)
+#define WCP14_DBGBCR8(val)		MCR14(val, 0, c0, c8, 5)
+#define WCP14_DBGBCR9(val)		MCR14(val, 0, c0, c9, 5)
+#define WCP14_DBGBCR10(val)		MCR14(val, 0, c0, c10, 5)
+#define WCP14_DBGBCR11(val)		MCR14(val, 0, c0, c11, 5)
+#define WCP14_DBGBCR12(val)		MCR14(val, 0, c0, c12, 5)
+#define WCP14_DBGBCR13(val)		MCR14(val, 0, c0, c13, 5)
+#define WCP14_DBGBCR14(val)		MCR14(val, 0, c0, c14, 5)
+#define WCP14_DBGBCR15(val)		MCR14(val, 0, c0, c15, 5)
+#define WCP14_DBGWVR0(val)		MCR14(val, 0, c0, c0, 6)
+#define WCP14_DBGWVR1(val)		MCR14(val, 0, c0, c1, 6)
+#define WCP14_DBGWVR2(val)		MCR14(val, 0, c0, c2, 6)
+#define WCP14_DBGWVR3(val)		MCR14(val, 0, c0, c3, 6)
+#define WCP14_DBGWVR4(val)		MCR14(val, 0, c0, c4, 6)
+#define WCP14_DBGWVR5(val)		MCR14(val, 0, c0, c5, 6)
+#define WCP14_DBGWVR6(val)		MCR14(val, 0, c0, c6, 6)
+#define WCP14_DBGWVR7(val)		MCR14(val, 0, c0, c7, 6)
+#define WCP14_DBGWVR8(val)		MCR14(val, 0, c0, c8, 6)
+#define WCP14_DBGWVR9(val)		MCR14(val, 0, c0, c9, 6)
+#define WCP14_DBGWVR10(val)		MCR14(val, 0, c0, c10, 6)
+#define WCP14_DBGWVR11(val)		MCR14(val, 0, c0, c11, 6)
+#define WCP14_DBGWVR12(val)		MCR14(val, 0, c0, c12, 6)
+#define WCP14_DBGWVR13(val)		MCR14(val, 0, c0, c13, 6)
+#define WCP14_DBGWVR14(val)		MCR14(val, 0, c0, c14, 6)
+#define WCP14_DBGWVR15(val)		MCR14(val, 0, c0, c15, 6)
+#define WCP14_DBGWCR0(val)		MCR14(val, 0, c0, c0, 7)
+#define WCP14_DBGWCR1(val)		MCR14(val, 0, c0, c1, 7)
+#define WCP14_DBGWCR2(val)		MCR14(val, 0, c0, c2, 7)
+#define WCP14_DBGWCR3(val)		MCR14(val, 0, c0, c3, 7)
+#define WCP14_DBGWCR4(val)		MCR14(val, 0, c0, c4, 7)
+#define WCP14_DBGWCR5(val)		MCR14(val, 0, c0, c5, 7)
+#define WCP14_DBGWCR6(val)		MCR14(val, 0, c0, c6, 7)
+#define WCP14_DBGWCR7(val)		MCR14(val, 0, c0, c7, 7)
+#define WCP14_DBGWCR8(val)		MCR14(val, 0, c0, c8, 7)
+#define WCP14_DBGWCR9(val)		MCR14(val, 0, c0, c9, 7)
+#define WCP14_DBGWCR10(val)		MCR14(val, 0, c0, c10, 7)
+#define WCP14_DBGWCR11(val)		MCR14(val, 0, c0, c11, 7)
+#define WCP14_DBGWCR12(val)		MCR14(val, 0, c0, c12, 7)
+#define WCP14_DBGWCR13(val)		MCR14(val, 0, c0, c13, 7)
+#define WCP14_DBGWCR14(val)		MCR14(val, 0, c0, c14, 7)
+#define WCP14_DBGWCR15(val)		MCR14(val, 0, c0, c15, 7)
+#define WCP14_DBGBXVR0(val)		MCR14(val, 0, c1, c0, 1)
+#define WCP14_DBGBXVR1(val)		MCR14(val, 0, c1, c1, 1)
+#define WCP14_DBGBXVR2(val)		MCR14(val, 0, c1, c2, 1)
+#define WCP14_DBGBXVR3(val)		MCR14(val, 0, c1, c3, 1)
+#define WCP14_DBGBXVR4(val)		MCR14(val, 0, c1, c4, 1)
+#define WCP14_DBGBXVR5(val)		MCR14(val, 0, c1, c5, 1)
+#define WCP14_DBGBXVR6(val)		MCR14(val, 0, c1, c6, 1)
+#define WCP14_DBGBXVR7(val)		MCR14(val, 0, c1, c7, 1)
+#define WCP14_DBGBXVR8(val)		MCR14(val, 0, c1, c8, 1)
+#define WCP14_DBGBXVR9(val)		MCR14(val, 0, c1, c9, 1)
+#define WCP14_DBGBXVR10(val)		MCR14(val, 0, c1, c10, 1)
+#define WCP14_DBGBXVR11(val)		MCR14(val, 0, c1, c11, 1)
+#define WCP14_DBGBXVR12(val)		MCR14(val, 0, c1, c12, 1)
+#define WCP14_DBGBXVR13(val)		MCR14(val, 0, c1, c13, 1)
+#define WCP14_DBGBXVR14(val)		MCR14(val, 0, c1, c14, 1)
+#define WCP14_DBGBXVR15(val)		MCR14(val, 0, c1, c15, 1)
+#define WCP14_DBGOSLAR(val)		MCR14(val, 0, c1, c0, 4)
+#define WCP14_DBGOSSRR(val)		MCR14(val, 0, c1, c2, 4)
+#define WCP14_DBGOSDLR(val)		MCR14(val, 0, c1, c3, 4)
+#define WCP14_DBGPRCR(val)		MCR14(val, 0, c1, c4, 4)
+#define WCP14_DBGITCTRL(val)		MCR14(val, 0, c7, c0, 4)
+#define WCP14_DBGCLAIMSET(val)		MCR14(val, 0, c7, c8, 6)
+#define WCP14_DBGCLAIMCLR(val)		MCR14(val, 0, c7, c9, 6)
+
+#endif

arch/arm/include/asm/hw_breakpoint.h

@@ -53,6 +53,7 @@ static inline void decode_ctrl_reg(u32 reg,
 #define ARM_DEBUG_ARCH_V7_MM	4
 #define ARM_DEBUG_ARCH_V7_1	5
 #define ARM_DEBUG_ARCH_V8	6
+#define ARM_DEBUG_ARCH_V8_8	8
 
 /* Breakpoint */
 #define ARM_BREAKPOINT_EXECUTE	0

arch/arm64/Kconfig.platforms

@@ -183,6 +183,14 @@ config ARCH_BENGAL
 	  This enables support for the BENGAL chipset. If you do not
 	  wish to build a kernel that runs on this chipset, say 'N' here.
 
+config ARCH_KHAJE
+	bool "Enable Support for Qualcomm Technologies, Inc. KHAJE"
+	depends on ARCH_QCOM
+	select COMMON_CLK_QCOM
+	help
+	  This enables support for the KHAJE chipset. If you do not
+	  wish to build a kernel that runs on this chipset, say 'N' here.
+
 config ARCH_SCUBA
 	bool "Enable Support for Qualcomm Technologies, Inc. SCUBA"
 	depends on ARCH_QCOM

arch/arm64/configs/gki_defconfig

@@ -484,7 +484,6 @@ CONFIG_NLS_MAC_ROMANIAN=y
 CONFIG_NLS_MAC_TURKISH=y
 CONFIG_NLS_UTF8=y
 CONFIG_UNICODE=y
-CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
 CONFIG_SECURITY=y
 CONFIG_SECURITYFS=y
 CONFIG_SECURITY_NETWORK=y

arch/arm64/configs/vendor/bengal-perf_defconfig

@@ -50,6 +50,7 @@ CONFIG_PROFILING=y
 CONFIG_HOTPLUG_SIZE_BITS=29
 CONFIG_ARCH_QCOM=y
 CONFIG_ARCH_BENGAL=y
+CONFIG_ARCH_KHAJE=y
 CONFIG_ARCH_SCUBA=y
 CONFIG_SCHED_MC=y
 CONFIG_NR_CPUS=8
@@ -63,6 +64,8 @@ CONFIG_SETEND_EMULATION=y
 CONFIG_ARM64_SW_TTBR0_PAN=y
 # CONFIG_ARM64_VHE is not set
 CONFIG_RANDOMIZE_BASE=y
+CONFIG_CMDLINE="cgroup_disable=pressure"
+CONFIG_CMDLINE_EXTEND=y
 CONFIG_COMPAT=y
 CONFIG_PM_WAKELOCKS=y
 CONFIG_PM_WAKELOCKS_LIMIT=0
@@ -363,6 +366,7 @@ CONFIG_SPI_SPIDEV=y
 CONFIG_SPMI=y
 CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
 CONFIG_PINCTRL_BENGAL=y
+CONFIG_PINCTRL_KHAJE=y
 CONFIG_PINCTRL_SCUBA=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_POWER_RESET_QCOM=y
@@ -372,8 +376,10 @@ CONFIG_QPNP_SMB5=y
 CONFIG_QPNP_SMBLITE=y
 CONFIG_SMB1355_SLAVE_CHARGER=y
 CONFIG_QPNP_QG=y
+CONFIG_SMB1398_CHARGER=y
 CONFIG_THERMAL=y
 CONFIG_THERMAL_STATISTICS=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=10000
 CONFIG_THERMAL_WRITABLE_TRIPS=y
 CONFIG_THERMAL_GOV_USER_SPACE=y
 CONFIG_THERMAL_GOV_LOW_LIMITS=y
@@ -389,6 +395,7 @@ CONFIG_QTI_BCL_SOC_DRIVER=y
 CONFIG_QTI_QMI_COOLING_DEVICE=y
 CONFIG_QTI_THERMAL_LIMITS_DCVS=y
 CONFIG_REGULATOR_COOLING_DEVICE=y
+CONFIG_QTI_RPM_SMD_COOLING_DEVICE=y
 CONFIG_QTI_CPU_ISOLATE_COOLING_DEVICE=y
 CONFIG_QTI_LMH_CPU_VDD_COOLING_DEVICE=y
 CONFIG_QTI_CX_IPEAK_COOLING_DEVICE=y
@@ -399,6 +406,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_PROXY_CONSUMER=y
 CONFIG_REGULATOR_QCOM_SMD_RPM=y
 CONFIG_REGULATOR_QPNP_LCDB=y
+CONFIG_REGULATOR_REFGEN=y
 CONFIG_REGULATOR_RPM_SMD=y
 CONFIG_REGULATOR_STUB=y
 CONFIG_REGULATOR_PM8008=y
@@ -446,6 +454,7 @@ CONFIG_USB_LINK_LAYER_TEST=y
 CONFIG_NOP_USB_XCEIV=y
 CONFIG_USB_MSM_SSPHY_QMP=y
 CONFIG_MSM_QUSB_PHY=y
+CONFIG_MSM_HSUSB_PHY=y
 CONFIG_USB_QCOM_EMU_PHY=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_VBUS_DRAW=900
@@ -466,6 +475,8 @@ CONFIG_USB_CONFIGFS_F_GSI=y
 CONFIG_USB_CONFIGFS_F_MTP=y
 CONFIG_USB_CONFIGFS_F_PTP=y
 CONFIG_TYPEC=y
+CONFIG_USB_PD_POLICY=y
+CONFIG_QPNP_USB_PDPHY=y
 CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=32
 CONFIG_MMC_BLOCK_DEFERRED_RESUME=y
@@ -477,6 +488,7 @@ CONFIG_MMC_CQHCI_CRYPTO_QTI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_CLASS_FLASH=y
+CONFIG_LEDS_AW2016=y
 CONFIG_LEDS_QTI_FLASH=y
 CONFIG_LEDS_PWM=y
 CONFIG_LEDS_QTI_TRI_LED=y
@@ -492,6 +504,7 @@ CONFIG_UIO_MSM_SHAREDMEM=y
 CONFIG_STAGING=y
 CONFIG_ASHMEM=y
 CONFIG_ION=y
+CONFIG_ION_SYSTEM_HEAP=y
 CONFIG_ION_POOL_AUTO_REFILL=y
 CONFIG_QPNP_REVID=y
 CONFIG_SPS=y
@@ -511,6 +524,9 @@ CONFIG_SM_DEBUGCC_BENGAL=y
 CONFIG_QM_DISPCC_SCUBA=y
 CONFIG_QM_GPUCC_SCUBA=y
 CONFIG_QM_DEBUGCC_SCUBA=y
+CONFIG_SM_GPUCC_KHAJE=y
+CONFIG_SM_DISPCC_KHAJE=y
+CONFIG_SM_DEBUGCC_KHAJE=y
 CONFIG_HWSPINLOCK=y
 CONFIG_HWSPINLOCK_QCOM=y
 CONFIG_MAILBOX=y
@@ -625,7 +641,6 @@ CONFIG_SDCARD_FS=y
 # CONFIG_NETWORK_FILESYSTEMS is not set
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
 CONFIG_SECURITY=y
 CONFIG_HARDENED_USERCOPY=y
 CONFIG_HARDENED_USERCOPY_PAGESPAN=y

arch/arm64/configs/vendor/bengal_defconfig

@@ -51,6 +51,7 @@ CONFIG_PROFILING=y
 CONFIG_HOTPLUG_SIZE_BITS=29
 CONFIG_ARCH_QCOM=y
 CONFIG_ARCH_BENGAL=y
+CONFIG_ARCH_KHAJE=y
 CONFIG_ARCH_SCUBA=y
 CONFIG_SCHED_MC=y
 CONFIG_NR_CPUS=8
@@ -65,6 +66,8 @@ CONFIG_SETEND_EMULATION=y
 CONFIG_ARM64_SW_TTBR0_PAN=y
 # CONFIG_ARM64_VHE is not set
 CONFIG_RANDOMIZE_BASE=y
+CONFIG_CMDLINE="cgroup_disable=pressure"
+CONFIG_CMDLINE_EXTEND=y
 CONFIG_COMPAT=y
 CONFIG_PM_WAKELOCKS=y
 CONFIG_PM_WAKELOCKS_LIMIT=0
@@ -376,6 +379,7 @@ CONFIG_SPI_SPIDEV=y
 CONFIG_SPMI=y
 CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
 CONFIG_PINCTRL_BENGAL=y
+CONFIG_PINCTRL_KHAJE=y
 CONFIG_PINCTRL_SCUBA=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_POWER_RESET_QCOM=y
@@ -385,8 +389,10 @@ CONFIG_QPNP_SMB5=y
 CONFIG_QPNP_SMBLITE=y
 CONFIG_SMB1355_SLAVE_CHARGER=y
 CONFIG_QPNP_QG=y
+CONFIG_SMB1398_CHARGER=y
 CONFIG_THERMAL=y
 CONFIG_THERMAL_STATISTICS=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=10000
 CONFIG_THERMAL_WRITABLE_TRIPS=y
 CONFIG_THERMAL_GOV_USER_SPACE=y
 CONFIG_THERMAL_GOV_LOW_LIMITS=y
@@ -402,6 +408,7 @@ CONFIG_QTI_BCL_SOC_DRIVER=y
 CONFIG_QTI_QMI_COOLING_DEVICE=y
 CONFIG_QTI_THERMAL_LIMITS_DCVS=y
 CONFIG_REGULATOR_COOLING_DEVICE=y
+CONFIG_QTI_RPM_SMD_COOLING_DEVICE=y
 CONFIG_QTI_CPU_ISOLATE_COOLING_DEVICE=y
 CONFIG_QTI_LMH_CPU_VDD_COOLING_DEVICE=y
 CONFIG_QTI_CX_IPEAK_COOLING_DEVICE=y
@@ -412,6 +419,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_PROXY_CONSUMER=y
 CONFIG_REGULATOR_QCOM_SMD_RPM=y
 CONFIG_REGULATOR_QPNP_LCDB=y
+CONFIG_REGULATOR_REFGEN=y
 CONFIG_REGULATOR_RPM_SMD=y
 CONFIG_REGULATOR_STUB=y
 CONFIG_REGULATOR_PM8008=y
@@ -460,6 +468,7 @@ CONFIG_USB_LINK_LAYER_TEST=y
 CONFIG_NOP_USB_XCEIV=y
 CONFIG_USB_MSM_SSPHY_QMP=y
 CONFIG_MSM_QUSB_PHY=y
+CONFIG_MSM_HSUSB_PHY=y
 CONFIG_USB_QCOM_EMU_PHY=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_VBUS_DRAW=900
@@ -480,6 +489,8 @@ CONFIG_USB_CONFIGFS_F_GSI=y
 CONFIG_USB_CONFIGFS_F_MTP=y
 CONFIG_USB_CONFIGFS_F_PTP=y
 CONFIG_TYPEC=y
+CONFIG_USB_PD_POLICY=y
+CONFIG_QPNP_USB_PDPHY=y
 CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=32
 CONFIG_MMC_BLOCK_DEFERRED_RESUME=y
@@ -492,6 +503,7 @@ CONFIG_MMC_CQHCI_CRYPTO_QTI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_CLASS_FLASH=y
+CONFIG_LEDS_AW2016=y
 CONFIG_LEDS_QTI_FLASH=y
 CONFIG_LEDS_PWM=y
 CONFIG_LEDS_QTI_TRI_LED=y
@@ -512,6 +524,7 @@ CONFIG_UIO_MSM_SHAREDMEM=y
 CONFIG_STAGING=y
 CONFIG_ASHMEM=y
 CONFIG_ION=y
+CONFIG_ION_SYSTEM_HEAP=y
 CONFIG_ION_POOL_AUTO_REFILL=y
 CONFIG_QPNP_REVID=y
 CONFIG_SPS=y
@@ -531,6 +544,9 @@ CONFIG_SM_DEBUGCC_BENGAL=y
 CONFIG_QM_DISPCC_SCUBA=y
 CONFIG_QM_GPUCC_SCUBA=y
 CONFIG_QM_DEBUGCC_SCUBA=y
+CONFIG_SM_GPUCC_KHAJE=y
+CONFIG_SM_DISPCC_KHAJE=y
+CONFIG_SM_DEBUGCC_KHAJE=y
 CONFIG_HWSPINLOCK=y
 CONFIG_HWSPINLOCK_QCOM=y
 CONFIG_MAILBOX=y
@@ -654,7 +670,6 @@ CONFIG_SDCARD_FS=y
 # CONFIG_NETWORK_FILESYSTEMS is not set
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
 CONFIG_SECURITY=y
 CONFIG_HARDENED_USERCOPY=y
 CONFIG_HARDENED_USERCOPY_PAGESPAN=y

arch/arm64/configs/vendor/kona-iot-perf_defconfig

@@ -396,6 +396,7 @@ CONFIG_QTI_QMI_COOLING_DEVICE=y
 CONFIG_QTI_THERMAL_LIMITS_DCVS=y
 CONFIG_QTI_CPU_ISOLATE_COOLING_DEVICE=y
 CONFIG_QTI_LIMITS_ISENSE_CDSP=y
+CONFIG_QTI_THERMAL_QFPROM=y
 CONFIG_MFD_I2C_PMIC=y
 CONFIG_MFD_SPMI_PMIC=y
 CONFIG_REGULATOR=y
@@ -664,7 +665,6 @@ CONFIG_ECRYPT_FS_MESSAGING=y
 CONFIG_SDCARD_FS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
 CONFIG_SECURITY=y
 CONFIG_HARDENED_USERCOPY=y
 CONFIG_FORTIFY_SOURCE=y

arch/arm64/configs/vendor/kona-iot_defconfig

@@ -412,6 +412,7 @@ CONFIG_QTI_QMI_COOLING_DEVICE=y
 CONFIG_QTI_THERMAL_LIMITS_DCVS=y
 CONFIG_QTI_CPU_ISOLATE_COOLING_DEVICE=y
 CONFIG_QTI_LIMITS_ISENSE_CDSP=y
+CONFIG_QTI_THERMAL_QFPROM=y
 CONFIG_MFD_I2C_PMIC=y
 CONFIG_MFD_SPMI_PMIC=y
 CONFIG_REGULATOR=y
@@ -698,7 +699,6 @@ CONFIG_SDCARD_FS=y
 # CONFIG_NETWORK_FILESYSTEMS is not set
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
 CONFIG_SECURITY=y
 CONFIG_HARDENED_USERCOPY=y
 CONFIG_HARDENED_USERCOPY_PAGESPAN=y

arch/arm64/configs/vendor/kona-perf_defconfig

@@ -63,6 +63,8 @@ CONFIG_ARM64_SW_TTBR0_PAN=y
 CONFIG_ARM64_LSE_ATOMICS=y
 # CONFIG_ARM64_VHE is not set
 CONFIG_RANDOMIZE_BASE=y
+CONFIG_CMDLINE="cgroup_disable=pressure"
+CONFIG_CMDLINE_EXTEND=y
 # CONFIG_EFI is not set
 CONFIG_BUILD_ARM64_UNCOMPRESSED_KERNEL=y
 CONFIG_KRYO_PMU_WORKAROUND=y
@@ -316,6 +318,7 @@ CONFIG_BONDING=y
 CONFIG_DUMMY=y
 CONFIG_TUN=y
 CONFIG_VETH=y
+CONFIG_AQFWD=y
 CONFIG_SKY2=y
 CONFIG_RMNET=y
 CONFIG_SMSC911X=y
@@ -459,7 +462,10 @@ CONFIG_HID_MICROSOFT=y
 CONFIG_HID_MULTITOUCH=y
 CONFIG_HID_NINTENDO=y
 CONFIG_HID_PLANTRONICS=y
+CONFIG_HID_PLAYSTATION=y
+CONFIG_PLAYSTATION_FF=y
 CONFIG_HID_SONY=y
+CONFIG_SONY_FF=y
 CONFIG_HID_QVR=y
 CONFIG_USB_HIDDEV=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
@@ -692,7 +698,6 @@ CONFIG_ECRYPT_FS_MESSAGING=y
 CONFIG_SDCARD_FS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
 CONFIG_SECURITY=y
 CONFIG_HARDENED_USERCOPY=y
 CONFIG_FORTIFY_SOURCE=y

arch/arm64/configs/vendor/kona_defconfig

@@ -64,6 +64,8 @@ CONFIG_ARM64_SW_TTBR0_PAN=y
 CONFIG_ARM64_LSE_ATOMICS=y
 # CONFIG_ARM64_VHE is not set
 CONFIG_RANDOMIZE_BASE=y
+CONFIG_CMDLINE="cgroup_disable=pressure"
+CONFIG_CMDLINE_EXTEND=y
 CONFIG_BUILD_ARM64_UNCOMPRESSED_KERNEL=y
 CONFIG_KRYO_PMU_WORKAROUND=y
 CONFIG_COMPAT=y
@@ -331,6 +333,7 @@ CONFIG_BONDING=y
 CONFIG_DUMMY=y
 CONFIG_TUN=y
 CONFIG_VETH=y
+CONFIG_AQFWD=y
 CONFIG_RMNET=y
 CONFIG_PPP=y
 CONFIG_PPP_BSDCOMP=y
@@ -367,6 +370,7 @@ CONFIG_TABLET_USB_HANWANG=y
 CONFIG_TABLET_USB_KBTAB=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_FTS=y
+CONFIG_TOUCHSCREEN_NT36XXX=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_QPNP_POWER_ON=y
 CONFIG_INPUT_QTI_HAPTICS=y
@@ -478,7 +482,10 @@ CONFIG_HID_MICROSOFT=y
 CONFIG_HID_MULTITOUCH=y
 CONFIG_HID_NINTENDO=y
 CONFIG_HID_PLANTRONICS=y
+CONFIG_HID_PLAYSTATION=y
+CONFIG_PLAYSTATION_FF=y
 CONFIG_HID_SONY=y
+CONFIG_SONY_FF=y
 CONFIG_HID_QVR=y
 CONFIG_USB_HIDDEV=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
@@ -729,7 +736,6 @@ CONFIG_SDCARD_FS=y
 # CONFIG_NETWORK_FILESYSTEMS is not set
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
 CONFIG_SECURITY=y
 CONFIG_HARDENED_USERCOPY=y
 CONFIG_HARDENED_USERCOPY_PAGESPAN=y

arch/arm64/configs/vendor/lito-perf_defconfig

@@ -61,6 +61,8 @@ CONFIG_SETEND_EMULATION=y
 CONFIG_ARM64_SW_TTBR0_PAN=y
 # CONFIG_ARM64_VHE is not set
 CONFIG_RANDOMIZE_BASE=y
+CONFIG_CMDLINE="cgroup_disable=pressure"
+CONFIG_CMDLINE_EXTEND=y
 # CONFIG_EFI is not set
 CONFIG_BUILD_ARM64_UNCOMPRESSED_KERNEL=y
 CONFIG_COMPAT=y
@@ -257,6 +259,7 @@ CONFIG_NET_ACT_MIRRED=y
 CONFIG_NET_ACT_SKBEDIT=y
 CONFIG_DNS_RESOLVER=y
 CONFIG_QRTR=y
+CONFIG_QRTR_WAKEUP_MS=500
 CONFIG_QRTR_SMD=y
 CONFIG_QRTR_MHI=y
 CONFIG_BPF_JIT=y
@@ -669,7 +672,6 @@ CONFIG_SDCARD_FS=y
 # CONFIG_NETWORK_FILESYSTEMS is not set
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
 CONFIG_SECURITY=y
 CONFIG_HARDENED_USERCOPY=y
 CONFIG_HARDENED_USERCOPY_PAGESPAN=y

arch/arm64/configs/vendor/lito_defconfig

@@ -62,6 +62,8 @@ CONFIG_SETEND_EMULATION=y
 CONFIG_ARM64_SW_TTBR0_PAN=y
 # CONFIG_ARM64_VHE is not set
 CONFIG_RANDOMIZE_BASE=y
+CONFIG_CMDLINE="cgroup_disable=pressure"
+CONFIG_CMDLINE_EXTEND=y
 CONFIG_BUILD_ARM64_UNCOMPRESSED_KERNEL=y
 CONFIG_COMPAT=y
 CONFIG_PM_WAKELOCKS=y
@@ -263,6 +265,7 @@ CONFIG_NET_ACT_MIRRED=y
 CONFIG_NET_ACT_SKBEDIT=y
 CONFIG_DNS_RESOLVER=y
 CONFIG_QRTR=y
+CONFIG_QRTR_WAKEUP_MS=500
 CONFIG_QRTR_SMD=y
 CONFIG_QRTR_MHI=y
 CONFIG_BPF_JIT=y
@@ -691,7 +694,6 @@ CONFIG_SDCARD_FS=y
 # CONFIG_NETWORK_FILESYSTEMS is not set
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
 CONFIG_SECURITY=y
 CONFIG_HARDENED_USERCOPY=y
 CONFIG_HARDENED_USERCOPY_PAGESPAN=y

arch/arm64/configs/vendor/msm8937-perf_defconfig

@@ -0,0 +1,667 @@
+CONFIG_LOCALVERSION="-perf"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_AUDIT=y
+# CONFIG_AUDITSYSCALL is not set
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_SCHED_WALT=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_PSI=y
+CONFIG_RCU_EXPERT=y
+CONFIG_RCU_FAST_NO_HZ=y
+CONFIG_RCU_NOCB_CPU=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKHEADERS=y
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=17
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_BPF=y
+CONFIG_SCHED_CORE_CTL=y
+CONFIG_NAMESPACES=y
+# CONFIG_PID_NS is not set
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_SCHED_TUNE=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+# CONFIG_FHANDLE is not set
+CONFIG_KALLSYMS_ALL=y
+CONFIG_BPF_SYSCALL=y
+CONFIG_BPF_JIT_ALWAYS_ON=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_ARCH_QCOM=y
+CONFIG_ARCH_QM215=y
+CONFIG_ARCH_MSM8937=y
+CONFIG_ARCH_SDM429=y
+CONFIG_ARCH_SDM439=y
+# CONFIG_ARM64_ERRATUM_1024718 is not set
+CONFIG_SCHED_MC=y
+CONFIG_NR_CPUS=8
+CONFIG_HZ_100=y
+CONFIG_SECCOMP=y
+CONFIG_ARMV8_DEPRECATED=y
+CONFIG_SWP_EMULATION=y
+CONFIG_CP15_BARRIER_EMULATION=y
+CONFIG_SETEND_EMULATION=y
+CONFIG_ARM64_SW_TTBR0_PAN=y
+# CONFIG_ARM64_VHE is not set
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_CMDLINE="cgroup_disable=pressure"
+CONFIG_CMDLINE_EXTEND=y
+CONFIG_COMPAT=y
+CONFIG_PM_WAKELOCKS=y
+CONFIG_PM_WAKELOCKS_LIMIT=0
+# CONFIG_PM_WAKELOCKS_GC is not set
+CONFIG_ENERGY_MODEL=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TIMES=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_BOOST=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_MSM=y
+CONFIG_MSM_TZ_LOG=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=16
+CONFIG_PANIC_ON_REFCOUNT_ERROR=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SIG=y
+CONFIG_MODULE_SIG_FORCE=y
+CONFIG_MODULE_SIG_SHA512=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_BLK_DEV_ZONED=y
+CONFIG_BLK_INLINE_ENCRYPTION=y
+CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_BFQ=y
+CONFIG_BFQ_GROUP_IOSCHED=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_CMA=y
+CONFIG_ZSMALLOC=y
+CONFIG_HAVE_USERSPACE_LOW_MEMORY_KILLER=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_XFRM_INTERFACE=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_NET_IPGRE_DEMUX=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_UDP_DIAG=y
+CONFIG_INET_DIAG_DESTROY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_IPV6_VTI=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_LOG=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_TEE=y
+CONFIG_NETFILTER_XT_TARGET_TPROXY=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_SECMARK=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_BPF=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+# CONFIG_NETFILTER_XT_MATCH_L2TP is not set
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+CONFIG_NETFILTER_XT_MATCH_SOCKET=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_RPFILTER=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_SECURITY=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_RPFILTER=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_BRIDGE_NF_EBTABLES=y
+CONFIG_BRIDGE_EBT_BROUTE=y
+CONFIG_IP_SCTP=y
+CONFIG_L2TP=y
+CONFIG_L2TP_V3=y
+CONFIG_L2TP_IP=y
+CONFIG_L2TP_ETH=y
+CONFIG_BRIDGE=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_INGRESS=y
+CONFIG_NET_CLS_FW=y
+CONFIG_NET_CLS_U32=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_FLOW=y
+CONFIG_NET_CLS_BPF=y
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_CMP=y
+CONFIG_NET_EMATCH_NBYTE=y
+CONFIG_NET_EMATCH_U32=y
+CONFIG_NET_EMATCH_META=y
+CONFIG_NET_EMATCH_TEXT=y
+CONFIG_NET_CLS_ACT=y
+CONFIG_QRTR=y
+CONFIG_QRTR_SMD=y
+CONFIG_BPF_JIT=y
+CONFIG_BT=y
+# CONFIG_BT_BREDR is not set
+# CONFIG_BT_LE is not set
+CONFIG_MSM_BT_POWER=y
+CONFIG_BTFM_SLIM_WCN3990=y
+CONFIG_CFG80211=y
+CONFIG_CFG80211_INTERNAL_REGDB=y
+# CONFIG_CFG80211_CRDA_SUPPORT is not set
+CONFIG_RFKILL=y
+CONFIG_NFC_NQ=y
+CONFIG_FW_LOADER_USER_HELPER=y
+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
+# CONFIG_FW_CACHE is not set
+CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y
+CONFIG_DMA_CMA=y
+CONFIG_ZRAM=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=16
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_HDCP_QSEECOM=y
+CONFIG_QSEECOM=y
+CONFIG_UID_SYS_STATS=y
+CONFIG_FPR_FPC=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_UFSHCD=y
+CONFIG_SCSI_UFSHCD_PLATFORM=y
+CONFIG_SCSI_UFS_QCOM=y
+CONFIG_SCSI_UFS_CRYPTO=y
+CONFIG_SCSI_UFS_CRYPTO_QTI=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=y
+CONFIG_DM_DEFAULT_KEY=y
+CONFIG_DM_SNAPSHOT=y
+CONFIG_DM_UEVENT=y
+CONFIG_DM_VERITY=y
+CONFIG_DM_VERITY_FEC=y
+CONFIG_DM_ANDROID_VERITY=y
+CONFIG_DM_BOW=y
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+CONFIG_TUN=y
+CONFIG_VETH=y
+# CONFIG_NET_VENDOR_AMAZON is not set
+CONFIG_MSM_RMNET_BAM=y
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+CONFIG_RMNET=y
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+CONFIG_PPP=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=y
+CONFIG_PPTP=y
+CONFIG_PPPOL2TP=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_RTL8152=y
+CONFIG_USB_USBNET=y
+# CONFIG_WLAN_VENDOR_ADMTEK is not set
+# CONFIG_WLAN_VENDOR_ATH is not set
+# CONFIG_WLAN_VENDOR_ATMEL is not set
+# CONFIG_WLAN_VENDOR_BROADCOM is not set
+# CONFIG_WLAN_VENDOR_CISCO is not set
+# CONFIG_WLAN_VENDOR_INTEL is not set
+# CONFIG_WLAN_VENDOR_INTERSIL is not set
+# CONFIG_WLAN_VENDOR_MARVELL is not set
+# CONFIG_WLAN_VENDOR_MEDIATEK is not set
+# CONFIG_WLAN_VENDOR_RALINK is not set
+# CONFIG_WLAN_VENDOR_REALTEK is not set
+# CONFIG_WLAN_VENDOR_RSI is not set
+# CONFIG_WLAN_VENDOR_ST is not set
+# CONFIG_WLAN_VENDOR_TI is not set
+# CONFIG_WLAN_VENDOR_ZYDAS is not set
+CONFIG_WCNSS_MEM_PRE_ALLOC=y
+CONFIG_CLD_LL_CORE=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_JOYSTICK_XPAD=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_HBTP_INPUT=y
+CONFIG_INPUT_QPNP_POWER_ON=y
+CONFIG_INPUT_UINPUT=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVMEM is not set
+CONFIG_SERIAL_MSM_HS=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MSM_LEGACY=y
+CONFIG_MSM_SMD_PKT=y
+CONFIG_DIAG_CHAR=y
+CONFIG_MSM_ADSPRPC=y
+CONFIG_MSM_RDBG=m
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MSM_V2=y
+CONFIG_SPI=y
+CONFIG_SPI_QUP=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SPMI=y
+CONFIG_PINCTRL_MSM8937=y
+CONFIG_PINCTRL_MSM8917=y
+CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_RESET_QCOM=y
+CONFIG_QPNP_SMB5=y
+CONFIG_QPNP_VM_BMS=y
+CONFIG_QPNP_LINEAR_CHARGER=y
+CONFIG_SMB1351_USB_CHARGER=y
+CONFIG_SMB1360_CHARGER_FG=y
+CONFIG_SMB1355_SLAVE_CHARGER=y
+CONFIG_QPNP_QG=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_GOV_LOW_LIMITS=y
+CONFIG_CPU_THERMAL=y
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_QCOM_SPMI_TEMP_ALARM=y
+CONFIG_THERMAL_QPNP_ADC_TM=y
+CONFIG_THERMAL_TSENS=y
+CONFIG_QTI_ADC_TM=y
+CONFIG_QTI_VIRTUAL_SENSOR=y
+CONFIG_QTI_BCL_PMIC5=y
+CONFIG_QTI_BCL_SOC_DRIVER=y
+CONFIG_QTI_QMI_COOLING_DEVICE=y
+CONFIG_REGULATOR_COOLING_DEVICE=y
+CONFIG_MFD_I2C_PMIC=y
+CONFIG_MFD_SPMI_PMIC=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_QPNP_LABIBB=y
+CONFIG_REGULATOR_QPNP_LCDB=y
+CONFIG_REGULATOR_MEM_ACC=y
+CONFIG_REGULATOR_CPR=y
+CONFIG_REGULATOR_RPM_SMD=y
+CONFIG_REGULATOR_SPM=y
+CONFIG_REGULATOR_STUB=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_MSM_VIDC_3X_GOVERNORS=y
+CONFIG_MSM_VIDC_3X_V4L2=y
+CONFIG_MSM_CAMERA=y
+CONFIG_MSMB_CAMERA=y
+CONFIG_MSM_CAMERA_SENSOR=y
+CONFIG_MSM_CPP=y
+CONFIG_MSM_CCI=y
+CONFIG_MSM_CSI20_HEADER=y
+CONFIG_MSM_CSI22_HEADER=y
+CONFIG_MSM_CSI30_HEADER=y
+CONFIG_MSM_CSI31_HEADER=y
+CONFIG_MSM_CSIPHY=y
+CONFIG_MSM_CSID=y
+CONFIG_MSM_EEPROM=y
+CONFIG_MSM_ISPIF_V2=y
+CONFIG_IMX134=y
+CONFIG_IMX132=y
+CONFIG_OV9724=y
+CONFIG_OV5648=y
+CONFIG_GC0339=y
+CONFIG_OV8825=y
+CONFIG_OV8865=y
+CONFIG_s5k4e1=y
+CONFIG_OV12830=y
+CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y
+CONFIG_MSMB_JPEG=y
+CONFIG_MSM_FD=y
+CONFIG_RADIO_IRIS=y
+CONFIG_RADIO_IRIS_TRANSPORT=y
+CONFIG_FB=y
+CONFIG_FB_MSM=y
+CONFIG_FB_MSM_MDSS=y
+CONFIG_FB_MSM_MDSS_WRITEBACK=y
+CONFIG_FB_MSM_MDSS_DSI_CTRL_STATUS=y
+CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_UHID=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_ELECOM=y
+CONFIG_HID_MAGICMOUSE=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MULTITOUCH=y
+CONFIG_HID_NINTENDO=y
+CONFIG_HID_SONY=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_MON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_EHCI_MSM=y
+CONFIG_USB_ACM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_ISD200=y
+CONFIG_USB_STORAGE_USBAT=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_USB_STORAGE_ALAUDA=y
+CONFIG_USB_STORAGE_ONETOUCH=y
+CONFIG_USB_STORAGE_KARMA=y
+CONFIG_USB_STORAGE_CYPRESS_ATACB=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_EHSET_TEST_FIXTURE=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_USB_CI13XXX_MSM=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_UEVENT=y
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_QCRNDIS=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_RMNET_BAM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_ACC=y
+CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y
+CONFIG_USB_CONFIGFS_F_MIDI=y
+CONFIG_USB_CONFIGFS_F_HID=y
+CONFIG_USB_CONFIGFS_F_DIAG=y
+CONFIG_USB_CONFIGFS_F_CDEV=y
+CONFIG_USB_CONFIGFS_F_CCID=y
+CONFIG_USB_CONFIGFS_F_QDSS=y
+CONFIG_USB_CONFIGFS_F_MTP=y
+CONFIG_USB_CONFIGFS_F_PTP=y
+CONFIG_TYPEC=y
+CONFIG_MMC=y
+# CONFIG_PWRSEQ_EMMC is not set
+# CONFIG_PWRSEQ_SIMPLE is not set
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_BLOCK_DEFERRED_RESUME=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_MSM=y
+CONFIG_MMC_CQHCI_CRYPTO=y
+CONFIG_MMC_CQHCI_CRYPTO_QTI=y
+CONFIG_LEDS_QTI_TRI_LED=y
+CONFIG_LEDS_QPNP_FLASH_V2=y
+CONFIG_LEDS_QPNP_VIBRATOR_LDO=y
+CONFIG_LEDS_QPNP_VIBRATOR=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_EDAC=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PM8XXX=y
+CONFIG_DMADEVICES=y
+CONFIG_QCOM_SPS_DMA=y
+CONFIG_UIO=y
+CONFIG_UIO_MSM_SHAREDMEM=y
+CONFIG_STAGING=y
+CONFIG_ASHMEM=y
+CONFIG_ION=y
+CONFIG_ION_POOL_AUTO_REFILL=y
+CONFIG_MSM_EXT_DISPLAY=y
+CONFIG_QPNP_REVID=y
+CONFIG_SPS=y
+CONFIG_SPS_SUPPORT_NDP_BAM=y
+CONFIG_IPA=y
+CONFIG_RMNET_IPA=y
+CONFIG_RNDIS_IPA=y
+CONFIG_USB_BAM=y
+CONFIG_MDSS_PLL=y
+CONFIG_QCOM_CLK_SMD_RPM=y
+CONFIG_SDM_GCC_429W=y
+CONFIG_SDM_DEBUGCC_429W=y
+CONFIG_CLOCK_CPU_SDM=y
+CONFIG_SDM_DEBUGCC_439=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_QCOM=y
+CONFIG_MAILBOX=y
+CONFIG_ARM_SMMU=y
+CONFIG_QCOM_LAZY_MAPPING=y
+CONFIG_RPMSG_CHAR=y
+CONFIG_RPMSG_QCOM_GLINK_RPM=y
+CONFIG_RPMSG_QCOM_GLINK_SMEM=y
+CONFIG_RPMSG_QCOM_SMD=y
+CONFIG_MSM_RPM_SMD=y
+CONFIG_QCOM_RUN_QUEUE_STATS=y
+CONFIG_QPNP_PBS=y
+CONFIG_QCOM_QMI_HELPERS=y
+CONFIG_QCOM_SMEM=y
+CONFIG_QCOM_SMD_RPM=y
+CONFIG_MSM_SPM=y
+CONFIG_MSM_L2_SPM=y
+CONFIG_QCOM_EARLY_RANDOM=y
+CONFIG_QCOM_MEMORY_DUMP_V2=y
+CONFIG_QCOM_SMP2P=y
+CONFIG_QCOM_SMSM=y
+CONFIG_MSM_PIL_MSS_QDSP6V5=y
+CONFIG_QCOM_SECURE_BUFFER=y
+CONFIG_MSM_TZ_SMMU=y
+CONFIG_MSM_SUBSYSTEM_RESTART=y
+CONFIG_MSM_PIL=y
+CONFIG_MSM_SYSMON_QMI_COMM=y
+CONFIG_MSM_PIL_SSR_GENERIC=y
+CONFIG_MSM_BOOT_STATS=y
+CONFIG_QCOM_WATCHDOG_V2=y
+CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
+CONFIG_QCOM_BUS_SCALING=y
+CONFIG_QCOM_GLINK=y
+CONFIG_MSM_EVENT_TIMER=y
+CONFIG_MSM_PM=y
+CONFIG_QCOM_DCC=y
+CONFIG_QTI_RPM_STATS_LOG=y
+CONFIG_QTEE_SHM_BRIDGE=y
+CONFIG_MEM_SHARE_QMI_SERVICE=y
+CONFIG_MSM_PERFORMANCE=y
+CONFIG_QTI_CRYPTO_COMMON=y
+CONFIG_QTI_CRYPTO_TZ=y
+CONFIG_MSM_BAM_DMUX=y
+CONFIG_WCNSS_CORE=y
+CONFIG_WCNSS_CORE_PRONTO=y
+CONFIG_WCNSS_REGISTER_DUMP_ON_BITE=y
+CONFIG_QCOM_BIMC_BWMON=y
+CONFIG_ARM_MEMLAT_MON=y
+CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y
+CONFIG_DEVFREQ_GOV_MEMLAT=y
+CONFIG_DEVFREQ_SIMPLE_DEV=y
+CONFIG_QCOM_DEVFREQ_DEVBW=y
+CONFIG_IIO=y
+CONFIG_QCOM_SPMI_ADC5=y
+CONFIG_QCOM_SPMI_VADC=y
+CONFIG_PWM=y
+CONFIG_PWM_QTI_LPG=y
+CONFIG_ARM_GIC_V3_ACL=y
+CONFIG_QCOM_MPM=y
+CONFIG_RAS=y
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_BINDERFS=y
+CONFIG_QCOM_QFPROM=y
+CONFIG_NVMEM_SPMI_SDAM=y
+CONFIG_SLIMBUS_MSM_NGD=y
+CONFIG_SENSORS_SSC=y
+CONFIG_QCOM_KGSL=y
+CONFIG_LEGACY_ENERGY_MODEL_DT=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXT4_ENCRYPTION=y
+CONFIG_F2FS_FS=y
+CONFIG_F2FS_FS_SECURITY=y
+CONFIG_F2FS_FS_ENCRYPTION=y
+CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
+CONFIG_FS_VERITY=y
+CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+CONFIG_QFMT_V2=y
+CONFIG_FUSE_FS=y
+CONFIG_OVERLAY_FS=y
+CONFIG_INCREMENTAL_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_SDCARD_FS=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_SECURITY=y
+CONFIG_HARDENED_USERCOPY=y
+CONFIG_STATIC_USERMODEHELPER=y
+CONFIG_STATIC_USERMODEHELPER_PATH=""
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SMACK=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_XCBC=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y
+CONFIG_CRYPTO_DEV_QCRYPTO=y
+CONFIG_CRYPTO_DEV_QCEDEV=y
+CONFIG_CRYPTO_DEV_QCOM_ICE=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_PANIC_TIMEOUT=5
+CONFIG_SCHEDSTATS=y
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_IPC_LOGGING=y
+CONFIG_BUG_ON_DATA_CORRUPTION=y
+CONFIG_DEBUG_ALIGN_RODATA=y
+CONFIG_CORESIGHT=y
+CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
+CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
+CONFIG_CORESIGHT_STM=y
+CONFIG_CORESIGHT_TPDA=y
+CONFIG_CORESIGHT_TPDM=y
+CONFIG_CORESIGHT_HWEVENT=y
+CONFIG_CORESIGHT_DUMMY=y
+CONFIG_CORESIGHT_REMOTE_ETM=y
+CONFIG_CORESIGHT_TGU=y

arch/arm64/configs/vendor/msm8937_defconfig

@@ -0,0 +1,736 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_AUDIT=y
+# CONFIG_AUDITSYSCALL is not set
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_SCHED_WALT=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_PSI=y
+CONFIG_RCU_EXPERT=y
+CONFIG_RCU_FAST_NO_HZ=y
+CONFIG_RCU_NOCB_CPU=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKHEADERS=y
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=17
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_BPF=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_SCHED_CORE_CTL=y
+CONFIG_NAMESPACES=y
+# CONFIG_PID_NS is not set
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_SCHED_TUNE=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+# CONFIG_FHANDLE is not set
+CONFIG_KALLSYMS_ALL=y
+CONFIG_BPF_SYSCALL=y
+CONFIG_BPF_JIT_ALWAYS_ON=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_ARCH_QCOM=y
+CONFIG_ARCH_QM215=y
+CONFIG_ARCH_MSM8937=y
+CONFIG_ARCH_SDM429=y
+CONFIG_ARCH_SDM439=y
+# CONFIG_ARM64_ERRATUM_1024718 is not set
+CONFIG_SCHED_MC=y
+CONFIG_NR_CPUS=8
+CONFIG_HZ_100=y
+CONFIG_SECCOMP=y
+CONFIG_ARMV8_DEPRECATED=y
+CONFIG_SWP_EMULATION=y
+CONFIG_CP15_BARRIER_EMULATION=y
+CONFIG_SETEND_EMULATION=y
+CONFIG_ARM64_SW_TTBR0_PAN=y
+# CONFIG_ARM64_VHE is not set
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_CMDLINE="cgroup_disable=pressure"
+CONFIG_CMDLINE_EXTEND=y
+CONFIG_COMPAT=y
+CONFIG_PM_WAKELOCKS=y
+CONFIG_PM_WAKELOCKS_LIMIT=0
+# CONFIG_PM_WAKELOCKS_GC is not set
+CONFIG_PM_DEBUG=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TIMES=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_BOOST=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_MSM=y
+CONFIG_MSM_TZ_LOG=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=16
+CONFIG_PANIC_ON_REFCOUNT_ERROR=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SIG=y
+CONFIG_MODULE_SIG_FORCE=y
+CONFIG_MODULE_SIG_SHA512=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_BLK_DEV_ZONED=y
+CONFIG_BLK_INLINE_ENCRYPTION=y
+CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_BFQ=y
+CONFIG_BFQ_GROUP_IOSCHED=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_CLEANCACHE=y
+CONFIG_CMA=y
+CONFIG_CMA_DEBUGFS=y
+CONFIG_ZSMALLOC=y
+CONFIG_HAVE_USERSPACE_LOW_MEMORY_KILLER=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_XFRM_INTERFACE=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_NET_IPGRE_DEMUX=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_UDP_DIAG=y
+CONFIG_INET_DIAG_DESTROY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_IPV6_VTI=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_LOG=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_TEE=y
+CONFIG_NETFILTER_XT_TARGET_TPROXY=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_SECMARK=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_BPF=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+# CONFIG_NETFILTER_XT_MATCH_L2TP is not set
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+CONFIG_NETFILTER_XT_MATCH_SOCKET=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_RPFILTER=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_SECURITY=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_RPFILTER=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_BRIDGE_NF_EBTABLES=y
+CONFIG_BRIDGE_EBT_BROUTE=y
+CONFIG_IP_SCTP=y
+CONFIG_L2TP=y
+CONFIG_L2TP_DEBUGFS=y
+CONFIG_L2TP_V3=y
+CONFIG_L2TP_IP=y
+CONFIG_L2TP_ETH=y
+CONFIG_BRIDGE=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_INGRESS=y
+CONFIG_NET_CLS_FW=y
+CONFIG_NET_CLS_U32=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_FLOW=y
+CONFIG_NET_CLS_BPF=y
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_CMP=y
+CONFIG_NET_EMATCH_NBYTE=y
+CONFIG_NET_EMATCH_U32=y
+CONFIG_NET_EMATCH_META=y
+CONFIG_NET_EMATCH_TEXT=y
+CONFIG_NET_CLS_ACT=y
+CONFIG_DNS_RESOLVER=y
+CONFIG_QRTR=y
+CONFIG_QRTR_SMD=y
+CONFIG_BPF_JIT=y
+CONFIG_BT=y
+# CONFIG_BT_BREDR is not set
+# CONFIG_BT_LE is not set
+CONFIG_MSM_BT_POWER=y
+CONFIG_BTFM_SLIM_WCN3990=y
+CONFIG_CFG80211=y
+CONFIG_CFG80211_INTERNAL_REGDB=y
+# CONFIG_CFG80211_CRDA_SUPPORT is not set
+CONFIG_RFKILL=y
+CONFIG_NFC_NQ=y
+CONFIG_FW_LOADER_USER_HELPER=y
+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
+# CONFIG_FW_CACHE is not set
+CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y
+CONFIG_DMA_CMA=y
+CONFIG_ZRAM=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=16
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_HDCP_QSEECOM=y
+CONFIG_QSEECOM=y
+CONFIG_UID_SYS_STATS=y
+CONFIG_FPR_FPC=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_UFSHCD=y
+CONFIG_SCSI_UFSHCD_PLATFORM=y
+CONFIG_SCSI_UFS_QCOM=y
+CONFIG_SCSI_UFSHCD_CMD_LOGGING=y
+CONFIG_SCSI_UFS_CRYPTO=y
+CONFIG_SCSI_UFS_CRYPTO_QTI=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=y
+CONFIG_DM_DEFAULT_KEY=y
+CONFIG_DM_SNAPSHOT=y
+CONFIG_DM_UEVENT=y
+CONFIG_DM_VERITY=y
+CONFIG_DM_VERITY_FEC=y
+CONFIG_DM_ANDROID_VERITY=y
+CONFIG_DM_BOW=y
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+CONFIG_TUN=y
+CONFIG_VETH=y
+# CONFIG_NET_VENDOR_AMAZON is not set
+CONFIG_MSM_RMNET_BAM=y
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+CONFIG_RMNET=y
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+CONFIG_PPP=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=y
+CONFIG_PPTP=y
+CONFIG_PPPOL2TP=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_SYNC_TTY=y
+CONFIG_USB_RTL8152=y
+CONFIG_USB_USBNET=y
+# CONFIG_WLAN_VENDOR_ADMTEK is not set
+# CONFIG_WLAN_VENDOR_ATH is not set
+# CONFIG_WLAN_VENDOR_ATMEL is not set
+# CONFIG_WLAN_VENDOR_BROADCOM is not set
+# CONFIG_WLAN_VENDOR_CISCO is not set
+# CONFIG_WLAN_VENDOR_INTEL is not set
+# CONFIG_WLAN_VENDOR_INTERSIL is not set
+# CONFIG_WLAN_VENDOR_MARVELL is not set
+# CONFIG_WLAN_VENDOR_MEDIATEK is not set
+# CONFIG_WLAN_VENDOR_RALINK is not set
+# CONFIG_WLAN_VENDOR_REALTEK is not set
+# CONFIG_WLAN_VENDOR_RSI is not set
+# CONFIG_WLAN_VENDOR_ST is not set
+# CONFIG_WLAN_VENDOR_TI is not set
+# CONFIG_WLAN_VENDOR_ZYDAS is not set
+CONFIG_WCNSS_MEM_PRE_ALLOC=y
+CONFIG_CLD_LL_CORE=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_JOYSTICK_XPAD=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_HBTP_INPUT=y
+CONFIG_INPUT_QPNP_POWER_ON=y
+CONFIG_INPUT_UINPUT=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVMEM is not set
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
+CONFIG_SERIAL_MSM_HS=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MSM_LEGACY=y
+CONFIG_MSM_SMD_PKT=y
+CONFIG_DIAG_CHAR=y
+CONFIG_MSM_ADSPRPC=y
+CONFIG_MSM_RDBG=m
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MSM_V2=y
+CONFIG_SPI=y
+CONFIG_SPI_QUP=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SPMI=y
+CONFIG_PINCTRL_MSM8937=y
+CONFIG_PINCTRL_MSM8917=y
+CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_RESET_QCOM=y
+CONFIG_QPNP_SMB5=y
+CONFIG_QPNP_VM_BMS=y
+CONFIG_QPNP_LINEAR_CHARGER=y
+CONFIG_SMB1351_USB_CHARGER=y
+CONFIG_SMB1360_CHARGER_FG=y
+CONFIG_SMB1355_SLAVE_CHARGER=y
+CONFIG_QPNP_QG=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_THERMAL_GOV_LOW_LIMITS=y
+CONFIG_CPU_THERMAL=y
+CONFIG_DEVFREQ_THERMAL=y
+CONFIG_QCOM_SPMI_TEMP_ALARM=y
+CONFIG_THERMAL_QPNP_ADC_TM=y
+CONFIG_THERMAL_TSENS=y
+CONFIG_QTI_ADC_TM=y
+CONFIG_QTI_VIRTUAL_SENSOR=y
+CONFIG_QTI_BCL_PMIC5=y
+CONFIG_QTI_BCL_SOC_DRIVER=y
+CONFIG_QTI_QMI_COOLING_DEVICE=y
+CONFIG_REGULATOR_COOLING_DEVICE=y
+CONFIG_MFD_I2C_PMIC=y
+CONFIG_MFD_SPMI_PMIC=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_QPNP_LABIBB=y
+CONFIG_REGULATOR_QPNP_LCDB=y
+CONFIG_REGULATOR_MEM_ACC=y
+CONFIG_REGULATOR_CPR=y
+CONFIG_REGULATOR_RPM_SMD=y
+CONFIG_REGULATOR_SPM=y
+CONFIG_REGULATOR_STUB=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_MSM_VIDC_3X_GOVERNORS=y
+CONFIG_MSM_VIDC_3X_V4L2=y
+CONFIG_MSM_CAMERA=y
+CONFIG_MSM_CAMERA_DEBUG=y
+CONFIG_MSMB_CAMERA=y
+CONFIG_MSMB_CAMERA_DEBUG=y
+CONFIG_MSM_CAMERA_SENSOR=y
+CONFIG_MSM_CPP=y
+CONFIG_MSM_CCI=y
+CONFIG_MSM_CSI20_HEADER=y
+CONFIG_MSM_CSI22_HEADER=y
+CONFIG_MSM_CSI30_HEADER=y
+CONFIG_MSM_CSI31_HEADER=y
+CONFIG_MSM_CSIPHY=y
+CONFIG_MSM_CSID=y
+CONFIG_MSM_EEPROM=y
+CONFIG_MSM_ISPIF_V2=y
+CONFIG_IMX134=y
+CONFIG_IMX132=y
+CONFIG_OV9724=y
+CONFIG_OV5648=y
+CONFIG_GC0339=y
+CONFIG_OV8825=y
+CONFIG_OV8865=y
+CONFIG_s5k4e1=y
+CONFIG_OV12830=y
+CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y
+CONFIG_MSMB_JPEG=y
+CONFIG_MSM_FD=y
+CONFIG_RADIO_IRIS=y
+CONFIG_RADIO_IRIS_TRANSPORT=y
+CONFIG_FB=y
+CONFIG_FB_VIRTUAL=y
+CONFIG_FB_MSM=y
+CONFIG_FB_MSM_MDSS=y
+CONFIG_FB_MSM_MDSS_WRITEBACK=y
+CONFIG_FB_MSM_MDSS_DSI_CTRL_STATUS=y
+CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_UHID=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_ELECOM=y
+CONFIG_HID_MAGICMOUSE=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MULTITOUCH=y
+CONFIG_HID_NINTENDO=y
+CONFIG_HID_SONY=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_MON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_EHCI_MSM=y
+CONFIG_USB_ACM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_ISD200=y
+CONFIG_USB_STORAGE_USBAT=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_USB_STORAGE_ALAUDA=y
+CONFIG_USB_STORAGE_ONETOUCH=y
+CONFIG_USB_STORAGE_KARMA=y
+CONFIG_USB_STORAGE_CYPRESS_ATACB=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_EHSET_TEST_FIXTURE=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_USB_CI13XXX_MSM=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_UEVENT=y
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_QCRNDIS=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_RMNET_BAM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_ACC=y
+CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y
+CONFIG_USB_CONFIGFS_F_MIDI=y
+CONFIG_USB_CONFIGFS_F_HID=y
+CONFIG_USB_CONFIGFS_F_DIAG=y
+CONFIG_USB_CONFIGFS_F_CDEV=y
+CONFIG_USB_CONFIGFS_F_CCID=y
+CONFIG_USB_CONFIGFS_F_QDSS=y
+CONFIG_USB_CONFIGFS_F_MTP=y
+CONFIG_USB_CONFIGFS_F_PTP=y
+CONFIG_TYPEC=y
+CONFIG_MMC=y
+# CONFIG_PWRSEQ_EMMC is not set
+# CONFIG_PWRSEQ_SIMPLE is not set
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_BLOCK_DEFERRED_RESUME=y
+CONFIG_MMC_IPC_LOGGING=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_MSM=y
+CONFIG_MMC_CQHCI_CRYPTO=y
+CONFIG_MMC_CQHCI_CRYPTO_QTI=y
+CONFIG_LEDS_QTI_TRI_LED=y
+CONFIG_LEDS_QPNP_FLASH_V2=y
+CONFIG_LEDS_QPNP_VIBRATOR_LDO=y
+CONFIG_LEDS_QPNP_VIBRATOR=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_EDAC=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PM8XXX=y
+CONFIG_DMADEVICES=y
+CONFIG_QCOM_SPS_DMA=y
+CONFIG_UIO=y
+CONFIG_UIO_MSM_SHAREDMEM=y
+CONFIG_STAGING=y
+CONFIG_ASHMEM=y
+CONFIG_ION=y
+CONFIG_ION_POOL_AUTO_REFILL=y
+CONFIG_MSM_EXT_DISPLAY=y
+CONFIG_QPNP_REVID=y
+CONFIG_SPS=y
+CONFIG_SPS_SUPPORT_NDP_BAM=y
+CONFIG_IPA=y
+CONFIG_RMNET_IPA=y
+CONFIG_RNDIS_IPA=y
+CONFIG_USB_BAM=y
+CONFIG_MDSS_PLL=y
+CONFIG_QCOM_CLK_SMD_RPM=y
+CONFIG_SDM_GCC_429W=y
+CONFIG_SDM_DEBUGCC_429W=y
+CONFIG_CLOCK_CPU_SDM=y
+CONFIG_SDM_DEBUGCC_439=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_QCOM=y
+CONFIG_MAILBOX=y
+CONFIG_ARM_SMMU=y
+CONFIG_QCOM_LAZY_MAPPING=y
+CONFIG_IOMMU_DEBUG=y
+CONFIG_IOMMU_TESTS=y
+CONFIG_RPMSG_CHAR=y
+CONFIG_RPMSG_QCOM_GLINK_RPM=y
+CONFIG_RPMSG_QCOM_GLINK_SMEM=y
+CONFIG_RPMSG_QCOM_SMD=y
+CONFIG_MSM_RPM_SMD=y
+CONFIG_QCOM_CPUSS_DUMP=y
+CONFIG_QCOM_RUN_QUEUE_STATS=y
+CONFIG_QPNP_PBS=y
+CONFIG_QCOM_QMI_HELPERS=y
+CONFIG_QCOM_SMEM=y
+CONFIG_QCOM_SMD_RPM=y
+CONFIG_MSM_SPM=y
+CONFIG_MSM_L2_SPM=y
+CONFIG_QCOM_EARLY_RANDOM=y
+CONFIG_QCOM_MEMORY_DUMP_V2=y
+CONFIG_MSM_DEBUG_LAR_UNLOCK=y
+CONFIG_QCOM_SMP2P=y
+CONFIG_QCOM_SMSM=y
+CONFIG_MSM_PIL_MSS_QDSP6V5=y
+CONFIG_QCOM_SECURE_BUFFER=y
+CONFIG_MSM_TZ_SMMU=y
+CONFIG_MSM_SUBSYSTEM_RESTART=y
+CONFIG_MSM_PIL=y
+CONFIG_MSM_SYSMON_QMI_COMM=y
+CONFIG_MSM_PIL_SSR_GENERIC=y
+CONFIG_MSM_BOOT_STATS=y
+CONFIG_MSM_CORE_HANG_DETECT=y
+CONFIG_QCOM_WATCHDOG_V2=y
+CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
+CONFIG_QCOM_BUS_SCALING=y
+CONFIG_QCOM_GLINK=y
+CONFIG_MSM_EVENT_TIMER=y
+CONFIG_MSM_PM=y
+CONFIG_QCOM_DCC=y
+CONFIG_QTI_RPM_STATS_LOG=y
+CONFIG_QTEE_SHM_BRIDGE=y
+CONFIG_MEM_SHARE_QMI_SERVICE=y
+CONFIG_MSM_PERFORMANCE=y
+CONFIG_QTI_CRYPTO_COMMON=y
+CONFIG_QTI_CRYPTO_TZ=y
+CONFIG_MSM_BAM_DMUX=y
+CONFIG_WCNSS_CORE=y
+CONFIG_WCNSS_CORE_PRONTO=y
+CONFIG_WCNSS_REGISTER_DUMP_ON_BITE=y
+CONFIG_QCOM_BIMC_BWMON=y
+CONFIG_ARM_MEMLAT_MON=y
+CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y
+CONFIG_DEVFREQ_GOV_MEMLAT=y
+CONFIG_DEVFREQ_SIMPLE_DEV=y
+CONFIG_QCOM_DEVFREQ_DEVBW=y
+CONFIG_IIO=y
+CONFIG_QCOM_SPMI_ADC5=y
+CONFIG_QCOM_SPMI_VADC=y
+CONFIG_PWM=y
+CONFIG_PWM_QTI_LPG=y
+CONFIG_ARM_GIC_V3_ACL=y
+CONFIG_QCOM_MPM=y
+CONFIG_RAS=y
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_BINDERFS=y
+CONFIG_QCOM_QFPROM=y
+CONFIG_NVMEM_SPMI_SDAM=y
+CONFIG_SLIMBUS_MSM_NGD=y
+CONFIG_SENSORS_SSC=y
+CONFIG_QCOM_KGSL=y
+CONFIG_LEGACY_ENERGY_MODEL_DT=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXT4_ENCRYPTION=y
+CONFIG_F2FS_FS=y
+CONFIG_F2FS_FS_SECURITY=y
+CONFIG_F2FS_CHECK_FS=y
+CONFIG_F2FS_FS_ENCRYPTION=y
+CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
+CONFIG_FS_VERITY=y
+CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+CONFIG_QFMT_V2=y
+CONFIG_FUSE_FS=y
+CONFIG_OVERLAY_FS=y
+CONFIG_INCREMENTAL_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_SDCARD_FS=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_SECURITY=y
+CONFIG_HARDENED_USERCOPY=y
+CONFIG_STATIC_USERMODEHELPER=y
+CONFIG_STATIC_USERMODEHELPER_PATH=""
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SMACK=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_XCBC=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y
+CONFIG_CRYPTO_DEV_QCRYPTO=y
+CONFIG_CRYPTO_DEV_QCEDEV=y
+CONFIG_CRYPTO_DEV_QCOM_ICE=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_CONSOLE_UNHASHED_POINTERS=y
+CONFIG_DEBUG_MODULE_LOAD_INFO=y
+CONFIG_DEBUG_INFO=y
+CONFIG_PAGE_OWNER=y
+CONFIG_PAGE_OWNER_ENABLE_DEFAULT=y
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_PAGEALLOC=y
+CONFIG_SLUB_DEBUG_PANIC_ON=y
+CONFIG_DEBUG_PANIC_ON_OOM=y
+CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y
+CONFIG_PAGE_POISONING=y
+CONFIG_DEBUG_OBJECTS=y
+CONFIG_DEBUG_OBJECTS_FREE=y
+CONFIG_DEBUG_OBJECTS_TIMERS=y
+CONFIG_DEBUG_OBJECTS_WORK=y
+CONFIG_DEBUG_OBJECTS_RCU_HEAD=y
+CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y
+CONFIG_DEBUG_KMEMLEAK=y
+CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=4000
+CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y
+CONFIG_DEBUG_STACK_USAGE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_WQ_WATCHDOG=y
+CONFIG_PANIC_ON_OOPS=y
+CONFIG_PANIC_TIMEOUT=5
+CONFIG_PANIC_ON_SCHED_BUG=y
+CONFIG_PANIC_ON_RT_THROTTLING=y
+CONFIG_SCHEDSTATS=y
+CONFIG_SCHED_STACK_END_CHECK=y
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+CONFIG_LOCK_TORTURE_TEST=m
+CONFIG_DEBUG_SG=y
+CONFIG_DEBUG_NOTIFIERS=y
+CONFIG_DEBUG_CREDENTIALS=y
+CONFIG_FAULT_INJECTION=y
+CONFIG_FAIL_PAGE_ALLOC=y
+CONFIG_FAULT_INJECTION_DEBUG_FS=y
+CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y
+CONFIG_IPC_LOGGING=y
+CONFIG_QCOM_RTB=y
+CONFIG_QCOM_RTB_SEPARATE_CPUS=y
+CONFIG_FUNCTION_TRACER=y
+CONFIG_PREEMPTIRQ_EVENTS=y
+CONFIG_IRQSOFF_TRACER=y
+CONFIG_PREEMPT_TRACER=y
+CONFIG_BLK_DEV_IO_TRACE=y
+CONFIG_LKDTM=y
+CONFIG_ATOMIC64_SELFTEST=m
+CONFIG_MEMTEST=y
+CONFIG_BUG_ON_DATA_CORRUPTION=y
+CONFIG_PANIC_ON_DATA_CORRUPTION=y
+CONFIG_CORESIGHT=y
+CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
+CONFIG_CORESIGHT_SOURCE_ETM4X=y
+CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
+CONFIG_CORESIGHT_STM=y
+CONFIG_CORESIGHT_CTI=y
+CONFIG_CORESIGHT_TPDA=y
+CONFIG_CORESIGHT_TPDM=y
+CONFIG_CORESIGHT_HWEVENT=y
+CONFIG_CORESIGHT_DUMMY=y
+CONFIG_CORESIGHT_REMOTE_ETM=y
+CONFIG_CORESIGHT_TGU=y

arch/arm64/configs/vendor/sdm660-perf_defconfig

@@ -67,6 +67,8 @@ CONFIG_SETEND_EMULATION=y
 CONFIG_ARM64_SW_TTBR0_PAN=y
 # CONFIG_ARM64_VHE is not set
 CONFIG_RANDOMIZE_BASE=y
+CONFIG_CMDLINE="cgroup_disable=pressure"
+CONFIG_CMDLINE_EXTEND=y
 CONFIG_COMPAT=y
 CONFIG_PM_WAKELOCKS=y
 CONFIG_PM_WAKELOCKS_LIMIT=0
@@ -431,6 +433,26 @@ CONFIG_USB_VIDEO_CLASS=y
 CONFIG_V4L_PLATFORM_DRIVERS=y
 CONFIG_MSM_VIDC_3X_GOVERNORS=y
 CONFIG_MSM_VIDC_3X_V4L2=y
+CONFIG_MSM_CAMERA=y
+CONFIG_MSM_CAMERA_DEBUG=y
+CONFIG_MSMB_CAMERA=y
+CONFIG_MSMB_CAMERA_DEBUG=y
+CONFIG_MSM_CAMERA_SENSOR=y
+CONFIG_MSM_CPP=y
+CONFIG_MSM_CCI=y
+CONFIG_MSM_CSI20_HEADER=y
+CONFIG_MSM_CSI22_HEADER=y
+CONFIG_MSM_CSI30_HEADER=y
+CONFIG_MSM_CSI31_HEADER=y
+CONFIG_MSM_CSIPHY=y
+CONFIG_MSM_CSID=y
+CONFIG_MSM_EEPROM=y
+CONFIG_MSM_ISPIF=y
+CONFIG_MSM_DUAL_ISP_SYNC=y
+CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y
+CONFIG_MSMB_JPEG=y
+CONFIG_MSM_FD=y
+CONFIG_MSM_JPEGDMA=y
 CONFIG_DVB_MPQ=m
 CONFIG_DVB_MPQ_DEMUX=m
 CONFIG_SDE_ROTATOR=y
@@ -513,8 +535,6 @@ CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_MSM=y
 CONFIG_MMC_CQHCI_CRYPTO=y
 CONFIG_MMC_CQHCI_CRYPTO_QTI=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_QTI_TRI_LED=y
 CONFIG_LEDS_QPNP_FLASH_V2=y
 CONFIG_RTC_CLASS=y
@@ -670,7 +690,6 @@ CONFIG_ECRYPT_FS_MESSAGING=y
 CONFIG_SDCARD_FS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
 CONFIG_SECURITY=y
 CONFIG_HARDENED_USERCOPY=y
 CONFIG_HARDENED_USERCOPY_PAGESPAN=y
@@ -703,10 +722,13 @@ CONFIG_IPC_LOGGING=y
 CONFIG_DEBUG_ALIGN_RODATA=y
 CONFIG_CORESIGHT=y
 CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
-CONFIG_CORESIGHT_SOURCE_ETM4X=y
+CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
 CONFIG_CORESIGHT_STM=y
 CONFIG_CORESIGHT_CTI=y
+CONFIG_CORESIGHT_CTI_SAVE_DISABLE=y
 CONFIG_CORESIGHT_TPDA=y
 CONFIG_CORESIGHT_TPDM=y
 CONFIG_CORESIGHT_HWEVENT=y
+CONFIG_CORESIGHT_DUMMY=y
 CONFIG_CORESIGHT_REMOTE_ETM=y
+CONFIG_CORESIGHT_TGU=y

arch/arm64/configs/vendor/sdm660_defconfig

@@ -67,6 +67,8 @@ CONFIG_SETEND_EMULATION=y
 CONFIG_ARM64_SW_TTBR0_PAN=y
 # CONFIG_ARM64_VHE is not set
 CONFIG_RANDOMIZE_BASE=y
+CONFIG_CMDLINE="cgroup_disable=pressure"
+CONFIG_CMDLINE_EXTEND=y
 CONFIG_COMPAT=y
 CONFIG_PM_WAKELOCKS=y
 CONFIG_PM_WAKELOCKS_LIMIT=0
@@ -711,7 +713,6 @@ CONFIG_SDCARD_FS=y
 # CONFIG_NETWORK_FILESYSTEMS is not set
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
 CONFIG_SECURITY=y
 CONFIG_HARDENED_USERCOPY=y
 CONFIG_HARDENED_USERCOPY_PAGESPAN=y
@@ -798,9 +799,12 @@ CONFIG_ARM64_STRICT_BREAK_BEFORE_MAKE=y
 CONFIG_CORESIGHT=y
 CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
 CONFIG_CORESIGHT_SOURCE_ETM4X=y
+CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y
 CONFIG_CORESIGHT_STM=y
 CONFIG_CORESIGHT_CTI=y
 CONFIG_CORESIGHT_TPDA=y
 CONFIG_CORESIGHT_TPDM=y
 CONFIG_CORESIGHT_HWEVENT=y
+CONFIG_CORESIGHT_DUMMY=y
 CONFIG_CORESIGHT_REMOTE_ETM=y
+CONFIG_CORESIGHT_TGU=y

arch/x86/configs/gki_defconfig

@@ -418,7 +418,6 @@ CONFIG_NLS_MAC_ROMANIAN=y
 CONFIG_NLS_MAC_TURKISH=y
 CONFIG_NLS_UTF8=y
 CONFIG_UNICODE=y
-CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
 CONFIG_SECURITY=y
 CONFIG_SECURITYFS=y
 CONFIG_SECURITY_NETWORK=y

block/blk-core.c

@@ -1741,8 +1741,12 @@ EXPORT_SYMBOL_GPL(part_round_stats);
 #ifdef CONFIG_PM
 static void blk_pm_put_request(struct request *rq)
 {
-	if (rq->q->dev && !(rq->rq_flags & RQF_PM) && !--rq->q->nr_pending)
+	if (rq->q->dev && !(rq->rq_flags & RQF_PM) &&
-		pm_runtime_mark_last_busy(rq->q->dev);
+	    (rq->rq_flags & RQF_PM_ADDED)) {
+		rq->rq_flags &= ~RQF_PM_ADDED;
+		if (!--rq->q->nr_pending)
+			pm_runtime_mark_last_busy(rq->q->dev);
+	}
 }
 #else
 static inline void blk_pm_put_request(struct request *rq) {}

block/elevator.c

@@ -560,15 +560,22 @@ void elv_bio_merged(struct request_queue *q, struct request *rq,
 #ifdef CONFIG_PM
 static void blk_pm_requeue_request(struct request *rq)
 {
-	if (rq->q->dev && !(rq->rq_flags & RQF_PM))
+	if (rq->q->dev && !(rq->rq_flags & RQF_PM) &&
+	    (rq->rq_flags & (RQF_PM_ADDED | RQF_FLUSH_SEQ))) {
+		rq->rq_flags &= ~RQF_PM_ADDED;
 		rq->q->nr_pending--;
+	}
 }
 
 static void blk_pm_add_request(struct request_queue *q, struct request *rq)
 {
-	if (q->dev && !(rq->rq_flags & RQF_PM) && q->nr_pending++ == 0 &&
+	if (q->dev && !(rq->rq_flags & RQF_PM)) {
-	    (q->rpm_status == RPM_SUSPENDED || q->rpm_status == RPM_SUSPENDING))
+		rq->rq_flags |= RQF_PM_ADDED;
-		pm_request_resume(q->dev);
+		if (q->nr_pending++ == 0 &&
+		    (q->rpm_status == RPM_SUSPENDED ||
+		     q->rpm_status == RPM_SUSPENDING))
+			pm_request_resume(q->dev);
+	}
 }
 #else
 static inline void blk_pm_requeue_request(struct request *rq) {}

drivers/bluetooth/bluetooth-power.c

@@ -448,10 +448,6 @@ static void bt_free_gpios(void)
 {
 	if (bt_power_pdata->bt_gpio_sys_rst > 0)
 		gpio_free(bt_power_pdata->bt_gpio_sys_rst);
-	if (bt_power_pdata->wl_gpio_sys_rst > 0)
-		gpio_free(bt_power_pdata->wl_gpio_sys_rst);
-	if  (bt_power_pdata->bt_gpio_sw_ctrl  >  0)
-		gpio_free(bt_power_pdata->bt_gpio_sw_ctrl);
 	if  (bt_power_pdata->bt_gpio_debug  >  0)
 		gpio_free(bt_power_pdata->bt_gpio_debug);
 }
@@ -1153,7 +1149,9 @@ static long bt_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 			soc_id = chipset_version;
 			if (soc_id == QCA_HSP_SOC_ID_0100 ||
 				soc_id == QCA_HSP_SOC_ID_0110 ||
-				soc_id == QCA_HSP_SOC_ID_0200) {
+				soc_id == QCA_HSP_SOC_ID_0200 ||
+				soc_id == QCA_HSP_SOC_ID_0210 ||
+				soc_id == QCA_HSP_SOC_ID_1211) {
 				ret = bt_disable_asd();
 			}
 		} else {

drivers/bluetooth/btfm_slim.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/init.h>
@@ -442,6 +442,8 @@ int btfm_slim_hw_init(struct btfmslim *btfmslim)
 
 	if (chipset_ver == QCA_HSP_SOC_ID_0100 ||
 		chipset_ver == QCA_HSP_SOC_ID_0110 ||
+		chipset_ver == QCA_HSP_SOC_ID_0210 ||
+		chipset_ver == QCA_HSP_SOC_ID_1211 ||
 		chipset_ver == QCA_HSP_SOC_ID_0200) {
 		BTFMSLIM_INFO("chipset is hastings prime, overwriting EA");
 		slim->e_addr[0] = 0x00;

drivers/bluetooth/btfm_slim_codec.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/init.h>
@@ -13,6 +13,7 @@
 #include <linux/slimbus/slimbus.h>
 #include <linux/ratelimit.h>
 #include <linux/slab.h>
+#include <linux/errno.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
@@ -209,6 +210,11 @@ static int btfm_slim_dai_prepare(struct snd_pcm_substream *substream,
 	/* save the enable channel status */
 	if (ret == 0)
 		bt_soc_enable_status = 1;
+
+	if (ret == -EISCONN) {
+		BTFMSLIM_ERR("channel opened without closing, return success");
+		ret = 0;
+	}
 	return ret;
 }
 

drivers/bluetooth/btfm_slim_slave.h

@@ -98,6 +98,7 @@ enum {
 	QCA_COMANCHE_SOC_ID_0110  = 0x40070110,
 	QCA_COMANCHE_SOC_ID_0120  = 0x40070120,
 	QCA_COMANCHE_SOC_ID_0130  = 0x40070130,
+	QCA_COMANCHE_SOC_ID_4130  = 0x40074130,
 	QCA_COMANCHE_SOC_ID_5120  = 0x40075120,
 	QCA_COMANCHE_SOC_ID_5130  = 0x40075130,
 };
@@ -110,6 +111,8 @@ enum {
 	QCA_HSP_SOC_ID_0100 = 0x400C0100,
 	QCA_HSP_SOC_ID_0110 = 0x400C0110,
 	QCA_HSP_SOC_ID_0200 = 0x400C0200,
+	QCA_HSP_SOC_ID_0210 = 0x400C0210,
+	QCA_HSP_SOC_ID_1211 = 0x400C1211,
 };
 
 /* Function Prototype */

drivers/bus/mhi/core/mhi_init.c

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */
 
 #include <linux/debugfs.h>
 #include <linux/device.h>
@@ -89,9 +89,12 @@ struct mhi_controller *find_mhi_controller_by_name(const char *name)
 
 const char *to_mhi_pm_state_str(enum MHI_PM_STATE state)
 {
-	int index = find_last_bit((unsigned long *)&state, 32);
+	int index;
 
-	if (index >= ARRAY_SIZE(mhi_pm_state_str))
+	if (state)
+		index = __fls(state);
+
+	if (!state || index >= ARRAY_SIZE(mhi_pm_state_str))
 		return "Invalid State";
 
 	return mhi_pm_state_str[index];
@@ -1048,7 +1051,16 @@ void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl,
 	vfree(buf_ring->base);
 
 	buf_ring->base = tre_ring->base = NULL;
+	tre_ring->ctxt_wp = NULL;
 	chan_ctxt->rbase = 0;
+	chan_ctxt->rlen = 0;
+	chan_ctxt->rp = chan_ctxt->wp = chan_ctxt->rbase;
+	tre_ring->rp = tre_ring->wp = tre_ring->base;
+	buf_ring->rp = buf_ring->wp = buf_ring->base;
+
+	/* Update to all cores */
+	smp_wmb();
+
 }
 
 int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl,

drivers/bus/mhi/core/mhi_main.c

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */
 
 #include <linux/debugfs.h>
 #include <linux/device.h>
@@ -558,18 +558,6 @@ int mhi_queue_dma(struct mhi_device *mhi_dev,
 		mhi_tre->dword[0] =
 			MHI_RSCTRE_DATA_DWORD0(buf_ring->wp - buf_ring->base);
 		mhi_tre->dword[1] = MHI_RSCTRE_DATA_DWORD1;
-		/*
-		 * on RSC channel IPA HW has a minimum credit requirement before
-		 * switching to DB mode
-		 */
-		n_free_tre = mhi_get_no_free_descriptors(mhi_dev,
-				DMA_FROM_DEVICE);
-		n_queued_tre = tre_ring->elements - n_free_tre;
-		read_lock_bh(&mhi_chan->lock);
-		if (mhi_chan->db_cfg.db_mode &&
-				n_queued_tre < MHI_RSC_MIN_CREDITS)
-			ring_db = false;
-		read_unlock_bh(&mhi_chan->lock);
 	} else {
 		mhi_tre->ptr = MHI_TRE_DATA_PTR(buf_info->p_addr);
 		mhi_tre->dword[0] = MHI_TRE_DATA_DWORD0(buf_info->len);
@@ -587,12 +575,25 @@ int mhi_queue_dma(struct mhi_device *mhi_dev,
 	if (mhi_chan->dir == DMA_TO_DEVICE)
 		atomic_inc(&mhi_cntrl->pending_pkts);
 
-	if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl)) && ring_db) {
+	read_lock_bh(&mhi_chan->lock);
-		read_lock_bh(&mhi_chan->lock);
+	if (mhi_chan->xfer_type == MHI_XFER_RSC_DMA) {
-		mhi_ring_chan_db(mhi_cntrl, mhi_chan);
+		/*
-		read_unlock_bh(&mhi_chan->lock);
+		 * on RSC channel IPA HW has a minimum credit requirement before
+		 * switching to DB mode
+		 */
+		n_free_tre = mhi_get_no_free_descriptors(mhi_dev,
+				DMA_FROM_DEVICE);
+		n_queued_tre = tre_ring->elements - n_free_tre;
+		if (mhi_chan->db_cfg.db_mode &&
+				n_queued_tre < MHI_RSC_MIN_CREDITS)
+			ring_db = false;
 	}
 
+	if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl)) && ring_db)
+		mhi_ring_chan_db(mhi_cntrl, mhi_chan);
+
+	read_unlock_bh(&mhi_chan->lock);
+
 	read_unlock_bh(&mhi_cntrl->pm_lock);
 
 	return 0;

drivers/bus/mhi/core/mhi_pm.c

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */
 
 #include <linux/debugfs.h>
 #include <linux/delay.h>
@@ -395,7 +395,8 @@ int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl)
 
 		read_lock_irq(&mhi_chan->lock);
 		/* only ring DB if ring is not empty */
-		if (tre_ring->base && tre_ring->wp  != tre_ring->rp)
+		if (tre_ring->base && tre_ring->wp  != tre_ring->rp &&
+		    mhi_chan->ch_state == MHI_CH_STATE_ENABLED)
 			mhi_ring_chan_db(mhi_cntrl, mhi_chan);
 		read_unlock_irq(&mhi_chan->lock);
 	}
@@ -1061,8 +1062,8 @@ void mhi_control_error(struct mhi_controller *mhi_cntrl)
 				sfr_info->buf_addr);
 	}
 
-	/* link is not down if device is in RDDM */
+	/* link is not down if device supports RDDM */
-	transition_state = (mhi_cntrl->ee == MHI_EE_RDDM) ?
+	transition_state = (mhi_cntrl->rddm_supported) ?
 		MHI_PM_DEVICE_ERR_DETECT : MHI_PM_LD_ERR_FATAL_DETECT;
 
 	write_lock_irq(&mhi_cntrl->pm_lock);

drivers/bus/mhi/devices/mhi_netdev.c

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.*/
+/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.*/
 
 #include <linux/module.h>
 #include <linux/kernel.h>
@@ -780,6 +780,7 @@ static void mhi_netdev_push_skb(struct mhi_netdev *mhi_netdev,
 			mhi_result->bytes_xferd, mhi_netdev->mru);
 	skb->dev = mhi_netdev->ndev;
 	skb->protocol = mhi_netdev_ip_type_trans(*(u8 *)mhi_buf->buf);
+	skb_set_mac_header(skb, 0);
 	netif_receive_skb(skb);
 }
 
@@ -815,6 +816,7 @@ static void mhi_netdev_xfer_dl_cb(struct mhi_device *mhi_dev,
 	/* we support chaining */
 	skb = alloc_skb(0, GFP_ATOMIC);
 	if (likely(skb)) {
+		skb_set_mac_header(skb, 0);
 		skb_add_rx_frag(skb, 0, mhi_buf->page, 0,
 				mhi_result->bytes_xferd, mhi_netdev->mru);
 		/* this is first on list */

drivers/char/adsprpc.c

@@ -415,6 +415,8 @@ struct fastrpc_mmap {
 	int uncached;
 	int secure;
 	uintptr_t attr;
+	bool is_filemap;
+	/* flag to indicate map used in process init */
 };
 
 enum fastrpc_perfkeys {
@@ -833,9 +835,10 @@ static int fastrpc_mmap_remove(struct fastrpc_file *fl, uintptr_t va,
 
 	spin_lock(&me->hlock);
 	hlist_for_each_entry_safe(map, n, &me->maps, hn) {
-		if (map->raddr == va &&
+		if (map->refs == 1 && map->raddr == va &&
 			map->raddr + map->len == va + len &&
-			map->refs == 1) {
+			/* Remove map if not used in process initialization*/
+			!map->is_filemap) {
 			match = map;
 			hlist_del_init(&map->hn);
 			break;
@@ -847,9 +850,10 @@ static int fastrpc_mmap_remove(struct fastrpc_file *fl, uintptr_t va,
 		return 0;
 	}
 	hlist_for_each_entry_safe(map, n, &fl->maps, hn) {
-		if (map->raddr == va &&
+		if (map->refs == 1 && map->raddr == va &&
 			map->raddr + map->len == va + len &&
-			map->refs == 1) {
+			/* Remove map if not used in process initialization*/
+			!map->is_filemap) {
 			match = map;
 			hlist_del_init(&map->hn);
 			break;
@@ -985,6 +989,7 @@ static int fastrpc_mmap_create(struct fastrpc_file *fl, int fd,
 	map->fl = fl;
 	map->fd = fd;
 	map->attr = attr;
+	map->is_filemap = false;
 	if (mflags == ADSP_MMAP_HEAP_ADDR ||
 				mflags == ADSP_MMAP_REMOTE_HEAP_ADDR) {
 		map->apps = me;
@@ -2496,7 +2501,7 @@ static int fastrpc_get_spd_session(char *name, int *session, int *cid)
 
 static int fastrpc_mmap_remove_pdr(struct fastrpc_file *fl);
 static int fastrpc_channel_open(struct fastrpc_file *fl);
-static int fastrpc_mmap_remove_ssr(struct fastrpc_file *fl);
+static int fastrpc_mmap_remove_ssr(struct fastrpc_file *fl, int locked);
 static int fastrpc_init_process(struct fastrpc_file *fl,
 				struct fastrpc_ioctl_init_attrs *uproc)
 {
@@ -2509,7 +2514,9 @@ static int fastrpc_init_process(struct fastrpc_file *fl,
 	struct fastrpc_buf *imem = NULL;
 	unsigned long imem_dma_attr = 0;
 	char *proc_name = NULL;
-	int unsigned_request = (uproc->attrs & FASTRPC_MODE_UNSIGNED_MODULE);
+	bool init_flags = init->flags == FASTRPC_INIT_CREATE ? true : false;
+	int proc_attrs = uproc->attrs & FASTRPC_MODE_UNSIGNED_MODULE;
+	int unsigned_request = proc_attrs && init_flags;
 	int cid = fl->cid;
 	struct fastrpc_channel_ctx *chan = &me->channel[cid];
 
@@ -2583,6 +2590,8 @@ static int fastrpc_init_process(struct fastrpc_file *fl,
 			mutex_lock(&fl->map_mutex);
 			VERIFY(err, !fastrpc_mmap_create(fl, init->filefd, 0,
 				init->file, init->filelen, mflags, &file));
+			if (file)
+				file->is_filemap = true;
 			mutex_unlock(&fl->map_mutex);
 			if (err)
 				goto bail;
@@ -2664,7 +2673,7 @@ static int fastrpc_init_process(struct fastrpc_file *fl,
 		if (!init->filelen)
 			goto bail;
 
-		proc_name = kzalloc(init->filelen, GFP_KERNEL);
+		proc_name = kzalloc(init->filelen + 1, GFP_KERNEL);
 		VERIFY(err, !IS_ERR_OR_NULL(proc_name));
 		if (err)
 			goto bail;
@@ -2692,6 +2701,8 @@ static int fastrpc_init_process(struct fastrpc_file *fl,
 			err = fastrpc_mmap_create(fl, -1, 0, init->mem,
 				 init->memlen, ADSP_MMAP_REMOTE_HEAP_ADDR,
 				 &mem);
+			if (mem)
+				mem->is_filemap = true;
 			mutex_unlock(&fl->map_mutex);
 			if (err)
 				goto bail;
@@ -3072,7 +3083,7 @@ static int fastrpc_mmap_on_dsp(struct fastrpc_file *fl, uint32_t flags,
 }
 
 static int fastrpc_munmap_on_dsp_rh(struct fastrpc_file *fl, uint64_t phys,
-						size_t size, uint32_t flags)
+					size_t size, uint32_t flags, int locked)
 {
 	int err = 0;
 	struct fastrpc_apps *me = &gfa;
@@ -3083,13 +3094,14 @@ static int fastrpc_munmap_on_dsp_rh(struct fastrpc_file *fl, uint64_t phys,
 	if (flags == ADSP_MMAP_HEAP_ADDR) {
 		struct fastrpc_ioctl_invoke_crc ioctl;
 		remote_arg_t ra[2];
-		int err = 0;
+		int err = 0, cid = 0;
 		struct {
 			uint8_t skey;
 		} routargs;
 
 		if (fl == NULL)
 			goto bail;
+		cid = fl->cid;
 		tgid = fl->tgid;
 		ra[0].buf.pv = (void *)&tgid;
 		ra[0].buf.len = sizeof(tgid);
@@ -3104,8 +3116,16 @@ static int fastrpc_munmap_on_dsp_rh(struct fastrpc_file *fl, uint64_t phys,
 		ioctl.attrs = NULL;
 		ioctl.crc = NULL;
 
+		if (locked) {
+			mutex_unlock(&fl->map_mutex);
+			mutex_unlock(&me->channel[cid].smd_mutex);
+		}
 		VERIFY(err, 0 == (err = fastrpc_internal_invoke(fl,
 				FASTRPC_MODE_PARALLEL, 1, &ioctl)));
+		if (locked) {
+			mutex_lock(&me->channel[cid].smd_mutex);
+			mutex_lock(&fl->map_mutex);
+		}
 		if (err)
 			goto bail;
 	} else if (flags == ADSP_MMAP_REMOTE_HEAP_ADDR) {
@@ -3139,7 +3159,8 @@ static int fastrpc_munmap_on_dsp(struct fastrpc_file *fl, uintptr_t raddr,
 		goto bail;
 	if (flags == ADSP_MMAP_HEAP_ADDR ||
 				flags == ADSP_MMAP_REMOTE_HEAP_ADDR) {
-		VERIFY(err, !fastrpc_munmap_on_dsp_rh(fl, phys, size, flags));
+		VERIFY(err, !fastrpc_munmap_on_dsp_rh(fl, phys, size,
+						flags, 0));
 		if (err)
 			goto bail;
 	}
@@ -3147,7 +3168,7 @@ static int fastrpc_munmap_on_dsp(struct fastrpc_file *fl, uintptr_t raddr,
 	return err;
 }
 
-static int fastrpc_mmap_remove_ssr(struct fastrpc_file *fl)
+static int fastrpc_mmap_remove_ssr(struct fastrpc_file *fl, int locked)
 {
 	struct fastrpc_mmap *match = NULL, *map = NULL;
 	struct hlist_node *n = NULL;
@@ -3170,7 +3191,7 @@ static int fastrpc_mmap_remove_ssr(struct fastrpc_file *fl)
 
 		if (match) {
 			err = fastrpc_munmap_on_dsp_rh(fl, match->phys,
-						match->size, match->flags);
+					match->size, match->flags, locked);
 			if (err)
 				goto bail;
 			if (me->ramdump_handle && me->enable_ramdump) {
@@ -3217,7 +3238,7 @@ static int fastrpc_mmap_remove_pdr(struct fastrpc_file *fl)
 	}
 	if (me->channel[fl->cid].spd[session].pdrcount !=
 		me->channel[fl->cid].spd[session].prevpdrcount) {
-		err = fastrpc_mmap_remove_ssr(fl);
+		err = fastrpc_mmap_remove_ssr(fl, 0);
 		if (err)
 			pr_warn("adsprpc: %s: %s: failed to unmap remote heap (err %d)\n",
 					__func__, current->comm, err);
@@ -4005,12 +4026,12 @@ static int fastrpc_channel_open(struct fastrpc_file *fl)
 	if (cid == ADSP_DOMAIN_ID && me->channel[cid].ssrcount !=
 			 me->channel[cid].prevssrcount) {
 		mutex_lock(&fl->map_mutex);
-		err = fastrpc_mmap_remove_ssr(fl);
+		err = fastrpc_mmap_remove_ssr(fl, 1);
+		mutex_unlock(&fl->map_mutex);
 		if (err)
 			pr_warn("adsprpc: %s: %s: failed to unmap remote heap for %s (err %d)\n",
 					__func__, current->comm,
 					me->channel[cid].subsys, err);
-		mutex_unlock(&fl->map_mutex);
 		me->channel[cid].prevssrcount =
 					me->channel[cid].ssrcount;
 	}
@@ -4088,11 +4109,14 @@ static int fastrpc_set_process_info(struct fastrpc_file *fl)
 {
 	int err = 0, buf_size = 0;
 	char strpid[PID_SIZE];
+	char cur_comm[TASK_COMM_LEN];
 
+	memcpy(cur_comm, current->comm, TASK_COMM_LEN);
+	cur_comm[TASK_COMM_LEN-1] = '\0';
 	fl->tgid = current->tgid;
 	snprintf(strpid, PID_SIZE, "%d", current->pid);
 	if (debugfs_root) {
-		buf_size = strlen(current->comm) + strlen("_")
+		buf_size = strlen(cur_comm) + strlen("_")
 			+ strlen(strpid) + 1;
 
 		spin_lock(&fl->hlock);
@@ -4107,13 +4131,13 @@ static int fastrpc_set_process_info(struct fastrpc_file *fl)
 			err = -ENOMEM;
 			return err;
 		}
-		snprintf(fl->debug_buf, UL_SIZE, "%.10s%s%d",
+		snprintf(fl->debug_buf, buf_size, "%.10s%s%d",
-			current->comm, "_", current->pid);
+			cur_comm, "_", current->pid);
 		fl->debugfs_file = debugfs_create_file(fl->debug_buf, 0644,
 			debugfs_root, fl, &debugfs_fops);
 		if (IS_ERR_OR_NULL(fl->debugfs_file)) {
 			pr_warn("Error: %s: %s: failed to create debugfs file %s\n",
-				current->comm, __func__, fl->debug_buf);
+				cur_comm, __func__, fl->debug_buf);
 			fl->debugfs_file = NULL;
 			kfree(fl->debug_buf);
 			fl->debug_buf_alloced_attempted = 0;
@@ -4551,7 +4575,6 @@ static long fastrpc_device_ioctl(struct file *file, unsigned int ioctl_num,
 		break;
 	default:
 		err = -ENOTTY;
-		pr_info("bad ioctl: %d\n", ioctl_num);
 		break;
 	}
  bail:

drivers/char/diag/diag_dci.c

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/slab.h>
@@ -1069,6 +1069,11 @@ void extract_dci_pkt_rsp(unsigned char *buf, int len, int data_source,
 		return;
 	}
 
+	if (token != entry->client_info.token) {
+		mutex_unlock(&driver->dci_mutex);
+		return;
+	}
+
 	mutex_lock(&entry->buffers[data_source].buf_mutex);
 	rsp_buf = entry->buffers[data_source].buf_cmd;
 
@@ -1740,7 +1745,16 @@ static int diag_send_dci_pkt_remote(unsigned char *data, int len, int tag,
 	write_len += dci_header_size;
 	*(int *)(buf + write_len) = tag;
 	write_len += sizeof(int);
-	memcpy(buf + write_len, data, len);
+	if ((write_len + len) < DIAG_MDM_BUF_SIZE) {
+		memcpy(buf + write_len, data, len);
+	} else {
+		pr_err("diag: skip writing invalid length packet, token: %d, pkt_len: %d\n",
+			token, (write_len + len));
+		spin_lock_irqsave(&driver->dci_mempool_lock, flags);
+		diagmem_free(driver, buf, dci_ops_tbl[token].mempool);
+		spin_unlock_irqrestore(&driver->dci_mempool_lock, flags);
+		return -EAGAIN;
+	}
 	write_len += len;
 	*(buf + write_len) = CONTROL_CHAR; /* End Terminator */
 	write_len += sizeof(uint8_t);

drivers/char/diag/diag_masks.c

@@ -54,7 +54,8 @@ static const struct diag_ssid_range_t msg_mask_tbl[] = {
 	{ .ssid_first = MSG_SSID_22, .ssid_last = MSG_SSID_22_LAST },
 	{ .ssid_first = MSG_SSID_23, .ssid_last = MSG_SSID_23_LAST },
 	{ .ssid_first = MSG_SSID_24, .ssid_last = MSG_SSID_24_LAST },
-	{ .ssid_first = MSG_SSID_25, .ssid_last = MSG_SSID_25_LAST }
+	{ .ssid_first = MSG_SSID_25, .ssid_last = MSG_SSID_25_LAST },
+	{ .ssid_first = MSG_SSID_26, .ssid_last = MSG_SSID_26_LAST }
 };
 
 static int diag_save_user_msg_mask(struct diag_md_session_t *info);

drivers/char/diag/diag_memorydevice.c

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/slab.h>
@@ -330,13 +330,19 @@ int diag_md_copy_to_user(char __user *buf, int *pret, size_t buf_size,
 	struct diag_md_info *ch = NULL;
 	struct diag_buf_tbl_t *entry = NULL;
 	uint8_t drain_again = 0;
-	int peripheral = 0;
+	int peripheral = 0, tmp_len = 0;
 	struct diag_md_session_t *session_info = NULL;
 	struct pid *pid_struct = NULL;
 	struct task_struct *task_s = NULL;
+	unsigned char *tmp_buf = NULL;
 
 	if (!info)
 		return -EINVAL;
+
+	tmp_buf = vzalloc(MAX_PERIPHERAL_HDLC_BUF_SZ);
+	if (!tmp_buf)
+		return -ENOMEM;
+
 	for (i = 0; i < NUM_DIAG_MD_DEV && !err; i++) {
 		ch = &diag_md[i];
 		if (!ch->md_info_inited)
@@ -348,6 +354,8 @@ int diag_md_copy_to_user(char __user *buf, int *pret, size_t buf_size,
 				spin_unlock_irqrestore(&ch->lock, flags);
 				continue;
 			}
+			tmp_len = entry->len;
+			memcpy(tmp_buf, entry->buf, entry->len);
 			peripheral = diag_md_get_peripheral(entry->ctx);
 			if (peripheral < 0) {
 				spin_unlock_irqrestore(&ch->lock, flags);
@@ -383,14 +391,6 @@ int diag_md_copy_to_user(char __user *buf, int *pret, size_t buf_size,
 					drain_again = 1;
 					break;
 				}
-			} else {
-				if ((ret + (2 * sizeof(int)) + entry->len) >=
-						buf_size) {
-					drain_again = 1;
-					break;
-				}
-			}
-			if (i > 0) {
 				remote_token = diag_get_remote(i);
 				task_s = get_pid_task(pid_struct, PIDTYPE_PID);
 				if (task_s) {
@@ -404,23 +404,20 @@ int diag_md_copy_to_user(char __user *buf, int *pret, size_t buf_size,
 					ret += sizeof(int);
 					put_task_struct(task_s);
 				}
+			} else {
+				if ((ret + (2 * sizeof(int)) + entry->len) >=
+						buf_size) {
+					drain_again = 1;
+					break;
+				}
 			}
 
 			task_s = get_pid_task(pid_struct, PIDTYPE_PID);
 			if (task_s) {
-				spin_lock_irqsave(&ch->lock, flags);
-				entry = &ch->tbl[j];
-				if (entry->len <= 0 || entry->buf == NULL) {
-					spin_unlock_irqrestore(&ch->lock,
-						flags);
-					continue;
-				}
-				spin_unlock_irqrestore(&ch->lock,
-						flags);
 				/* Copy the length of data being passed */
-				if (entry->len) {
+				if (tmp_len) {
 					err = copy_to_user(buf + ret,
-							(void *)&(entry->len),
+							(void *)&(tmp_len),
 							sizeof(int));
 					if (err) {
 						put_task_struct(task_s);
@@ -430,10 +427,10 @@ int diag_md_copy_to_user(char __user *buf, int *pret, size_t buf_size,
 				}
 
 				/* Copy the actual data being passed */
-				if (entry->buf) {
+				if (tmp_buf) {
 					err = copy_to_user(buf + ret,
-							(void *)entry->buf,
+							(void *)tmp_buf,
-							entry->len);
+							tmp_len);
 					if (err) {
 						put_task_struct(task_s);
 						goto drop_data;
@@ -467,6 +464,8 @@ int diag_md_copy_to_user(char __user *buf, int *pret, size_t buf_size,
 			spin_unlock_irqrestore(&ch->lock, flags);
 
 			put_pid(pid_struct);
+			memset(tmp_buf, 0, MAX_PERIPHERAL_HDLC_BUF_SZ);
+			tmp_len = 0;
 		}
 	}
 
@@ -482,6 +481,8 @@ int diag_md_copy_to_user(char __user *buf, int *pret, size_t buf_size,
 		}
 		put_pid(pid_struct);
 	}
+	vfree(tmp_buf);
+	tmp_buf = NULL;
 	diag_ws_on_copy_complete(DIAG_WS_MUX);
 	if (drain_again)
 		chk_logging_wakeup();

drivers/char/diag/diagchar_core.c

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2008-2020, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2008-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/slab.h>
@@ -376,6 +376,8 @@ static int diagchar_open(struct inode *inode, struct file *file)
 		if (driver->ref_count == 0)
 			diag_mempool_init();
 		driver->ref_count++;
+		DIAG_LOG(DIAG_DEBUG_USERSPACE,
+		"diag: open successful for client pid: %d\n", current->tgid);
 		mutex_unlock(&driver->diagchar_mutex);
 		return 0;
 	}
@@ -3794,6 +3796,9 @@ static ssize_t diagchar_read(struct file *file, char __user *buf, size_t count,
 
 	if (driver->data_ready[index] & MSG_MASKS_TYPE) {
 		/*Copy the type of data being passed*/
+		DIAG_LOG(DIAG_DEBUG_MASKS,
+		"diag: msg masks update to client pid: %d\n", current->tgid);
+
 		data_type = driver->data_ready[index] & MSG_MASKS_TYPE;
 		mutex_unlock(&driver->diagchar_mutex);
 		mutex_lock(&driver->md_session_lock);
@@ -3815,11 +3820,19 @@ static ssize_t diagchar_read(struct file *file, char __user *buf, size_t count,
 		mutex_lock(&driver->diagchar_mutex);
 		driver->data_ready[index] ^= MSG_MASKS_TYPE;
 		atomic_dec(&driver->data_ready_notif[index]);
+
+		DIAG_LOG(DIAG_DEBUG_MASKS,
+		"diag: msg masks update complete for client pid: %d\n",
+		current->tgid);
+
 		goto exit;
 	}
 
 	if (driver->data_ready[index] & EVENT_MASKS_TYPE) {
 		/*Copy the type of data being passed*/
+		DIAG_LOG(DIAG_DEBUG_MASKS,
+		"diag: event masks update to client pid: %d\n", current->tgid);
+
 		data_type = driver->data_ready[index] & EVENT_MASKS_TYPE;
 		mutex_unlock(&driver->diagchar_mutex);
 		mutex_lock(&driver->md_session_lock);
@@ -3852,11 +3865,19 @@ static ssize_t diagchar_read(struct file *file, char __user *buf, size_t count,
 		mutex_lock(&driver->diagchar_mutex);
 		driver->data_ready[index] ^= EVENT_MASKS_TYPE;
 		atomic_dec(&driver->data_ready_notif[index]);
+
+		DIAG_LOG(DIAG_DEBUG_MASKS,
+		"diag: %s: event masks update complete for client pid: %d\n",
+		current->tgid);
+
 		goto exit;
 	}
 
 	if (driver->data_ready[index] & LOG_MASKS_TYPE) {
 		/*Copy the type of data being passed*/
+		DIAG_LOG(DIAG_DEBUG_MASKS,
+		"diag: log masks update to client pid: %d\n", current->tgid);
+
 		data_type = driver->data_ready[index] & LOG_MASKS_TYPE;
 		mutex_unlock(&driver->diagchar_mutex);
 		mutex_lock(&driver->md_session_lock);
@@ -3878,6 +3899,11 @@ static ssize_t diagchar_read(struct file *file, char __user *buf, size_t count,
 		mutex_lock(&driver->diagchar_mutex);
 		driver->data_ready[index] ^= LOG_MASKS_TYPE;
 		atomic_dec(&driver->data_ready_notif[index]);
+
+		DIAG_LOG(DIAG_DEBUG_MASKS,
+		"diag: log masks update complete for client pid: %d\n",
+		current->tgid);
+
 		goto exit;
 	}
 

drivers/char/diag/diagfwd_peripheral.c

@@ -178,7 +178,7 @@ static int diag_add_hdlc_encoding(unsigned char *dest_buf, int *dest_len,
 
 static int check_bufsize_for_encoding(struct diagfwd_buf_t *buf, uint32_t len)
 {
-	int i, ctx = 0;
+	int i, ctx = 0, flag_64k = 0;
 	uint32_t max_size = 0;
 	unsigned long flags;
 	unsigned char *temp_buf = NULL;
@@ -189,10 +189,11 @@ static int check_bufsize_for_encoding(struct diagfwd_buf_t *buf, uint32_t len)
 
 	max_size = (2 * len) + 3;
 	if (max_size > PERIPHERAL_BUF_SZ) {
-		if (max_size > MAX_PERIPHERAL_HDLC_BUF_SZ) {
+		if (max_size > MAX_PERIPHERAL_BUF_SZ) {
-			pr_err("diag: In %s, max_size is going beyond limit %d\n",
+			pr_err("diag: In %s, max_size (%d) is going beyond 32k\n",
 			       __func__, max_size);
 			max_size = MAX_PERIPHERAL_HDLC_BUF_SZ;
+			flag_64k = 1;
 		}
 
 		mutex_lock(&driver->md_session_lock);
@@ -229,11 +230,19 @@ static int check_bufsize_for_encoding(struct diagfwd_buf_t *buf, uint32_t len)
 				mutex_unlock(&driver->md_session_lock);
 				return -ENOMEM;
 			}
-			DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
-			"Reallocated data buffer: %pK with size: %d\n",
-			temp_buf, max_size);
 			buf->data = temp_buf;
-			buf->len = max_size;
+
+			if (flag_64k)
+				buf->len = MAX_PERIPHERAL_HDLC_BUF_SZ;
+			else
+				buf->len = MAX_PERIPHERAL_BUF_SZ;
+
+			DIAG_LOG(DIAG_DEBUG_PERIPHERALS,
+			"diag: Reallocated data buffer: %pK with size: %d, max_buf_len: %d, p: %d, t: %d, n: %d\n",
+			temp_buf, max_size, buf->len,
+			GET_BUF_PERIPHERAL(buf->ctxt),
+			GET_BUF_TYPE(buf->ctxt),
+			GET_BUF_NUM(buf->ctxt));
 		}
 		mutex_unlock(&driver->md_session_lock);
 	}

drivers/char/diag/diagfwd_peripheral.h

@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2019, 2021 The Linux Foundation. All rights reserved.
  */
 
 #ifndef DIAGFWD_PERIPHERAL_H
@@ -7,7 +7,7 @@
 
 #define PERIPHERAL_BUF_SZ		16384
 #define MAX_PERIPHERAL_BUF_SZ		32768
-#define MAX_PERIPHERAL_HDLC_BUF_SZ	65539
+#define MAX_PERIPHERAL_HDLC_BUF_SZ	65536
 
 #define TRANSPORT_UNKNOWN		-1
 #define TRANSPORT_SOCKET		0

drivers/char/diag/diagfwd_rpmsg.c

@@ -22,6 +22,7 @@
 #include "diag_ipc_logging.h"
 
 #define PERI_RPMSG rpmsg_info->peripheral
+#define RX_LIST_MAX_PKT_CNT	10
 
 struct diag_rpmsg_read_work {
 	struct work_struct work;
@@ -717,8 +718,15 @@ static void diag_rpmsg_notify_rx_work_fn(struct work_struct *work)
 			spin_unlock_irqrestore(&read_work_struct->rx_lock,
 								flags);
 		} else {
+			rpmsg_info->list_pkt_cnt += 1;
+			if (rpmsg_info->list_pkt_cnt > RX_LIST_MAX_PKT_CNT)
+				list_del(&rx_item->list);
 			spin_unlock_irqrestore(&read_work_struct->rx_lock,
 								flags);
+			if (rpmsg_info->list_pkt_cnt > RX_LIST_MAX_PKT_CNT) {
+				kfree(rx_item->rpmsg_rx_buf);
+				kfree(rx_item);
+			}
 			goto end;
 		}
 
@@ -782,6 +790,9 @@ void rpmsg_mark_buffers_free(uint8_t peripheral, uint8_t type, int buf_num)
 		rpmsg_info->buf2 = NULL;
 		DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "marked buf2 NULL");
 	}
+
+	if (rpmsg_info->list_pkt_cnt > 0)
+		rpmsg_info->list_pkt_cnt -= 1;
 }
 
 static void rpmsg_late_init(struct diag_rpmsg_info *rpmsg_info)
@@ -850,6 +861,7 @@ static void __diag_rpmsg_init(struct diag_rpmsg_info *rpmsg_info)
 	rpmsg_info->hdl = NULL;
 	rpmsg_info->fwd_ctxt = NULL;
 	rpmsg_info->probed = 0;
+	rpmsg_info->list_pkt_cnt = 0;
 	atomic_set(&rpmsg_info->opened, 0);
 	atomic_set(&rpmsg_info->diag_state, 0);
 	DIAG_LOG(DIAG_DEBUG_PERIPHERALS,

drivers/char/diag/diagfwd_rpmsg.h

@@ -16,6 +16,7 @@ struct diag_rpmsg_info {
 	atomic_t opened;
 	atomic_t diag_state;
 	uint32_t fifo_size;
+	uint32_t list_pkt_cnt;
 	struct rpmsg_device *hdl;
 	char edge[DIAG_RPMSG_NAME_SZ];
 	char name[DIAG_RPMSG_NAME_SZ];

drivers/char/diag/diagmem.c

@@ -172,7 +172,7 @@ void *diagmem_alloc(struct diagchar_dev *driver, int size, int pool_type)
 			break;
 		}
 		if (size == 0 || size > mempool->itemsize ||
-			size > (int)mempool->pool->pool_data) {
+			size > (size_t)mempool->pool->pool_data) {
 			pr_err_ratelimited("diag: cannot alloc from mempool %s, invalid size: %d\n",
 					   mempool->name, size);
 			break;

drivers/clk/qcom/Kconfig

@@ -608,3 +608,44 @@ config CLOCK_CPU_SDM
 	 Support for the cpu clock controller on SDM based devices(e.g. QM215/SDM429).
 	 Say Y if you want to support CPU clock scaling using
 	 CPUfreq drivers for dynamic power management.
+
+config SM_GCC_KHAJE
+	tristate "KHAJE Global Clock Controller"
+	depends on COMMON_CLK_QCOM
+	help
+	 Support for the global clock controller on KHAJE devices.
+	 Say Y if you want to use peripheral devices such as UART, SPI,
+	 I2C, USB, UFS, SDCC, PCIe, Camera, Video etc.
+
+config SM_GPUCC_KHAJE
+	tristate "KHAJE Graphics Clock Controller"
+	select SM_GCC_KHAJE
+	help
+	 Support for the graphics clock controller on Qualcomm Technologies, Inc
+	 KHAJE devices.
+	 Say Y if you want to support graphics controller devices.
+
+config SM_DISPCC_KHAJE
+	tristate "KHAJE Display Clock Controller"
+	select SM_GCC_KHAJE
+	help
+	 Support for the display clock controller on Qualcomm Technologies, Inc.
+	 KHAJE devices.
+	 Say Y if you want to support display devices and functionality such as
+	 splash screen.
+
+config SM_DEBUGCC_KHAJE
+	tristate "KHAJE Debug Clock Controller"
+	select SM_GCC_KHAJE
+	help
+	 Support for the debug clock controller on Qualcomm Technologies, Inc
+	 KHAJE devices.
+	 Say Y if you want to support the clock measurement functionality.
+
+config SDM_DEBUGCC_439
+	tristate "SDM439 SDM429 Debug Clock Controller"
+	depends on SDM_GCC_429W
+	help
+	  Support for the debug clock controller on Qualcomm Technologies, Inc
+	  SDM429/SDM439 devices.
+	  Say Y if you want to support the clock measurement functionality.

drivers/clk/qcom/Makefile

@@ -57,6 +57,7 @@ obj-$(CONFIG_QM_GPUCC_SCUBA) += gpucc-scuba.o
 obj-$(CONFIG_QM_DEBUGCC_SCUBA) += debugcc-scuba.o
 obj-$(CONFIG_SDM_CAMCC_LAGOON) += camcc-lagoon.o
 obj-$(CONFIG_SDM_DEBUGCC_429W) += debugcc-sdm429w.o
+obj-$(CONFIG_SDM_DEBUGCC_439) += debugcc-sdm439.o
 obj-$(CONFIG_SDM_DEBUGCC_LAGOON) += debugcc-lagoon.o
 obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
 obj-$(CONFIG_SDM_DISPCC_LAGOON) += dispcc-lagoon.o
@@ -72,12 +73,16 @@ obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
 obj-$(CONFIG_SDM_VIDEOCC_LAGOON) += videocc-lagoon.o
 obj-$(CONFIG_SM_CAMCC_LITO) += camcc-lito.o
 obj-$(CONFIG_SM_DEBUGCC_BENGAL) += debugcc-bengal.o
+obj-$(CONFIG_SM_DEBUGCC_KHAJE) += debugcc-khaje.o
 obj-$(CONFIG_SM_DEBUGCC_LITO) += debugcc-lito.o
 obj-$(CONFIG_SM_DISPCC_BENGAL) += dispcc-bengal.o
+obj-$(CONFIG_SM_DISPCC_KHAJE) += dispcc-khaje.o
 obj-$(CONFIG_SM_DISPCC_LITO) += dispcc-lito.o
 obj-$(CONFIG_SM_GCC_BENGAL) += gcc-bengal.o
+obj-$(CONFIG_SM_GCC_KHAJE) += gcc-khaje.o
 obj-$(CONFIG_SM_GCC_LITO) += gcc-lito.o
 obj-$(CONFIG_SM_GPUCC_BENGAL) += gpucc-bengal.o
+obj-$(CONFIG_SM_GPUCC_KHAJE) += gpucc-khaje.o
 obj-$(CONFIG_SM_GPUCC_LITO) += gpucc-lito.o
 obj-$(CONFIG_SM_NPUCC_LITO) += npucc-lito.o
 obj-$(CONFIG_SM_VIDEOCC_LITO) += videocc-lito.o

drivers/clk/qcom/clk-alpha-pll.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (c) 2015, 2018-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015, 2018-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/kernel.h>
@@ -30,6 +30,7 @@
 #define PLL_VOTE_FSM_RESET	BIT(21)
 #define PLL_UPDATE		BIT(22)
 #define PLL_UPDATE_BYPASS	BIT(23)
+#define PLL_FSM_LEGACY_MODE	BIT(24)
 #define PLL_ALPHA_EN		BIT(24)
 #define PLL_OFFLINE_ACK		BIT(28)
 #define ALPHA_PLL_ACK_LATCH	BIT(29)
@@ -509,9 +510,22 @@ alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
 	return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
 }
 
+static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate,
+									u32 *l)
+{
+	u64 remainder, quotient;
+
+	quotient = rate;
+	remainder = do_div(quotient, prate);
+	*l = quotient;
+
+	if ((remainder * 2) / prate)
+		*l = *l + 1;
+}
+
 static unsigned long
 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
-		     u32 alpha_width)
+			u32 alpha_width)
 {
 	u64 remainder;
 	u64 quotient;
@@ -1265,10 +1279,10 @@ static int clk_zonda_pll_enable(struct clk_hw *hw)
 static void clk_zonda_pll_disable(struct clk_hw *hw)
 {
 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
-	u32 val, mask, off = pll->offset;
+	u32 val, mask;
 	int ret;
 
-	ret = regmap_read(pll->clkr.regmap, off + PLL_MODE(pll), &val);
+	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 	if (ret)
 		return;
 
@@ -1304,12 +1318,13 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 {
 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 	unsigned long rrate;
-	u32 test_ctl_val;
+	u32 test_ctl_val, alpha_width = pll_alpha_width(pll);
 	u32 l;
 	u64 a;
 	int ret;
 
-	rrate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_BITWIDTH);
+	rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
+
 	/*
 	 * Due to a limited number of bits for fractional rate programming, the
 	 * rounded up rate could be marginally higher than the requested rate.
@@ -1320,9 +1335,15 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 		return -EINVAL;
 	}
 
+	if (a && (a & BIT(15)))
+		zonda_pll_adjust_l_val(rate, prate, &l);
+
 	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
 	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
 
+	if (!clk_hw_is_enabled(hw))
+		return 0;
+
 	/* Wait before polling for the frequency latch */
 	udelay(5);
 
@@ -1344,16 +1365,33 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 	return 0;
 }
 
+static unsigned long alpha_pll_adjust_calc_rate(u64 prate, u32 l, u32 frac,
+		u32 alpha_width)
+{
+	uint64_t tmp;
+
+	frac = 100 - DIV_ROUND_UP_ULL((frac * 100), BIT(alpha_width));
+
+	tmp = frac * prate;
+	do_div(tmp, 100);
+
+	return (l * prate) - tmp;
+}
+
 static unsigned long
 clk_zonda_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 {
 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
-	u32 l, frac;
+	u32 l, frac, alpha_width = pll_alpha_width(pll);
 
 	regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
 	regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
 
-	return alpha_pll_calc_rate(parent_rate, l, frac, ALPHA_BITWIDTH);
+	if (frac & BIT(15))
+		return alpha_pll_adjust_calc_rate(parent_rate, l, frac,
+								alpha_width);
+	else
+		return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
 }
 
 static void clk_zonda_pll_list_registers(struct seq_file *f, struct clk_hw *hw)
@@ -2076,6 +2114,9 @@ void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 				 PLL_UPDATE_BYPASS,
 				 PLL_UPDATE_BYPASS);
 
+	if (pll->flags & SUPPORTS_FSM_LEGACY_MODE)
+		regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE,
+						PLL_FSM_LEGACY_MODE);
 	/* Disable PLL output */
 	regmap_update_bits(regmap, PLL_MODE(pll),
 					PLL_OUTCTRL, 0);
@@ -2678,8 +2719,7 @@ static int clk_alpha_pll_calibrate(struct clk_hw *hw)
 	 * So slew pll to the previously set frequency.
 	 */
 	freq_hz = alpha_pll_round_rate(clk_hw_get_rate(hw),
-			clk_hw_get_rate(parent), &l, &a, alpha_width);
+				clk_hw_get_rate(parent), &l, &a, alpha_width);
-
 
 	pr_debug("pll %s: setting back to required rate %lu, freq_hz %ld\n",
 				hw->init->name, clk_hw_get_rate(hw), freq_hz);

drivers/clk/qcom/clk-alpha-pll.h

@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2015, 2018-2020, The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2015, 2018-2021, The Linux Foundation. All rights reserved. */
 
 #ifndef __QCOM_CLK_ALPHA_PLL_H__
 #define __QCOM_CLK_ALPHA_PLL_H__
@@ -91,6 +91,7 @@ struct clk_alpha_pll {
 #define SUPPORTS_SLEW		BIT(4)
 	/* Associated with soft_vote for multiple PLL software instances */
 #define SUPPORTS_FSM_VOTE	BIT(5)
+#define SUPPORTS_FSM_LEGACY_MODE BIT(6)
 	u8 flags;
 
 	struct clk_regmap clkr;

drivers/clk/qcom/clk-cpu-sdm.c

@@ -27,6 +27,8 @@
 	container_of(to_clk_regmap(_hw), struct clk_regmap_mux_div, clkr)
 
 static DEFINE_VDD_REGULATORS(vdd_hf_pll, VDD_HF_PLL_NUM, 2, vdd_hf_levels);
+static DEFINE_VDD_REGULATORS(vdd_sr2_pll, VDD_HF_PLL_NUM, 2, vdd_hf_levels);
+static DEFINE_VDD_REGS_INIT(vdd_cpu_c0, 1);
 static DEFINE_VDD_REGS_INIT(vdd_cpu_c1, 1);
 static DEFINE_VDD_REGS_INIT(vdd_cpu_cci, 1);
 
@@ -36,29 +38,22 @@ enum apcs_mux_clk_parent {
 	P_APCS_CPU_PLL,
 };
 
-struct pll_spm_ctrl {
-	u32 offset;
-	u32 force_event_offset;
-	u32 event_bit;
-	void __iomem *spm_base;
-};
-
-static struct pll_spm_ctrl apcs_pll_spm = {
-	.offset = 0x50,
-	.force_event_offset = 0x4,
-	.event_bit = 0x4,
-};
-
 static const struct parent_map apcs_mux_clk_parent_map0[] = {
 	{ P_BI_TCXO_AO, 0 },
 	{ P_GPLL0_AO_OUT_MAIN, 4 },
 	{ P_APCS_CPU_PLL, 5 },
 };
 
-static const char *const apcs_mux_clk_parent_name0[] = {
+static const char *const apcs_mux_clk_c1_parent_name0[] = {
 	"bi_tcxo_ao",
 	"gpll0_ao_out_main",
-	"apcs_cpu_pll",
+	"apcs_cpu_pll1",
+};
+
+static const char *const apcs_mux_clk_c0_parent_name0[] = {
+	"bi_tcxo_ao",
+	"gpll0_ao_out_main",
+	"apcs_cpu_pll0",
 };
 
 static const struct parent_map apcs_mux_clk_parent_map1[] = {
@@ -111,6 +106,20 @@ static int cpucc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 	return mux_div_set_src_div(cpuclk, cpuclk->src, cpuclk->div);
 }
 
+static bool freq_from_gpll0(unsigned long req_rate, unsigned long gpll0_rate)
+{
+	unsigned long temp;
+	int div;
+
+	for (div = 10; div <= 40; div += 5) {
+		temp = mult_frac(gpll0_rate, 10, div);
+		if (req_rate == temp)
+			return true;
+	}
+
+	return false;
+}
+
 static int cpucc_clk_determine_rate(struct clk_hw *hw,
 					struct clk_rate_request *req)
 {
@@ -137,7 +146,7 @@ static int cpucc_clk_determine_rate(struct clk_hw *hw,
 	apcs_gpll0_rate = clk_hw_get_rate(apcs_gpll0_hw);
 	apcs_gpll0_rrate = DIV_ROUND_UP(apcs_gpll0_rate, 1000000) * 1000000;
 
-	if (rate <= apcs_gpll0_rrate) {
+	if (freq_from_gpll0(rate, apcs_gpll0_rrate)) {
 		req->best_parent_hw = apcs_gpll0_hw;
 		req->best_parent_rate = apcs_gpll0_rrate;
 		div = DIV_ROUND_CLOSEST(2 * apcs_gpll0_rrate, rate) - 1;
@@ -227,48 +236,7 @@ static u8 cpucc_clk_get_parent(struct clk_hw *hw)
 	return clk_regmap_mux_div_ops.get_parent(hw);
 }
 
-static void spm_event(struct pll_spm_ctrl *apcs_pll_spm, bool enable)
+static void do_nothing(void *unused) { }
-{
-	void __iomem *base = apcs_pll_spm->spm_base;
-	u32 offset, force_event_offset, bit, val;
-
-	if (!apcs_pll_spm || !base)
-		return;
-
-	offset = apcs_pll_spm->offset;
-	force_event_offset = apcs_pll_spm->force_event_offset;
-	bit = apcs_pll_spm->event_bit;
-
-	if (enable) {
-		/* L2_SPM_FORCE_EVENT_EN */
-		val = readl_relaxed(base + offset);
-		val |= BIT(bit);
-		writel_relaxed(val, (base + offset));
-		/* Ensure that the write above goes through. */
-		mb();
-
-		/* L2_SPM_FORCE_EVENT */
-		val = readl_relaxed(base + offset + force_event_offset);
-		val |= BIT(bit);
-		writel_relaxed(val, (base + offset + force_event_offset));
-		/* Ensure that the write above goes through. */
-		mb();
-	} else {
-		/* L2_SPM_FORCE_EVENT */
-		val = readl_relaxed(base + offset + force_event_offset);
-		val &= ~BIT(bit);
-		writel_relaxed(val, (base + offset + force_event_offset));
-		/* Ensure that the write above goes through. */
-		mb();
-
-		/* L2_SPM_FORCE_EVENT_EN */
-		val = readl_relaxed(base + offset);
-		val &= ~BIT(bit);
-		writel_relaxed(val, (base + offset));
-		/* Ensure that the write above goes through. */
-		mb();
-	}
-}
 
 /*
  * We use the notifier function for switching to a temporary safe configuration
@@ -279,17 +247,31 @@ static int cpucc_notifier_cb(struct notifier_block *nb, unsigned long event,
 {
 	struct clk_regmap_mux_div *cpuclk = container_of(nb,
 					struct clk_regmap_mux_div, clk_nb);
+	bool hw_low_power_ctrl = cpuclk->clk_lpm.hw_low_power_ctrl;
 	int ret = 0, safe_src = cpuclk->safe_src;
 
 	switch (event) {
 	case PRE_RATE_CHANGE:
+		if (hw_low_power_ctrl) {
+			memset(&cpuclk->clk_lpm.req, 0,
+					sizeof(cpuclk->clk_lpm.req));
+			cpumask_copy(&cpuclk->clk_lpm.req.cpus_affine,
+			(const struct cpumask *)&cpuclk->clk_lpm.cpu_reg_mask);
+			cpuclk->clk_lpm.req.type = PM_QOS_REQ_AFFINE_CORES;
+			pm_qos_add_request(&cpuclk->clk_lpm.req,
+				PM_QOS_CPU_DMA_LATENCY,
+				cpuclk->clk_lpm.cpu_latency_no_l2_pc_us - 1);
+			smp_call_function_any(&cpuclk->clk_lpm.cpu_reg_mask,
+				do_nothing, NULL, 1);
+		}
+
 		/* set the mux to safe source gpll0_ao_out & div */
-		ret = mux_div_set_src_div(cpuclk, safe_src, 1);
+		mux_div_set_src_div(cpuclk, safe_src, 1);
-		spm_event(&apcs_pll_spm, true);
 		break;
 	case POST_RATE_CHANGE:
-		if (cpuclk->src != safe_src)
+		if (hw_low_power_ctrl)
-			spm_event(&apcs_pll_spm, false);
+			pm_qos_remove_request(&cpuclk->clk_lpm.req);
+
 		break;
 	case ABORT_RATE_CHANGE:
 		pr_err("Error in configuring PLL - stay at safe src only\n");
@@ -324,7 +306,7 @@ static const struct pll_config apcs_cpu_pll_config = {
 	.aux_output_mask = BIT(1),
 };
 
-static struct clk_pll apcs_cpu_pll = {
+static struct clk_pll apcs_cpu_pll0 = {
 	.mode_reg = 0x0,
 	.l_reg = 0x4,
 	.m_reg = 0x8,
@@ -332,8 +314,68 @@ static struct clk_pll apcs_cpu_pll = {
 	.config_reg = 0x10,
 	.status_reg = 0x1c,
 	.status_bit = 16,
+	.spm_ctrl = {
+		.offset = 0x50,
+		.event_bit = 0x4,
+	},
 	.clkr.hw.init = &(struct clk_init_data){
-		.name = "apcs_cpu_pll",
+		.name = "apcs_cpu_pll0",
+		.parent_names = (const char *[]){ "bi_tcxo_ao" },
+		.num_parents = 1,
+		.ops = &clk_pll_hf_ops,
+		.vdd_class = &vdd_sr2_pll,
+		.rate_max = (unsigned long[VDD_HF_PLL_NUM]) {
+			[VDD_HF_PLL_SVS] = 1000000000,
+			[VDD_HF_PLL_NOM] = 1900000000,
+		},
+		.num_rate_max = VDD_HF_PLL_NUM,
+	},
+};
+
+static struct clk_regmap_mux_div apcs_mux_c0_clk = {
+	.reg_offset = 0x0,
+	.hid_width  = 5,
+	.hid_shift  = 0,
+	.src_width  = 3,
+	.src_shift  = 8,
+	.safe_src = 4,
+	.safe_div = 1,
+	.parent_map = apcs_mux_clk_parent_map0,
+	.clk_nb.notifier_call = cpucc_notifier_cb,
+	.clk_lpm = {
+		/* CPU 4 - 7 */
+		.cpu_reg_mask = { 0xf0 },
+		.latency_lvl = {
+			.affinity_level = LPM_AFF_LVL_L2,
+			.reset_level = LPM_RESET_LVL_GDHS,
+			.level_name = "pwr",
+		},
+		.cpu_latency_no_l2_pc_us = 300,
+	},
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "apcs_mux_c0_clk",
+		.parent_names = apcs_mux_clk_c0_parent_name0,
+		.num_parents = 3,
+		.vdd_class = &vdd_cpu_c0,
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &cpucc_clk_ops,
+	},
+};
+
+static struct clk_pll apcs_cpu_pll1 = {
+	.mode_reg = 0x0,
+	.l_reg = 0x4,
+	.m_reg = 0x8,
+	.n_reg = 0xc,
+	.config_reg = 0x10,
+	.status_reg = 0x1c,
+	.status_bit = 16,
+	.spm_ctrl = {
+		.offset = 0x50,
+		.event_bit = 0x4,
+	},
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "apcs_cpu_pll1",
 		.parent_names = (const char *[]){ "bi_tcxo_ao" },
 		.num_parents = 1,
 		.ops = &clk_pll_hf_ops,
@@ -356,9 +398,19 @@ static struct clk_regmap_mux_div apcs_mux_c1_clk = {
 	.safe_div = 1,
 	.parent_map = apcs_mux_clk_parent_map0,
 	.clk_nb.notifier_call = cpucc_notifier_cb,
+	.clk_lpm  = {
+		/* CPU 0 - 3*/
+		.cpu_reg_mask = { 0xf },
+		.latency_lvl = {
+			.affinity_level = LPM_AFF_LVL_L2,
+			.reset_level = LPM_RESET_LVL_GDHS,
+			.level_name = "perf",
+		},
+		.cpu_latency_no_l2_pc_us = 300,
+	},
 	.clkr.hw.init = &(struct clk_init_data) {
 		.name = "apcs_mux_c1_clk",
-		.parent_names = apcs_mux_clk_parent_name0,
+		.parent_names = apcs_mux_clk_c1_parent_name0,
 		.num_parents = 3,
 		.vdd_class = &vdd_cpu_c1,
 		.flags = CLK_SET_RATE_PARENT,
@@ -386,6 +438,7 @@ static struct clk_regmap_mux_div apcs_mux_cci_clk = {
 };
 
 static const struct of_device_id match_table[] = {
+	{ .compatible = "qcom,cpu-clock-sdm439" },
 	{ .compatible = "qcom,cpu-clock-sdm429" },
 	{ .compatible = "qcom,cpu-clock-qm215" },
 	{}
@@ -400,15 +453,24 @@ static struct regmap_config cpu_regmap_config = {
 };
 
 static struct clk_hw *cpu_clks_hws_qm215[] = {
-	[APCS_CPU_PLL] = &apcs_cpu_pll.clkr.hw,
+	[APCS_CPU_PLL1] = &apcs_cpu_pll1.clkr.hw,
 	[APCS_MUX_C1_CLK] = &apcs_mux_c1_clk.clkr.hw,
 };
 
 static struct clk_hw *cpu_clks_hws_sdm429[] = {
-	[APCS_CPU_PLL] = &apcs_cpu_pll.clkr.hw,
+	[APCS_CPU_PLL1] = &apcs_cpu_pll1.clkr.hw,
 	[APCS_MUX_C1_CLK] = &apcs_mux_c1_clk.clkr.hw,
 	[APCS_MUX_CCI_CLK] = &apcs_mux_cci_clk.clkr.hw,
 };
+
+static struct clk_hw *cpu_clks_hws_sdm439[] = {
+	[APCS_CPU_PLL1] = &apcs_cpu_pll1.clkr.hw,
+	[APCS_MUX_C1_CLK] = &apcs_mux_c1_clk.clkr.hw,
+	[APCS_MUX_CCI_CLK] = &apcs_mux_cci_clk.clkr.hw,
+	[APCS_CPU_PLL0] = &apcs_cpu_pll0.clkr.hw,
+	[APCS_MUX_C0_CLK] = &apcs_mux_c0_clk.clkr.hw,
+};
+
 static void cpucc_clk_get_speed_bin(struct platform_device *pdev, int *bin,
 							int *version)
 {
@@ -559,41 +621,74 @@ cpucc_clk_add_opp(struct clk_hw *hw, struct device *dev, unsigned long max_rate)
 	return 0;
 }
 
-static void cpucc_clk_print_opp_table(int cpu)
+static void cpucc_clk_print_opp_table(int c0, int c1, bool is_sdm439)
 {
 	struct dev_pm_opp *oppfmax, *oppfmin;
-	unsigned long apc_c1_fmax, apc_c1_fmin;
+	unsigned long apc_c0_fmax, apc_c0_fmin, apc_c1_fmax, apc_c1_fmin;
-	u32 max_index = apcs_mux_c1_clk.clkr.hw.init->num_rate_max;
+	u32 max_index;
 
+	max_index = apcs_mux_c1_clk.clkr.hw.init->num_rate_max;
 	apc_c1_fmax = apcs_mux_c1_clk.clkr.hw.init->rate_max[max_index - 1];
 	apc_c1_fmin = apcs_mux_c1_clk.clkr.hw.init->rate_max[1];
 
-	oppfmax = dev_pm_opp_find_freq_exact(get_cpu_device(cpu),
+	oppfmax = dev_pm_opp_find_freq_exact(get_cpu_device(c1),
-					apc_c1_fmax, true);
+		apc_c1_fmax, true);
-	oppfmin = dev_pm_opp_find_freq_exact(get_cpu_device(cpu),
+	oppfmin = dev_pm_opp_find_freq_exact(get_cpu_device(c1),
-					apc_c1_fmin, true);
+		apc_c1_fmin, true);
-	pr_info("Clock_cpu:(cpu %d) OPP voltage for %lu: %ld\n", cpu,
+
+	pr_info("Clock_cpu:(cpu %d) OPP voltage for %lu: %ld\n", c1,
 		 apc_c1_fmin, dev_pm_opp_get_voltage(oppfmin));
-	pr_info("Clock_cpu:(cpu %d) OPP voltage for %lu: %ld\n", cpu,
+	pr_info("Clock_cpu:(cpu %d) OPP voltage for %lu: %ld\n", c1,
 		 apc_c1_fmax, dev_pm_opp_get_voltage(oppfmax));
 
+	if (is_sdm439) {
+		max_index = apcs_mux_c0_clk.clkr.hw.init->num_rate_max;
+		apc_c0_fmax =
+			apcs_mux_c0_clk.clkr.hw.init->rate_max[max_index - 1];
+		apc_c0_fmin = apcs_mux_c0_clk.clkr.hw.init->rate_max[1];
+
+		oppfmax = dev_pm_opp_find_freq_exact(get_cpu_device(c0),
+			apc_c0_fmax, true);
+		oppfmin = dev_pm_opp_find_freq_exact(get_cpu_device(c0),
+			apc_c0_fmin, true);
+
+		pr_info("Clock_cpu:(cpu %d) OPP voltage for %lu: %ld\n", c0,
+			 apc_c0_fmin, dev_pm_opp_get_voltage(oppfmin));
+		pr_info("Clock_cpu:(cpu %d) OPP voltage for %lu: %ld\n", c0,
+			 apc_c0_fmax, dev_pm_opp_get_voltage(oppfmax));
+	}
 }
 
-static void cpucc_clk_populate_opp_table(struct platform_device *pdev)
+static void cpucc_clk_populate_opp_table(struct platform_device *pdev,
+		bool is_sdm439)
 {
-	unsigned long apc_c1_fmax;
+	unsigned long apc_c1_fmax, apc_c0_fmax;
-	u32 max_index = apcs_mux_c1_clk.clkr.hw.init->num_rate_max;
+	u32 max_index;
-	int cpu, sdm_cpu = 0;
+	int cpu, sdm_cpu0 = 0, sdm_cpu1 = 0;
 
+	if (is_sdm439) {
+		max_index = apcs_mux_c0_clk.clkr.hw.init->num_rate_max;
+		apc_c0_fmax =
+			apcs_mux_c0_clk.clkr.hw.init->rate_max[max_index - 1];
+	}
+
+	max_index = apcs_mux_c1_clk.clkr.hw.init->num_rate_max;
 	apc_c1_fmax = apcs_mux_c1_clk.clkr.hw.init->rate_max[max_index - 1];
 
 	for_each_possible_cpu(cpu) {
-		sdm_cpu = cpu;
+		if (cpu/4 == 0) {
-		WARN(cpucc_clk_add_opp(&apcs_mux_c1_clk.clkr.hw,
+			sdm_cpu1 = cpu;
-		 get_cpu_device(cpu), apc_c1_fmax),
+			WARN(cpucc_clk_add_opp(&apcs_mux_c1_clk.clkr.hw,
-		  "Failed to add OPP levels for apcs_mux_c1_clk\n");
+			get_cpu_device(cpu), apc_c1_fmax),
+			"Failed to add OPP levels for apcs_mux_c1_clk\n");
+		} else if (cpu/4 == 1 && is_sdm439) {
+			sdm_cpu0 = cpu;
+			WARN(cpucc_clk_add_opp(&apcs_mux_c0_clk.clkr.hw,
+			get_cpu_device(cpu), apc_c0_fmax),
+			"Failed to add OPP levels for apcs_mux_c0_clk\n");
+		}
 	}
-	cpucc_clk_print_opp_table(sdm_cpu);
+	cpucc_clk_print_opp_table(sdm_cpu0, sdm_cpu1, is_sdm439);
 }
 
 static int clock_sdm429_pm_event(struct notifier_block *this,
@@ -620,6 +715,32 @@ static struct notifier_block clock_sdm429_pm_notifier = {
 	.notifier_call = clock_sdm429_pm_event,
 };
 
+static int clock_sdm439_pm_event(struct notifier_block *this,
+				unsigned long event, void *ptr)
+{
+	switch (event) {
+	case PM_POST_HIBERNATION:
+	case PM_POST_SUSPEND:
+		clk_unprepare(apcs_mux_c0_clk.clkr.hw.clk);
+		clk_unprepare(apcs_mux_c1_clk.clkr.hw.clk);
+		clk_unprepare(apcs_mux_cci_clk.clkr.hw.clk);
+		break;
+	case PM_HIBERNATION_PREPARE:
+	case PM_SUSPEND_PREPARE:
+		clk_prepare(apcs_mux_c0_clk.clkr.hw.clk);
+		clk_prepare(apcs_mux_c1_clk.clkr.hw.clk);
+		clk_prepare(apcs_mux_cci_clk.clkr.hw.clk);
+		break;
+	default:
+		break;
+	}
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block clock_sdm439_pm_notifier = {
+	.notifier_call = clock_sdm439_pm_event,
+};
+
 static int clock_qm215_pm_event(struct notifier_block *this,
 				unsigned long event, void *ptr)
 {
@@ -642,6 +763,126 @@ static struct notifier_block clock_qm215_pm_notifier = {
 	.notifier_call = clock_qm215_pm_event,
 };
 
+static int fixup_for_sdm439(struct platform_device *pdev, int speed_bin,
+		int version)
+{
+	struct resource *res;
+	void __iomem *base;
+	struct device *dev = &pdev->dev;
+	char prop_name[] = "qcom,speedX-bin-vX-XXX";
+	int ret;
+
+	 /* Rail Regulator for apcs_pll0 */
+	vdd_sr2_pll.regulator[0] = devm_regulator_get(&pdev->dev,
+			"vdd_sr2_pll");
+	if (IS_ERR(vdd_sr2_pll.regulator[0])) {
+		if (!(PTR_ERR(vdd_sr2_pll.regulator[0]) ==
+			-EPROBE_DEFER))
+			dev_err(&pdev->dev,
+				"Unable to get sr2_pll regulator\n");
+		return PTR_ERR(vdd_sr2_pll.regulator[0]);
+	}
+
+	vdd_sr2_pll.regulator[1] = devm_regulator_get(&pdev->dev,
+			"vdd_sr2_dig_ao");
+	if (IS_ERR(vdd_sr2_pll.regulator[1])) {
+		if (!(PTR_ERR(vdd_sr2_pll.regulator[1]) ==
+			-EPROBE_DEFER))
+			dev_err(&pdev->dev,
+				"Unable to get dig_ao regulator\n");
+		return PTR_ERR(vdd_sr2_pll.regulator[1]);
+	}
+
+	/* Rail Regulator for APCS C0 mux */
+	vdd_cpu_c0.regulator[0] = devm_regulator_get(&pdev->dev,
+			"cpu-vdd");
+	if (IS_ERR(vdd_cpu_c0.regulator[0])) {
+		if (!(PTR_ERR(vdd_cpu_c0.regulator[0]) ==
+					-EPROBE_DEFER))
+			dev_err(&pdev->dev, "Unable to get C0 cpu-vdd regulator\n");
+		return PTR_ERR(vdd_cpu_c0.regulator[0]);
+	}
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+			"apcs_pll0");
+	if (res == NULL) {
+		dev_err(&pdev->dev, "Failed to get apcs_pll0 resources\n");
+		return -EINVAL;
+	}
+
+	base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(base)) {
+		dev_err(&pdev->dev, "Failed map apcs_cpu_pll0 register base\n");
+		return PTR_ERR(base);
+	}
+
+	cpu_regmap_config.name = "apcs_pll0";
+	apcs_cpu_pll0.clkr.regmap = devm_regmap_init_mmio(dev, base,
+						&cpu_regmap_config);
+	if (IS_ERR(apcs_cpu_pll0.clkr.regmap)) {
+		dev_err(&pdev->dev, "Couldn't get regmap for apcs_cpu_pll0\n");
+		return PTR_ERR(apcs_cpu_pll0.clkr.regmap);
+	}
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+		 "apcs-c0-rcg-base");
+	if (res == NULL) {
+		dev_err(&pdev->dev, "Failed to get apcs-c0 resources\n");
+		return -EINVAL;
+	}
+
+	base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(base)) {
+		dev_err(&pdev->dev, "Failed map apcs-c0-rcg register base\n");
+		return PTR_ERR(base);
+	}
+
+	cpu_regmap_config.name = "apcs-c0-rcg-base";
+	apcs_mux_c0_clk.clkr.regmap = devm_regmap_init_mmio(dev, base,
+						&cpu_regmap_config);
+	if (IS_ERR(apcs_mux_c0_clk.clkr.regmap)) {
+		dev_err(&pdev->dev, "Couldn't get regmap for apcs-c0-rcg\n");
+		return PTR_ERR(apcs_mux_c0_clk.clkr.regmap);
+	}
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+		"spm_c0_base");
+	if (res == NULL) {
+		dev_err(&pdev->dev, "Failed to get spm-c0 resources\n");
+		return -EINVAL;
+	}
+
+	base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(base)) {
+		dev_err(&pdev->dev, "Failed to ioremap c0 spm registers\n");
+		return -ENOMEM;
+	}
+	apcs_cpu_pll0.spm_ctrl.spm_base = base;
+
+	snprintf(prop_name, ARRAY_SIZE(prop_name),
+		"qcom,speed%d-bin-v%d-%s", speed_bin, version, "c0");
+
+	ret = cpucc_clk_get_fmax_vdd_class(pdev,
+		(struct clk_init_data *)apcs_mux_c0_clk.clkr.hw.init,
+			 prop_name);
+	if (ret) {
+		dev_err(&pdev->dev, "Didn't get c0 speed bin\n");
+
+		snprintf(prop_name, ARRAY_SIZE(prop_name),
+				"qcom,speed0-bin-v0-%s", "c0");
+		ret = cpucc_clk_get_fmax_vdd_class(pdev,
+			(struct clk_init_data *)
+			apcs_mux_c0_clk.clkr.hw.init,
+				prop_name);
+		if (ret) {
+			dev_err(&pdev->dev,
+				"Unable to load safe voltage plan for c0\n");
+			return ret;
+		}
+	}
+	return 0;
+}
+
 static int cpucc_driver_probe(struct platform_device *pdev)
 {
 	struct resource *res;
@@ -651,7 +892,10 @@ static int cpucc_driver_probe(struct platform_device *pdev)
 	int i, ret, speed_bin, version, cpu;
 	char prop_name[] = "qcom,speedX-bin-vX-XXX";
 	void __iomem *base;
-	bool is_sdm429, is_qm215;
+	bool is_sdm439, is_sdm429, is_qm215;
+
+	is_sdm439 = of_device_is_compatible(pdev->dev.of_node,
+						"qcom,cpu-clock-sdm439");
 
 	is_sdm429 = of_device_is_compatible(pdev->dev.of_node,
 						"qcom,cpu-clock-sdm429");
@@ -702,7 +946,7 @@ static int cpucc_driver_probe(struct platform_device *pdev)
 	}
 
 	/* Rail Regulator for APCS CCI mux */
-	if (is_sdm429) {
+	if (is_sdm429 || is_sdm439) {
 		vdd_cpu_cci.regulator[0] =
 			devm_regulator_get(&pdev->dev, "cpu-vdd");
 		if (IS_ERR(vdd_cpu_cci.regulator[0])) {
@@ -714,26 +958,40 @@ static int cpucc_driver_probe(struct platform_device *pdev)
 		}
 	}
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apcs_pll");
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apcs_pll1");
 	if (res == NULL) {
-		dev_err(&pdev->dev, "Failed to get apcs_pll resources\n");
+		dev_err(&pdev->dev, "Failed to get apcs_pll1 resources\n");
 		return -EINVAL;
 	}
 
 	base = devm_ioremap_resource(dev, res);
 	if (IS_ERR(base)) {
-		dev_err(&pdev->dev, "Failed map apcs_cpu_pll register base\n");
+		dev_err(&pdev->dev, "Failed map apcs_cpu_pll1 register base\n");
 		return PTR_ERR(base);
 	}
 
-	cpu_regmap_config.name = "apcs_pll";
+	cpu_regmap_config.name = "apcs_pll1";
-	apcs_cpu_pll.clkr.regmap = devm_regmap_init_mmio(dev, base,
+	apcs_cpu_pll1.clkr.regmap = devm_regmap_init_mmio(dev, base,
 							&cpu_regmap_config);
-	if (IS_ERR(apcs_cpu_pll.clkr.regmap)) {
+	if (IS_ERR(apcs_cpu_pll1.clkr.regmap)) {
-		dev_err(&pdev->dev, "Couldn't get regmap for apcs_cpu_pll\n");
+		dev_err(&pdev->dev, "Couldn't get regmap for apcs_cpu_pll1\n");
-		return PTR_ERR(apcs_cpu_pll.clkr.regmap);
+		return PTR_ERR(apcs_cpu_pll1.clkr.regmap);
 	}
 
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+		"spm_c1_base");
+	if (res == NULL) {
+		dev_err(&pdev->dev, "Failed to get spm-c1 resources\n");
+		return -EINVAL;
+	}
+
+	base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(base)) {
+		dev_err(&pdev->dev, "Failed to ioremap c1 spm registers\n");
+		return -ENOMEM;
+	}
+	apcs_cpu_pll1.spm_ctrl.spm_base = base;
+
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 			 "apcs-c1-rcg-base");
 	if (res == NULL) {
@@ -755,7 +1013,7 @@ static int cpucc_driver_probe(struct platform_device *pdev)
 		return PTR_ERR(apcs_mux_c1_clk.clkr.regmap);
 	}
 
-	if (is_sdm429) {
+	if (is_sdm429 || is_sdm439) {
 		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 				 "apcs-cci-rcg-base");
 		if (res == NULL) {
@@ -776,21 +1034,6 @@ static int cpucc_driver_probe(struct platform_device *pdev)
 			dev_err(&pdev->dev, "Couldn't get regmap for apcs-cci-rcg\n");
 			return PTR_ERR(apcs_mux_cci_clk.clkr.regmap);
 		}
-
-		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-				"spm_c1_base");
-		if (res == NULL) {
-			dev_err(&pdev->dev, "Failed to get spm-c1 resources\n");
-			return -EINVAL;
-		}
-
-		base = devm_ioremap_resource(dev, res);
-		if (IS_ERR(base)) {
-			dev_err(&pdev->dev, "Failed to ioremap c1 spm registers\n");
-			return -ENOMEM;
-		}
-
-		apcs_pll_spm.spm_base = base;
 	}
 
 	/* Get speed bin information */
@@ -804,17 +1047,21 @@ static int cpucc_driver_probe(struct platform_device *pdev)
 				 prop_name);
 	if (ret) {
 		dev_err(&pdev->dev, "Didn't get c1 speed bin\n");
+
+		snprintf(prop_name, ARRAY_SIZE(prop_name),
+				"qcom,speed0-bin-v0-%s", "c1");
 		ret = cpucc_clk_get_fmax_vdd_class(pdev,
 				(struct clk_init_data *)
 				apcs_mux_c1_clk.clkr.hw.init,
 					prop_name);
 		if (ret) {
-			dev_err(&pdev->dev, "Unable to get vdd class for c1\n");
+			dev_err(&pdev->dev,
+				"Unable to load safe voltage plan for c1\n");
 			return ret;
 		}
 	}
 
-	if (is_sdm429) {
+	if (is_sdm429 || is_sdm439) {
 		snprintf(prop_name, ARRAY_SIZE(prop_name),
 			"qcom,speed%d-bin-v%d-%s", speed_bin, version, "cci");
 
@@ -823,17 +1070,29 @@ static int cpucc_driver_probe(struct platform_device *pdev)
 				 prop_name);
 		if (ret) {
 			dev_err(&pdev->dev, "Didn't get cci speed bin\n");
+
+			snprintf(prop_name, ARRAY_SIZE(prop_name),
+				"qcom,speed0-bin-v0-%s", "cci");
 			ret = cpucc_clk_get_fmax_vdd_class(pdev,
 				(struct clk_init_data *)
 				apcs_mux_cci_clk.clkr.hw.init,
 					prop_name);
 			if (ret) {
-				dev_err(&pdev->dev, "Unable get vdd class for cci\n");
+				dev_err(&pdev->dev,
+					"Unable to load safe voltage plan for cci\n");
 				return ret;
 			}
 		}
 	}
 
+	if (is_sdm439) {
+		ret = fixup_for_sdm439(pdev, speed_bin, version);
+		if (ret) {
+			dev_err(&pdev->dev, "Unable get sdm439 clocks\n");
+			return ret;
+		}
+	}
+
 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 	if (!data)
 		return -ENOMEM;
@@ -864,6 +1123,19 @@ static int cpucc_driver_probe(struct platform_device *pdev)
 			}
 			data->hws[i] = cpu_clks_hws_qm215[i];
 		}
+	} else if (is_sdm439) {
+		data->num = ARRAY_SIZE(cpu_clks_hws_sdm439);
+
+		for (i = 0; i < ARRAY_SIZE(cpu_clks_hws_sdm439); i++) {
+			ret = devm_clk_hw_register(dev,
+					cpu_clks_hws_sdm439[i]);
+			if (ret) {
+				dev_err(&pdev->dev,
+					"Failed to register clock\n");
+				return ret;
+			}
+			data->hws[i] = cpu_clks_hws_sdm439[i];
+		}
 	}
 
 	ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, data);
@@ -873,6 +1145,23 @@ static int cpucc_driver_probe(struct platform_device *pdev)
 	}
 
 	/* For safe freq switching during rate change */
+	if (is_sdm439) {
+		apcs_mux_c0_clk.clk_lpm.hw_low_power_ctrl = true;
+		ret = clk_notifier_register(apcs_mux_c0_clk.clkr.hw.clk,
+						&apcs_mux_c0_clk.clk_nb);
+		if (ret) {
+			dev_err(dev, "failed to register clock notifier: %d\n",
+					ret);
+			return ret;
+		}
+		ret = clk_prepare_enable(apcs_cpu_pll0.clkr.hw.clk);
+		if (ret) {
+			dev_err(dev, "failed to Enable PLL0 clock: %d\n", ret);
+			return ret;
+		}
+	}
+
+	apcs_mux_c1_clk.clk_lpm.hw_low_power_ctrl = true;
 	ret = clk_notifier_register(apcs_mux_c1_clk.clkr.hw.clk,
 						&apcs_mux_c1_clk.clk_nb);
 	if (ret) {
@@ -880,25 +1169,41 @@ static int cpucc_driver_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	ret = clk_prepare_enable(apcs_cpu_pll1.clkr.hw.clk);
+	if (ret) {
+		dev_err(dev, "failed to Enable PLL1 clock: %d\n", ret);
+		return ret;
+	}
+
 	/*
 	 * To increase the enable count for the clocks so
 	 * that they dont get disabled during late init.
 	 */
 	get_online_cpus();
 	for_each_online_cpu(cpu) {
-		WARN(clk_prepare_enable(apcs_mux_c1_clk.clkr.hw.clk),
+		if (!(cpu/4)) {
-			"Unable to turn on CPU clock\n");
+			WARN(clk_prepare_enable(apcs_mux_c1_clk.clkr.hw.clk),
-		if (is_sdm429)
+				"Unable to turn on CPU clock\n");
+		}
+
+		if (cpu/4 && is_sdm439) {
+			WARN(clk_prepare_enable(apcs_mux_c0_clk.clkr.hw.clk),
+				"Unable to turn on CPU clock\n");
+		}
+
+		if (is_sdm429 || is_sdm439)
 			clk_prepare_enable(apcs_mux_cci_clk.clkr.hw.clk);
 	}
 	put_online_cpus();
 
-	if (is_sdm429)
+	if (is_sdm439)
+		register_pm_notifier(&clock_sdm439_pm_notifier);
+	else if (is_sdm429)
 		register_pm_notifier(&clock_sdm429_pm_notifier);
 	else if (is_qm215)
 		register_pm_notifier(&clock_qm215_pm_notifier);
 
-	cpucc_clk_populate_opp_table(pdev);
+	cpucc_clk_populate_opp_table(pdev, is_sdm439);
 	dev_info(dev, "CPU clock Driver probed successfully\n");
 
 	return ret;
@@ -925,20 +1230,42 @@ static void __exit cpu_clk_exit(void)
 module_exit(cpu_clk_exit);
 
 #define REG_OFFSET	0x4
-#define APCS_PLL	0x0b016000
+#define APCS_PLL0	0x0b116000
+#define APCS_PLL1	0x0b016000
+#define A53SS_MUX_C0	0x0b111050
 #define A53SS_MUX_C1	0x0b011050
 
+static void config_enable_sr2_pll(void __iomem *base)
+{
+	/* Configure L/M/N values */
+	writel_relaxed(0x34, base + apcs_cpu_pll0.l_reg);
+	writel_relaxed(0x0, base + apcs_cpu_pll0.m_reg);
+	writel_relaxed(0x1, base + apcs_cpu_pll0.n_reg);
+
+	/* Configure USER_CTL value */
+	writel_relaxed(0xf, base + apcs_cpu_pll0.config_reg);
+
+	/* Enable the pll */
+	writel_relaxed(0x2, base + apcs_cpu_pll0.mode_reg);
+	udelay(2);
+	writel_relaxed(0x6, base + apcs_cpu_pll0.mode_reg);
+	udelay(50);
+	writel_relaxed(0x7, base + apcs_cpu_pll0.mode_reg);
+	/* Ensure that the writes go through before enabling PLL */
+	mb();
+}
+
 static void config_enable_hf_pll(void __iomem *base)
 {
 	/* Configure USER_CTL value */
-	writel_relaxed(0xf, base + apcs_cpu_pll.config_reg);
+	writel_relaxed(0xf, base + apcs_cpu_pll1.config_reg);
 
 	/* Enable the pll */
-	writel_relaxed(0x2, base + apcs_cpu_pll.mode_reg);
+	writel_relaxed(0x2, base + apcs_cpu_pll1.mode_reg);
 	udelay(2);
-	writel_relaxed(0x6, base + apcs_cpu_pll.mode_reg);
+	writel_relaxed(0x6, base + apcs_cpu_pll1.mode_reg);
 	udelay(50);
-	writel_relaxed(0x7, base + apcs_cpu_pll.mode_reg);
+	writel_relaxed(0x7, base + apcs_cpu_pll1.mode_reg);
 	/* Ensure that the writes go through before enabling PLL */
 	mb();
 }
@@ -948,9 +1275,16 @@ static int __init cpu_clock_init(void)
 	struct device_node *dev;
 	void __iomem  *base;
 	int count, regval = 0;
+	bool is_sdm439 = false;
 	unsigned long enable_mask = GENMASK(2, 0);
+	dev = of_find_compatible_node(NULL, NULL, "qcom,cpu-clock-sdm439");
 
-	dev = of_find_compatible_node(NULL, NULL, "qcom,cpu-clock-sdm429");
+	if (dev)
+		is_sdm439 = true;
+
+	if (!dev)
+		dev = of_find_compatible_node(NULL, NULL,
+				"qcom,cpu-clock-sdm429");
 
 	if (!dev)
 		dev = of_find_compatible_node(NULL, NULL,
@@ -960,7 +1294,19 @@ static int __init cpu_clock_init(void)
 		return -ENOMEM;
 	}
 
-	base = ioremap_nocache(APCS_PLL, SZ_64);
+	if (is_sdm439) {
+		base = ioremap_nocache(APCS_PLL0, SZ_64);
+		if (!base)
+			return -ENOMEM;
+
+		regval = readl_relaxed(base);
+		if (!((regval & enable_mask) == enable_mask))
+			config_enable_sr2_pll(base);
+
+		iounmap(base);
+	}
+
+	base = ioremap_nocache(APCS_PLL1, SZ_64);
 	if (!base)
 		return -ENOMEM;
 
@@ -1000,10 +1346,54 @@ static int __init cpu_clock_init(void)
 		udelay(1);
 	}
 
+	iounmap(base);
 	return 0;
 }
 early_initcall(cpu_clock_init);
 
+static int __init clock_cpu_lpm_get_latency(void)
+{
+	int rc;
+	bool is_sdm439 = false;
+	struct device_node *ofnode = of_find_compatible_node(NULL, NULL,
+					"qcom,cpu-clock-sdm439");
+	if (ofnode)
+		is_sdm439 = true;
+
+	if (!ofnode)
+		ofnode = of_find_compatible_node(NULL, NULL,
+				"qcom,cpu-clock-sdm429");
+
+	if (!ofnode)
+		ofnode = of_find_compatible_node(NULL, NULL,
+				"qcom,cpu-clock-qm215");
+
+	if (!ofnode) {
+		pr_err("device node not initialized\n");
+		return -ENOMEM;
+	}
+
+	rc = lpm_get_latency(&apcs_mux_c1_clk.clk_lpm.latency_lvl,
+			&apcs_mux_c1_clk.clk_lpm.cpu_latency_no_l2_pc_us);
+	if (rc < 0)
+		pr_err("Failed to get the L2 PC value for perf\n");
+
+	if (is_sdm439) {
+		rc = lpm_get_latency(&apcs_mux_c0_clk.clk_lpm.latency_lvl,
+			&apcs_mux_c0_clk.clk_lpm.cpu_latency_no_l2_pc_us);
+		if (rc < 0)
+			pr_err("Failed to get the L2 PC value for pwr\n");
+		pr_debug("Latency for pwr cluster : %d\n",
+			apcs_mux_c0_clk.clk_lpm.cpu_latency_no_l2_pc_us);
+	}
+
+	pr_debug("Latency for perf cluster : %d\n",
+		apcs_mux_c1_clk.clk_lpm.cpu_latency_no_l2_pc_us);
+
+	return rc;
+}
+late_initcall_sync(clock_cpu_lpm_get_latency);
+
 MODULE_ALIAS("platform:cpu");
 MODULE_DESCRIPTION("SDM CPU clock Driver");
 MODULE_LICENSE("GPL v2");

drivers/clk/qcom/clk-pll.c

@@ -29,6 +29,44 @@
 #define PLL_BYPASSNL		BIT(1)
 #define PLL_RESET_N		BIT(2)
 
+static void spm_event(void __iomem *base, u32 offset, u32 bit, bool enable)
+{
+	uint32_t val;
+
+	if (!base)
+		return;
+
+	if (enable) {
+		/* L2_SPM_FORCE_EVENT_EN */
+		val = readl_relaxed(base + offset);
+		val |= BIT(bit);
+		writel_relaxed(val, (base + offset));
+		/* Ensure that the write above goes through. */
+		mb();
+
+		/* L2_SPM_FORCE_EVENT */
+		val = readl_relaxed(base + offset + 0x4);
+		val |= BIT(bit);
+		writel_relaxed(val, (base + offset + 0x4));
+		/* Ensure that the write above goes through. */
+		mb();
+	} else {
+		/* L2_SPM_FORCE_EVENT */
+		val = readl_relaxed(base + offset + 0x4);
+		val &= ~BIT(bit);
+		writel_relaxed(val, (base + offset + 0x4));
+		/* Ensure that the write above goes through. */
+		mb();
+
+		/* L2_SPM_FORCE_EVENT_EN */
+		val = readl_relaxed(base + offset);
+		val &= ~BIT(bit);
+		writel_relaxed(val, (base + offset));
+		/* Ensure that the write above goes through. */
+		mb();
+	}
+}
+
 static int clk_pll_enable(struct clk_hw *hw)
 {
 	struct clk_pll *pll = to_clk_pll(hw);
@@ -76,6 +114,9 @@ static void clk_pll_disable(struct clk_hw *hw)
 	u32 mask;
 	u32 val;
 
+	spm_event(pll->spm_ctrl.spm_base, pll->spm_ctrl.offset,
+			pll->spm_ctrl.event_bit, true);
+
 	regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
 	/* Skip if in FSM mode */
 	if (val & PLL_VOTE_FSM_ENA)
@@ -138,7 +179,8 @@ clk_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
 
 	f = find_freq(pll->freq_tbl, req->rate);
 	if (!f)
-		req->rate = clk_pll_recalc_rate(hw, req->best_parent_rate);
+		req->rate = DIV_ROUND_UP_ULL(req->rate, req->best_parent_rate)
+			* req->best_parent_rate;
 	else
 		req->rate = f->freq;
 
@@ -175,12 +217,38 @@ clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long p_rate)
 	return 0;
 }
 
+static void clk_pll_list_registers(struct seq_file *f, struct clk_hw *hw)
+{
+	struct clk_pll *pll = to_clk_pll(hw);
+	int size, i, val;
+
+	static struct clk_register_data data[] = {
+		{"PLL_MODE", 0x0},
+		{"PLL_L_VAL", 0x4},
+		{"PLL_M_VAL", 0x8},
+		{"PLL_N_VAL", 0xC},
+		{"PLL_USER_CTL", 0x10},
+		{"PLL_CONFIG_CTL", 0x14},
+		{"PLL_STATUS_CTL", 0x1C},
+	};
+
+	size = ARRAY_SIZE(data);
+
+	for (i = 0; i < size; i++) {
+		regmap_read(pll->clkr.regmap, pll->mode_reg + data[i].offset,
+									&val);
+		clock_debug_output(f, false,
+				"%20s: 0x%.8x\n", data[i].name, val);
+	}
+}
+
 const struct clk_ops clk_pll_ops = {
 	.enable = clk_pll_enable,
 	.disable = clk_pll_disable,
 	.recalc_rate = clk_pll_recalc_rate,
 	.determine_rate = clk_pll_determine_rate,
 	.set_rate = clk_pll_set_rate,
+	.list_registers = clk_pll_list_registers,
 };
 EXPORT_SYMBOL_GPL(clk_pll_ops);
 
@@ -192,7 +260,7 @@ static int wait_for_pll(struct clk_pll *pll)
 	const char *name = clk_hw_get_name(&pll->clkr.hw);
 
 	/* Wait for pll to enable. */
-	for (count = 200; count > 0; count--) {
+	for (count = 500; count > 0; count--) {
 		ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val);
 		if (ret)
 			return ret;
@@ -201,7 +269,8 @@ static int wait_for_pll(struct clk_pll *pll)
 		udelay(1);
 	}
 
-	WARN(1, "%s didn't enable after voting for it!\n", name);
+	WARN_CLK(pll->clkr.hw.core, name, 1,
+			"didn't enable after voting for it!\n");
 	return -ETIMEDOUT;
 }
 
@@ -274,6 +343,9 @@ static int clk_pll_sr2_enable(struct clk_hw *hw)
 	int ret;
 	u32 mode;
 
+	spm_event(pll->spm_ctrl.spm_base, pll->spm_ctrl.offset,
+			pll->spm_ctrl.event_bit, false);
+
 	ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
 	if (ret)
 		return ret;
@@ -296,6 +368,10 @@ static int clk_pll_sr2_enable(struct clk_hw *hw)
 	if (ret)
 		return ret;
 
+	/* Make sure De-assert active-low PLL reset request goes through */
+	mb();
+	udelay(50);
+
 	ret = wait_for_pll(pll);
 	if (ret)
 		return ret;

drivers/clk/qcom/clk-pll.h

@@ -32,6 +32,12 @@ struct pll_freq_tbl {
 	u32 ibits;
 };
 
+struct pll_spm_ctrl {
+	u32 offset;
+	u32 event_bit;
+	void __iomem *spm_base;
+};
+
 /**
  * struct clk_pll - phase locked loop (PLL)
  * @l_reg: L register
@@ -58,6 +64,7 @@ struct clk_pll {
 	const struct pll_freq_tbl *freq_tbl;
 
 	struct clk_regmap clkr;
+	struct pll_spm_ctrl spm_ctrl;
 };
 
 extern const struct clk_ops clk_pll_ops;

drivers/clk/qcom/clk-rcg2.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (c) 2013, 2018-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013, 2018-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/kernel.h>
@@ -1395,7 +1395,19 @@ static int clk_gfx3d_src_set_rate_and_parent(struct clk_hw *hw,
 	if (ret)
 		return ret;
 
-	return update_config(rcg, old_cfg);
+	if ((!clk_rcg2_is_force_enabled(hw) && (!clk_hw_is_prepared(hw)
+		|| !clk_hw_is_enabled(hw))))
+		clk_rcg2_set_force_enable(hw);
+
+	ret = update_config(rcg, old_cfg);
+	if (ret)
+		return ret;
+
+	if ((clk_rcg2_is_force_enabled(hw) && (!clk_hw_is_prepared(hw)
+		|| !clk_hw_is_enabled(hw))))
+		clk_rcg2_clear_force_enable(hw);
+
+	return ret;
 }
 
 static int clk_gfx3d_src_determine_rate(struct clk_hw *hw,

drivers/clk/qcom/clk-regmap-mux-div.c

@@ -51,7 +51,8 @@ int mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div)
 		udelay(1);
 	}
 
-	pr_err("%s: RCG did not update its configuration", name);
+	WARN_CLK(md->clkr.hw.core, name, 1,
+			"%s: rcg didn't update its configuration.", name);
 	return -EBUSY;
 }
 EXPORT_SYMBOL_GPL(mux_div_set_src_div);

drivers/clk/qcom/clk-regmap-mux-div.h

@@ -8,9 +8,28 @@
 #define __QCOM_CLK_REGMAP_MUX_DIV_H__
 
 #include <linux/clk-provider.h>
+#include <linux/pm_qos.h>
+#include <soc/qcom/pm.h>
 #include "common.h"
 #include "clk-regmap.h"
 
+/**
+ * struct clk_regmap_mux_div_lpm - regmap_mux_div_lpm clock
+ * @cpu_reg_mask: logical cpu mask for node
+ * @hw_low_power_ctrl: hw low power control
+ * @req:  pm_qos request
+ * @latency_lvl: lpm latency level
+ * @cpu_latency_no_l2_pc_us:  cpu latency in ms
+ */
+
+struct clk_regmap_mux_div_lpm {
+	cpumask_t cpu_reg_mask;
+	bool hw_low_power_ctrl;
+	struct pm_qos_request req;
+	struct latency_level latency_lvl;
+	s32 cpu_latency_no_l2_pc_us;
+};
+
 /**
  * struct mux_div_clk - combined mux/divider clock
  * @reg_offset: offset of the mux/divider register
@@ -52,6 +71,9 @@ struct clk_regmap_mux_div {
 	struct clk_regmap		clkr;
 	struct clk			*pclk;
 	struct notifier_block		clk_nb;
+
+	/* LPM Latency related */
+	struct clk_regmap_mux_div_lpm	clk_lpm;
 };
 
 extern const struct clk_ops clk_regmap_mux_div_ops;

drivers/clk/qcom/clk-smd-rpm.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Linaro Limited
- * Copyright (c) 2014, 2016-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014, 2016-2021, The Linux Foundation. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -1190,6 +1190,7 @@ static const struct of_device_id rpm_smd_clk_match_table[] = {
 	{ .compatible = "qcom,rpmcc-scuba", .data = &rpm_clk_scuba},
 	{ .compatible = "qcom,rpmcc-sdm660",  .data = &rpm_clk_sdm660  },
 	{ .compatible = "qcom,rpmcc-qm215",  .data = &rpm_clk_qm215 },
+	{ .compatible = "qcom,rpmcc-sdm439",  .data = &rpm_clk_qm215 },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
@@ -1200,7 +1201,7 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
 	struct clk *clk;
 	struct rpm_cc *rcc;
 	struct clk_onecell_data *data;
-	int ret, is_bengal, is_scuba, is_sdm660, is_qm215;
+	int ret, is_bengal, is_scuba, is_sdm660, is_qm215, is_sdm439;
 	size_t num_clks, i;
 	struct clk_hw **hw_clks;
 	const struct rpm_smd_clk_desc *desc;
@@ -1222,13 +1223,16 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
 	is_qm215 = of_device_is_compatible(pdev->dev.of_node,
 						"qcom,rpmcc-qm215");
 
+	is_sdm439 = of_device_is_compatible(pdev->dev.of_node,
+						"qcom,rpmcc-sdm439");
+
 	if (is_sdm660) {
 		ret = clk_vote_bimc(&sdm660_bimc_clk.hw, INT_MAX);
 		if (ret < 0)
 			return ret;
 	}
 
-	if (is_qm215) {
+	if (is_qm215 || is_sdm439) {
 		ret = clk_vote_bimc(&sdm429w_bimc_clk.hw, INT_MAX);
 		if (ret < 0)
 			return ret;
@@ -1251,6 +1255,11 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
 	data->clks = clks;
 	data->clk_num = num_clks;
 
+	if (is_sdm439) {
+		rpm_clk_qm215.clks[RPM_SMD_BIMC_GPU_CLK] = NULL;
+		rpm_clk_qm215.clks[RPM_SMD_BIMC_GPU_A_CLK] = NULL;
+	}
+
 	for (i = 0; i <= desc->num_rpm_clks; i++) {
 		if (!hw_clks[i]) {
 			clks[i] = ERR_PTR(-ENOENT);
@@ -1317,7 +1326,7 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
 		/* Hold an active set vote for the cnoc_periph resource */
 		clk_set_rate(cnoc_periph_keepalive_a_clk.hw.clk, 19200000);
 		clk_prepare_enable(cnoc_periph_keepalive_a_clk.hw.clk);
-	} else if (is_qm215) {
+	} else if (is_qm215 || is_sdm439) {
 		clk_prepare_enable(sdm429w_bi_tcxo_ao.hw.clk);
 
 		/*

drivers/clk/qcom/debugcc-khaje.c

@@ -0,0 +1,626 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+#define pr_fmt(fmt) "clk: %s: " fmt, __func__
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+
+#include "clk-debug.h"
+#include "common.h"
+
+static struct measure_clk_data debug_mux_priv = {
+	.ctl_reg = 0x62038,
+	.status_reg = 0x6203C,
+	.xo_div4_cbcr = 0x28008,
+};
+
+static const char *const apss_cc_debug_mux_parent_names[] = {
+	"perfcl_clk",
+	"pwrcl_clk",
+};
+
+static int apss_cc_debug_mux_sels[] = {
+	0x1,		/* perfcl_clk */
+	0x0,		/* pwrclk_clk */
+};
+
+static int apss_cc_debug_mux_pre_divs[] = {
+	0x8,		/* perfcl_clk */
+	0x8,		/* pwrcl_clk */
+};
+
+static struct clk_debug_mux apss_cc_debug_mux = {
+	.priv = &debug_mux_priv,
+	.debug_offset = 0x0,
+	.post_div_offset = 0x0,
+	.cbcr_offset = U32_MAX,
+	.src_sel_mask = 0x3FF00,
+	.src_sel_shift = 8,
+	.post_div_mask = 0xF0000000,
+	.post_div_shift = 28,
+	.post_div_val = 1,
+	.mux_sels = apss_cc_debug_mux_sels,
+	.pre_div_vals = apss_cc_debug_mux_pre_divs,
+	.hw.init = &(struct clk_init_data){
+		.name = "apss_cc_debug_mux",
+		.ops = &clk_debug_mux_ops,
+		.parent_names = apss_cc_debug_mux_parent_names,
+		.num_parents = ARRAY_SIZE(apss_cc_debug_mux_parent_names),
+		.flags = CLK_IS_MEASURE,
+	},
+};
+
+static const char *const disp_cc_debug_mux_parent_names[] = {
+	"disp_cc_mdss_ahb_clk",
+	"disp_cc_mdss_byte0_clk",
+	"disp_cc_mdss_byte0_intf_clk",
+	"disp_cc_mdss_esc0_clk",
+	"disp_cc_mdss_mdp_clk",
+	"disp_cc_mdss_mdp_lut_clk",
+	"disp_cc_mdss_non_gdsc_ahb_clk",
+	"disp_cc_mdss_pclk0_clk",
+	"disp_cc_mdss_rot_clk",
+	"disp_cc_mdss_rscc_ahb_clk",
+	"disp_cc_mdss_rscc_vsync_clk",
+	"disp_cc_mdss_vsync_clk",
+	"measure_only_disp_cc_sleep_clk",
+	"measure_only_disp_cc_xo_clk",
+};
+
+static int disp_cc_debug_mux_sels[] = {
+	0x14,		/* disp_cc_mdss_ahb_clk */
+	0xC,		/* disp_cc_mdss_byte0_clk */
+	0xD,		/* disp_cc_mdss_byte0_intf_clk */
+	0xE,		/* disp_cc_mdss_esc0_clk */
+	0x8,		/* disp_cc_mdss_mdp_clk */
+	0xA,		/* disp_cc_mdss_mdp_lut_clk */
+	0x15,		/* disp_cc_mdss_non_gdsc_ahb_clk */
+	0x7,		/* disp_cc_mdss_pclk0_clk */
+	0x9,		/* disp_cc_mdss_rot_clk */
+	0x17,		/* disp_cc_mdss_rscc_ahb_clk */
+	0x16,		/* disp_cc_mdss_rscc_vsync_clk */
+	0xB,		/* disp_cc_mdss_vsync_clk */
+	0x1D,		/* measure_only_disp_cc_sleep_clk */
+	0x1E,		/* measure_only_disp_cc_xo_clk */
+};
+
+static struct clk_debug_mux disp_cc_debug_mux = {
+	.priv = &debug_mux_priv,
+	.debug_offset = 0x7000,
+	.post_div_offset = 0x3000,
+	.cbcr_offset = 0x3004,
+	.src_sel_mask = 0xFF,
+	.src_sel_shift = 0,
+	.post_div_mask = 0xF,
+	.post_div_shift = 0,
+	.post_div_val = 4,
+	.mux_sels = disp_cc_debug_mux_sels,
+	.hw.init = &(struct clk_init_data){
+		.name = "disp_cc_debug_mux",
+		.ops = &clk_debug_mux_ops,
+		.parent_names = disp_cc_debug_mux_parent_names,
+		.num_parents = ARRAY_SIZE(disp_cc_debug_mux_parent_names),
+		.flags = CLK_IS_MEASURE,
+	},
+};
+
+static const char *const gcc_debug_mux_parent_names[] = {
+	"apss_cc_debug_mux",
+	"disp_cc_debug_mux",
+	"gcc_ahb2phy_csi_clk",
+	"gcc_ahb2phy_usb_clk",
+	"gcc_bimc_gpu_axi_clk",
+	"gcc_boot_rom_ahb_clk",
+	"gcc_cam_throttle_nrt_clk",
+	"gcc_cam_throttle_rt_clk",
+	"gcc_camera_ahb_clk",
+	"gcc_camss_axi_clk",
+	"gcc_camss_cci_0_clk",
+	"gcc_camss_cphy_0_clk",
+	"gcc_camss_cphy_1_clk",
+	"gcc_camss_cphy_2_clk",
+	"gcc_camss_csi0phytimer_clk",
+	"gcc_camss_csi1phytimer_clk",
+	"gcc_camss_csi2phytimer_clk",
+	"gcc_camss_mclk0_clk",
+	"gcc_camss_mclk1_clk",
+	"gcc_camss_mclk2_clk",
+	"gcc_camss_mclk3_clk",
+	"gcc_camss_nrt_axi_clk",
+	"gcc_camss_ope_ahb_clk",
+	"gcc_camss_ope_clk",
+	"gcc_camss_rt_axi_clk",
+	"gcc_camss_tfe_0_clk",
+	"gcc_camss_tfe_0_cphy_rx_clk",
+	"gcc_camss_tfe_0_csid_clk",
+	"gcc_camss_tfe_1_clk",
+	"gcc_camss_tfe_1_cphy_rx_clk",
+	"gcc_camss_tfe_1_csid_clk",
+	"gcc_camss_tfe_2_clk",
+	"gcc_camss_tfe_2_cphy_rx_clk",
+	"gcc_camss_tfe_2_csid_clk",
+	"gcc_camss_top_ahb_clk",
+	"gcc_cfg_noc_usb3_prim_axi_clk",
+	"gcc_disp_ahb_clk",
+	"gcc_disp_gpll0_div_clk_src",
+	"gcc_disp_hf_axi_clk",
+	"gcc_disp_sleep_clk",
+	"gcc_disp_throttle_core_clk",
+	"gcc_gp1_clk",
+	"gcc_gp2_clk",
+	"gcc_gp3_clk",
+	"gcc_gpu_gpll0_clk_src",
+	"gcc_gpu_gpll0_div_clk_src",
+	"gcc_gpu_memnoc_gfx_clk",
+	"gcc_gpu_snoc_dvm_gfx_clk",
+	"gcc_gpu_throttle_core_clk",
+	"gcc_pdm2_clk",
+	"gcc_pdm_ahb_clk",
+	"gcc_pdm_xo4_clk",
+	"gcc_prng_ahb_clk",
+	"gcc_qmip_camera_nrt_ahb_clk",
+	"gcc_qmip_camera_rt_ahb_clk",
+	"gcc_qmip_disp_ahb_clk",
+	"gcc_qmip_gpu_cfg_ahb_clk",
+	"gcc_qmip_video_vcodec_ahb_clk",
+	"gcc_qupv3_wrap0_core_2x_clk",
+	"gcc_qupv3_wrap0_core_clk",
+	"gcc_qupv3_wrap0_s0_clk",
+	"gcc_qupv3_wrap0_s1_clk",
+	"gcc_qupv3_wrap0_s2_clk",
+	"gcc_qupv3_wrap0_s3_clk",
+	"gcc_qupv3_wrap0_s4_clk",
+	"gcc_qupv3_wrap0_s5_clk",
+	"gcc_qupv3_wrap_0_m_ahb_clk",
+	"gcc_qupv3_wrap_0_s_ahb_clk",
+	"gcc_sdcc1_ahb_clk",
+	"gcc_sdcc1_apps_clk",
+	"gcc_sdcc1_ice_core_clk",
+	"gcc_sdcc2_ahb_clk",
+	"gcc_sdcc2_apps_clk",
+	"gcc_sys_noc_cpuss_ahb_clk",
+	"gcc_sys_noc_ufs_phy_axi_clk",
+	"gcc_sys_noc_usb3_prim_axi_clk",
+	"gcc_ufs_phy_ahb_clk",
+	"gcc_ufs_phy_axi_clk",
+	"gcc_ufs_phy_ice_core_clk",
+	"gcc_ufs_phy_phy_aux_clk",
+	"gcc_ufs_phy_rx_symbol_0_clk",
+	"gcc_ufs_phy_rx_symbol_1_clk",
+	"gcc_ufs_phy_tx_symbol_0_clk",
+	"gcc_ufs_phy_unipro_core_clk",
+	"gcc_usb30_prim_master_clk",
+	"gcc_usb30_prim_mock_utmi_clk",
+	"gcc_usb30_prim_sleep_clk",
+	"gcc_usb3_prim_phy_com_aux_clk",
+	"gcc_usb3_prim_phy_pipe_clk",
+	"gcc_vcodec0_axi_clk",
+	"gcc_venus_ahb_clk",
+	"gcc_venus_ctl_axi_clk",
+	"gcc_video_ahb_clk",
+	"gcc_video_axi0_clk",
+	"gcc_video_throttle_core_clk",
+	"gcc_video_vcodec0_sys_clk",
+	"gcc_video_venus_ctl_clk",
+	"gcc_video_xo_clk",
+	"gpu_cc_debug_mux",
+	"mc_cc_debug_mux",
+	"measure_only_cnoc_clk",
+	"measure_only_gcc_camera_xo_clk",
+	"measure_only_gcc_cpuss_gnoc_clk",
+	"measure_only_gcc_disp_xo_clk",
+	"measure_only_gcc_gpu_cfg_ahb_clk",
+	"measure_only_ipa_2x_clk",
+	"measure_only_snoc_clk",
+};
+
+static int gcc_debug_mux_sels[] = {
+	0xB6,		/* apss_cc_debug_mux */
+	0x45,		/* disp_cc_debug_mux */
+	0x6A,		/* gcc_ahb2phy_csi_clk */
+	0x6B,		/* gcc_ahb2phy_usb_clk */
+	0x97,		/* gcc_bimc_gpu_axi_clk */
+	0x7D,		/* gcc_boot_rom_ahb_clk */
+	0x4F,		/* gcc_cam_throttle_nrt_clk */
+	0x4E,		/* gcc_cam_throttle_rt_clk */
+	0x3A,		/* gcc_camera_ahb_clk */
+	0x141,		/* gcc_camss_axi_clk */
+	0x13F,		/* gcc_camss_cci_0_clk */
+	0x130,		/* gcc_camss_cphy_0_clk */
+	0x131,		/* gcc_camss_cphy_1_clk */
+	0x132,		/* gcc_camss_cphy_2_clk */
+	0x122,		/* gcc_camss_csi0phytimer_clk */
+	0x123,		/* gcc_camss_csi1phytimer_clk */
+	0x124,		/* gcc_camss_csi2phytimer_clk */
+	0x125,		/* gcc_camss_mclk0_clk */
+	0x126,		/* gcc_camss_mclk1_clk */
+	0x127,		/* gcc_camss_mclk2_clk */
+	0x128,		/* gcc_camss_mclk3_clk */
+	0x145,		/* gcc_camss_nrt_axi_clk */
+	0x13E,		/* gcc_camss_ope_ahb_clk */
+	0x13C,		/* gcc_camss_ope_clk */
+	0x147,		/* gcc_camss_rt_axi_clk */
+	0x129,		/* gcc_camss_tfe_0_clk */
+	0x12D,		/* gcc_camss_tfe_0_cphy_rx_clk */
+	0x133,		/* gcc_camss_tfe_0_csid_clk */
+	0x12A,		/* gcc_camss_tfe_1_clk */
+	0x12E,		/* gcc_camss_tfe_1_cphy_rx_clk */
+	0x135,		/* gcc_camss_tfe_1_csid_clk */
+	0x12B,		/* gcc_camss_tfe_2_clk */
+	0x12F,		/* gcc_camss_tfe_2_cphy_rx_clk */
+	0x137,		/* gcc_camss_tfe_2_csid_clk */
+	0x140,		/* gcc_camss_top_ahb_clk */
+	0x1E,		/* gcc_cfg_noc_usb3_prim_axi_clk */
+	0x3B,		/* gcc_disp_ahb_clk */
+	0x4A,		/* gcc_disp_gpll0_div_clk_src */
+	0x40,		/* gcc_disp_hf_axi_clk */
+	0x50,		/* gcc_disp_sleep_clk */
+	0x4C,		/* gcc_disp_throttle_core_clk */
+	0xC1,		/* gcc_gp1_clk */
+	0xC2,		/* gcc_gp2_clk */
+	0xC3,		/* gcc_gp3_clk */
+	0xF1,		/* gcc_gpu_gpll0_clk_src */
+	0xF2,		/* gcc_gpu_gpll0_div_clk_src */
+	0xEE,		/* gcc_gpu_memnoc_gfx_clk */
+	0xF0,		/* gcc_gpu_snoc_dvm_gfx_clk */
+	0xF5,		/* gcc_gpu_throttle_core_clk */
+	0x7A,		/* gcc_pdm2_clk */
+	0x78,		/* gcc_pdm_ahb_clk */
+	0x79,		/* gcc_pdm_xo4_clk */
+	0x7B,		/* gcc_prng_ahb_clk */
+	0x3D,		/* gcc_qmip_camera_nrt_ahb_clk */
+	0x4B,		/* gcc_qmip_camera_rt_ahb_clk */
+	0x3E,		/* gcc_qmip_disp_ahb_clk */
+	0xF3,		/* gcc_qmip_gpu_cfg_ahb_clk */
+	0x3C,		/* gcc_qmip_video_vcodec_ahb_clk */
+	0x71,		/* gcc_qupv3_wrap0_core_2x_clk */
+	0x70,		/* gcc_qupv3_wrap0_core_clk */
+	0x72,		/* gcc_qupv3_wrap0_s0_clk */
+	0x73,		/* gcc_qupv3_wrap0_s1_clk */
+	0x74,		/* gcc_qupv3_wrap0_s2_clk */
+	0x75,		/* gcc_qupv3_wrap0_s3_clk */
+	0x76,		/* gcc_qupv3_wrap0_s4_clk */
+	0x77,		/* gcc_qupv3_wrap0_s5_clk */
+	0x6E,		/* gcc_qupv3_wrap_0_m_ahb_clk */
+	0x6F,		/* gcc_qupv3_wrap_0_s_ahb_clk */
+	0xF9,		/* gcc_sdcc1_ahb_clk */
+	0xF8,		/* gcc_sdcc1_apps_clk */
+	0xFA,		/* gcc_sdcc1_ice_core_clk */
+	0x6D,		/* gcc_sdcc2_ahb_clk */
+	0x6C,		/* gcc_sdcc2_apps_clk */
+	0x9,		/* gcc_sys_noc_cpuss_ahb_clk */
+	0x19,		/* gcc_sys_noc_ufs_phy_axi_clk */
+	0x18,		/* gcc_sys_noc_usb3_prim_axi_clk */
+	0x117,		/* gcc_ufs_phy_ahb_clk */
+	0x116,		/* gcc_ufs_phy_axi_clk */
+	0x11D,		/* gcc_ufs_phy_ice_core_clk */
+	0x11E,		/* gcc_ufs_phy_phy_aux_clk */
+	0x119,		/* gcc_ufs_phy_rx_symbol_0_clk */
+	0x121,		/* gcc_ufs_phy_rx_symbol_1_clk */
+	0x118,		/* gcc_ufs_phy_tx_symbol_0_clk */
+	0x11C,		/* gcc_ufs_phy_unipro_core_clk */
+	0x60,		/* gcc_usb30_prim_master_clk */
+	0x62,		/* gcc_usb30_prim_mock_utmi_clk */
+	0x61,		/* gcc_usb30_prim_sleep_clk */
+	0x63,		/* gcc_usb3_prim_phy_com_aux_clk */
+	0x64,		/* gcc_usb3_prim_phy_pipe_clk */
+	0x14D,		/* gcc_vcodec0_axi_clk */
+	0x14E,		/* gcc_venus_ahb_clk */
+	0x14C,		/* gcc_venus_ctl_axi_clk */
+	0x39,		/* gcc_video_ahb_clk */
+	0x3F,		/* gcc_video_axi0_clk */
+	0x4D,		/* gcc_video_throttle_core_clk */
+	0x14A,		/* gcc_video_vcodec0_sys_clk */
+	0x148,		/* gcc_video_venus_ctl_clk */
+	0x41,		/* gcc_video_xo_clk */
+	0xED,		/* gpu_cc_debug_mux */
+	0xA5,		/* mc_cc_debug_mux */
+	0x1C,		/* measure_only_cnoc_clk */
+	0x42,		/* measure_only_gcc_camera_xo_clk */
+	0xB1,		/* measure_only_gcc_cpuss_gnoc_clk */
+	0x43,		/* measure_only_gcc_disp_xo_clk */
+	0xEB,		/* measure_only_gcc_gpu_cfg_ahb_clk */
+	0xCD,		/* measure_only_ipa_2x_clk */
+	0x7,		/* measure_only_snoc_clk */
+};
+
+static struct clk_debug_mux gcc_debug_mux = {
+	.priv = &debug_mux_priv,
+	.debug_offset = 0x62000,
+	.post_div_offset = 0x30000,
+	.cbcr_offset = 0x30004,
+	.src_sel_mask = 0x3FF,
+	.src_sel_shift = 0,
+	.post_div_mask = 0xF,
+	.post_div_shift = 0,
+	.post_div_val = 1,
+	.mux_sels = gcc_debug_mux_sels,
+	.hw.init = &(struct clk_init_data){
+		.name = "gcc_debug_mux",
+		.ops = &clk_debug_mux_ops,
+		.parent_names = gcc_debug_mux_parent_names,
+		.num_parents = ARRAY_SIZE(gcc_debug_mux_parent_names),
+		.flags = CLK_IS_MEASURE,
+	},
+};
+
+static const char *const gpu_cc_debug_mux_parent_names[] = {
+	"gpu_cc_ahb_clk",
+	"gpu_cc_crc_ahb_clk",
+	"gpu_cc_cx_gfx3d_clk",
+	"gpu_cc_cx_gmu_clk",
+	"gpu_cc_cx_snoc_dvm_clk",
+	"gpu_cc_cxo_aon_clk",
+	"gpu_cc_cxo_clk",
+	"gpu_cc_gx_gfx3d_clk",
+	"gpu_cc_sleep_clk",
+	"measure_only_gcc_gpu_cfg_ahb_clk",
+	"measure_only_gpu_cc_gx_cxo_clk",
+};
+
+static int gpu_cc_debug_mux_sels[] = {
+	0x10,		/* gpu_cc_ahb_clk */
+	0x11,		/* gpu_cc_crc_ahb_clk */
+	0x1A,		/* gpu_cc_cx_gfx3d_clk */
+	0x18,		/* gpu_cc_cx_gmu_clk */
+	0x15,		/* gpu_cc_cx_snoc_dvm_clk */
+	0xA,		/* gpu_cc_cxo_aon_clk */
+	0x19,		/* gpu_cc_cxo_clk */
+	0xB,		/* gpu_cc_gx_gfx3d_clk */
+	0x16,		/* gpu_cc_sleep_clk */
+	0x1,		/* measure_only_gcc_gpu_cfg_ahb_clk */
+	0xE,		/* measure_only_gpu_cc_gx_cxo_clk */
+};
+
+static struct clk_debug_mux gpu_cc_debug_mux = {
+	.priv = &debug_mux_priv,
+	.debug_offset = 0x1568,
+	.post_div_offset = 0x10FC,
+	.cbcr_offset = 0x1100,
+	.src_sel_mask = 0xFF,
+	.src_sel_shift = 0,
+	.post_div_mask = 0xF,
+	.post_div_shift = 0,
+	.post_div_val = 2,
+	.mux_sels = gpu_cc_debug_mux_sels,
+	.hw.init = &(struct clk_init_data){
+		.name = "gpu_cc_debug_mux",
+		.ops = &clk_debug_mux_ops,
+		.parent_names = gpu_cc_debug_mux_parent_names,
+		.num_parents = ARRAY_SIZE(gpu_cc_debug_mux_parent_names),
+		.flags = CLK_IS_MEASURE,
+	},
+};
+
+static const char *const mc_cc_debug_mux_parent_names[] = {
+	"measure_only_mccc_clk",
+};
+
+static struct clk_debug_mux mc_cc_debug_mux = {
+	.period_offset = 0x20,
+	.hw.init = &(struct clk_init_data){
+		.name = "mc_cc_debug_mux",
+		.ops = &clk_debug_mux_ops,
+		.parent_names = mc_cc_debug_mux_parent_names,
+		.num_parents = ARRAY_SIZE(mc_cc_debug_mux_parent_names),
+		.flags = CLK_IS_MEASURE,
+	},
+};
+
+static struct mux_regmap_names mux_list[] = {
+	{ .mux = &apss_cc_debug_mux, .regmap_name = "qcom,cpucc" },
+	{ .mux = &disp_cc_debug_mux, .regmap_name = "qcom,dispcc" },
+	{ .mux = &gcc_debug_mux, .regmap_name = "qcom,gcc" },
+	{ .mux = &gpu_cc_debug_mux, .regmap_name = "qcom,gpucc" },
+	{ .mux = &mc_cc_debug_mux, .regmap_name = "qcom,mccc" },
+};
+
+static struct clk_dummy measure_only_mccc_clk = {
+	.rrate = 1000,
+	.hw.init = &(struct clk_init_data){
+		.name = "measure_only_mccc_clk",
+		.ops = &clk_dummy_ops,
+	},
+};
+
+static struct clk_dummy measure_only_cnoc_clk = {
+	.rrate = 1000,
+	.hw.init = &(struct clk_init_data){
+		.name = "measure_only_cnoc_clk",
+		.ops = &clk_dummy_ops,
+	},
+};
+
+static struct clk_dummy measure_only_disp_cc_sleep_clk = {
+	.rrate = 1000,
+	.hw.init = &(struct clk_init_data){
+		.name = "measure_only_disp_cc_sleep_clk",
+		.ops = &clk_dummy_ops,
+	},
+};
+
+static struct clk_dummy measure_only_disp_cc_xo_clk = {
+	.rrate = 1000,
+	.hw.init = &(struct clk_init_data){
+		.name = "measure_only_disp_cc_xo_clk",
+		.ops = &clk_dummy_ops,
+	},
+};
+
+static struct clk_dummy measure_only_gcc_camera_xo_clk = {
+	.rrate = 1000,
+	.hw.init = &(struct clk_init_data){
+		.name = "measure_only_gcc_camera_xo_clk",
+		.ops = &clk_dummy_ops,
+	},
+};
+
+static struct clk_dummy measure_only_gcc_cpuss_gnoc_clk = {
+	.rrate = 1000,
+	.hw.init = &(struct clk_init_data){
+		.name = "measure_only_gcc_cpuss_gnoc_clk",
+		.ops = &clk_dummy_ops,
+	},
+};
+
+static struct clk_dummy measure_only_gcc_disp_xo_clk = {
+	.rrate = 1000,
+	.hw.init = &(struct clk_init_data){
+		.name = "measure_only_gcc_disp_xo_clk",
+		.ops = &clk_dummy_ops,
+	},
+};
+
+static struct clk_dummy measure_only_gcc_gpu_cfg_ahb_clk = {
+	.rrate = 1000,
+	.hw.init = &(struct clk_init_data){
+		.name = "measure_only_gcc_gpu_cfg_ahb_clk",
+		.ops = &clk_dummy_ops,
+	},
+};
+
+static struct clk_dummy measure_only_gpu_cc_gx_cxo_clk = {
+	.rrate = 1000,
+	.hw.init = &(struct clk_init_data){
+		.name = "measure_only_gpu_cc_gx_cxo_clk",
+		.ops = &clk_dummy_ops,
+	},
+};
+
+static struct clk_dummy measure_only_ipa_2x_clk = {
+	.rrate = 1000,
+	.hw.init = &(struct clk_init_data){
+		.name = "measure_only_ipa_2x_clk",
+		.ops = &clk_dummy_ops,
+	},
+};
+
+static struct clk_dummy measure_only_snoc_clk = {
+	.rrate = 1000,
+	.hw.init = &(struct clk_init_data){
+		.name = "measure_only_snoc_clk",
+		.ops = &clk_dummy_ops,
+	},
+};
+
+static struct clk_dummy perfcl_clk = {
+	.rrate = 1000,
+	.hw.init = &(struct clk_init_data){
+		.name = "perfcl_clk",
+		.ops = &clk_dummy_ops,
+	},
+};
+
+static struct clk_dummy pwrcl_clk = {
+	.rrate = 1000,
+	.hw.init = &(struct clk_init_data){
+		.name = "pwrcl_clk",
+		.ops = &clk_dummy_ops,
+	},
+};
+
+struct clk_hw *debugcc_khaje_hws[] = {
+	&measure_only_cnoc_clk.hw,
+	&measure_only_disp_cc_sleep_clk.hw,
+	&measure_only_disp_cc_xo_clk.hw,
+	&measure_only_gcc_camera_xo_clk.hw,
+	&measure_only_gcc_cpuss_gnoc_clk.hw,
+	&measure_only_gcc_disp_xo_clk.hw,
+	&measure_only_gcc_gpu_cfg_ahb_clk.hw,
+	&measure_only_gpu_cc_gx_cxo_clk.hw,
+	&measure_only_ipa_2x_clk.hw,
+	&measure_only_mccc_clk.hw,
+	&measure_only_snoc_clk.hw,
+	&perfcl_clk.hw,
+	&pwrcl_clk.hw,
+};
+
+static const struct of_device_id clk_debug_match_table[] = {
+	{ .compatible = "qcom,khaje-debugcc" },
+	{ }
+};
+
+static int clk_debug_khaje_probe(struct platform_device *pdev)
+{
+	struct clk *clk;
+	int ret = 0, i;
+
+	BUILD_BUG_ON(ARRAY_SIZE(apss_cc_debug_mux_parent_names) !=
+		ARRAY_SIZE(apss_cc_debug_mux_sels));
+	BUILD_BUG_ON(ARRAY_SIZE(disp_cc_debug_mux_parent_names) !=
+		ARRAY_SIZE(disp_cc_debug_mux_sels));
+	BUILD_BUG_ON(ARRAY_SIZE(gcc_debug_mux_parent_names) !=
+		ARRAY_SIZE(gcc_debug_mux_sels));
+	BUILD_BUG_ON(ARRAY_SIZE(gpu_cc_debug_mux_parent_names) !=
+		ARRAY_SIZE(gpu_cc_debug_mux_sels));
+
+	clk = devm_clk_get(&pdev->dev, "xo_clk_src");
+	if (IS_ERR(clk)) {
+		if (PTR_ERR(clk) != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "Unable to get xo clock\n");
+		return PTR_ERR(clk);
+	}
+
+	debug_mux_priv.cxo = clk;
+
+	for (i = 0; i < ARRAY_SIZE(mux_list); i++) {
+		ret = map_debug_bases(pdev, mux_list[i].regmap_name,
+				      mux_list[i].mux);
+		if (ret == -EBADR)
+			continue;
+		else if (ret)
+			return ret;
+
+		clk = devm_clk_register(&pdev->dev, &mux_list[i].mux->hw);
+		if (IS_ERR(clk)) {
+			dev_err(&pdev->dev, "Unable to register %s, err:(%d)\n",
+				mux_list[i].mux->hw.init->name, PTR_ERR(clk));
+			return PTR_ERR(clk);
+		}
+	}
+
+	for (i = 0; i < ARRAY_SIZE(debugcc_khaje_hws); i++) {
+		clk = devm_clk_register(&pdev->dev, debugcc_khaje_hws[i]);
+		if (IS_ERR(clk)) {
+			dev_err(&pdev->dev, "Unable to register %s, err:(%d)\n",
+			debugcc_khaje_hws[i]->init->name, PTR_ERR(clk));
+			return PTR_ERR(clk);
+		}
+	}
+
+	ret = clk_debug_measure_register(&gcc_debug_mux.hw);
+	if (ret) {
+		dev_err(&pdev->dev, "Could not register Measure clocks\n");
+		return ret;
+	}
+
+	dev_info(&pdev->dev, "Registered debug measure clocks\n");
+
+	return ret;
+}
+
+static struct platform_driver clk_debug_driver = {
+	.probe = clk_debug_khaje_probe,
+	.driver = {
+		.name = "khaje-debugcc",
+		.of_match_table = clk_debug_match_table,
+	},
+};
+
+int __init clk_debug_khaje_init(void)
+{
+	return platform_driver_register(&clk_debug_driver);
+}
+fs_initcall(clk_debug_khaje_init);
+
+MODULE_DESCRIPTION("QTI DEBUG CC KHAJE Driver");
+MODULE_LICENSE("GPL v2");

drivers/clk/qcom/debugcc-sdm429w.c

@@ -25,6 +25,39 @@ static struct measure_clk_data debug_mux_priv = {
 	.xo_div4_cbcr = 0x30034,
 };
 
+static const char *const apss_cc_debug_mux_parent_names[] = {
+	"pwrcl_clk",
+};
+
+static int apss_cc_debug_mux_sels[] = {
+	0x0,		/* pwrcl_clk */
+};
+
+static int apss_cc_debug_mux_pre_divs[] = {
+	0x1,		/* pwrcl_clk */
+};
+
+static struct clk_debug_mux apss_cc_debug_mux = {
+	.priv = &debug_mux_priv,
+	.debug_offset = 0x0,
+	.post_div_offset = 0x0,
+	.cbcr_offset = U32_MAX,
+	.src_sel_mask = 0x3FF00,
+	.src_sel_shift = 8,
+	.post_div_mask = 0xF0000000,
+	.post_div_shift = 28,
+	.post_div_val = 1,
+	.mux_sels = apss_cc_debug_mux_sels,
+	.pre_div_vals = apss_cc_debug_mux_pre_divs,
+	.hw.init = &(struct clk_init_data){
+		.name = "apss_cc_debug_mux",
+		.ops = &clk_debug_mux_ops,
+		.parent_names = apss_cc_debug_mux_parent_names,
+		.num_parents = ARRAY_SIZE(apss_cc_debug_mux_parent_names),
+		.flags = CLK_IS_MEASURE,
+	},
+};
+
 static const char *const gcc_debug_mux_parent_names[] = {
 	"gcc_ahb_clk",
 	"gcc_apss_ahb_clk",
@@ -154,8 +187,9 @@ static const char *const gcc_debug_mux_parent_names[] = {
 	"gcc_gfx_tbu_clk",
 	"gcc_gfx_tcu_clk",
 	"gcc_gtcu_ahb_clk",
-	"gcc_bimc_clk",
+	"bimc_clk",
 	"gcc_smmu_cfg_clk",
+	"apss_cc_debug_mux",
 };
 
 static int gcc_debug_mux_sels[] = {
@@ -287,8 +321,9 @@ static int gcc_debug_mux_sels[] = {
 	0x52,		/* gcc_gfx_tbu_clk */
 	0x53,		/* gcc_gfx_tcu_clk */
 	0x58,		/* gcc_gtcu_ahb_clk */
-	0x15A,		/* gcc_bimc_clk */
+	0x15A,		/* bimc_clk */
 	0x5B,		/* gcc_smmu_cfg_clk */
+	0x16A,		/* apss_cc_debug_mux */
 };
 
 static struct clk_debug_mux gcc_debug_mux = {
@@ -312,13 +347,27 @@ static struct clk_debug_mux gcc_debug_mux = {
 	},
 };
 
+static struct clk_dummy pwrcl_clk = {
+	.rrate = 1000,
+	.hw.init = &(struct clk_init_data){
+		.name = "pwrcl_clk",
+		.ops = &clk_dummy_ops,
+	},
+};
+
+struct clk_hw *debugcc_qm215_hws[] = {
+	&pwrcl_clk.hw,
+};
+
 static struct mux_regmap_names mux_list[] = {
 	{ .mux = &gcc_debug_mux, .regmap_name = "qcom,gcc" },
+	{ .mux = &apss_cc_debug_mux, .regmap_name = "qcom,cpu" },
 };
 
 static const struct of_device_id clk_debug_match_table[] = {
 	{ .compatible = "qcom,sdm429w-debugcc" },
 	{ .compatible = "qcom,qm215-debugcc" },
+	{ .compatible = "qcom,sdm429-debugcc" },
 	{ }
 };
 
@@ -356,6 +405,15 @@ static int clk_debug_sdm429w_probe(struct platform_device *pdev)
 		}
 	}
 
+	for (i = 0; i < ARRAY_SIZE(debugcc_qm215_hws); i++) {
+		clk = devm_clk_register(&pdev->dev, debugcc_qm215_hws[i]);
+		if (IS_ERR(clk)) {
+			dev_err(&pdev->dev, "Unable to register %s, err:(%d)\n",
+			debugcc_qm215_hws[i]->init->name, PTR_ERR(clk));
+			return PTR_ERR(clk);
+		}
+	}
+
 	ret = clk_debug_measure_register(&gcc_debug_mux.hw);
 	if (ret) {
 		dev_err(&pdev->dev, "Could not register Measure clocks\n");

drivers/clk/qcom/debugcc-sdm439.c

@@ -0,0 +1,471 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+#define pr_fmt(fmt) "clk: %s: " fmt, __func__
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "clk-debug.h"
+#include "common.h"
+
+static struct measure_clk_data debug_mux_priv = {
+	.ctl_reg = 0x74004,
+	.status_reg = 0x74008,
+	.xo_div4_cbcr = 0x30034,
+};
+
+static const char *const apss_cc_debug_mux_parent_names[] = {
+	"pwrcl_clk",
+	"perfcl_clk",
+};
+
+static int apss_cc_debug_mux_sels[] = {
+	0x0,		/* pwrcl_clk */
+	0x1,		/* perfcl_clk */
+};
+
+static int apss_cc_debug_mux_pre_divs[] = {
+	0x1,		/* pwrcl_clk */
+	0x1,		/* perfcl_clk */
+};
+
+static struct clk_debug_mux apss_cc_debug_mux = {
+	.priv = &debug_mux_priv,
+	.debug_offset = 0x0,
+	.post_div_offset = 0x0,
+	.cbcr_offset = U32_MAX,
+	.src_sel_mask = 0x3FF00,
+	.src_sel_shift = 8,
+	.post_div_mask = 0xF0000000,
+	.post_div_shift = 28,
+	.post_div_val = 2,
+	.mux_sels = apss_cc_debug_mux_sels,
+	.pre_div_vals = apss_cc_debug_mux_pre_divs,
+	.hw.init = &(struct clk_init_data){
+		.name = "apss_cc_debug_mux",
+		.ops = &clk_debug_mux_ops,
+		.parent_names = apss_cc_debug_mux_parent_names,
+		.num_parents = ARRAY_SIZE(apss_cc_debug_mux_parent_names),
+		.flags = CLK_IS_MEASURE,
+	},
+};
+
+static const char *const gcc_debug_mux_parent_names[] = {
+	"gcc_ahb_clk",
+	"gcc_apss_ahb_clk",
+	"gcc_apss_axi_clk",
+	"gcc_bimc_gfx_clk",
+	"gcc_bimc_gpu_clk",
+	"gcc_blsp1_ahb_clk",
+	"gcc_blsp1_qup2_i2c_apps_clk",
+	"gcc_blsp1_qup2_spi_apps_clk",
+	"gcc_blsp1_qup3_i2c_apps_clk",
+	"gcc_blsp1_qup3_spi_apps_clk",
+	"gcc_blsp1_qup4_i2c_apps_clk",
+	"gcc_blsp1_qup4_spi_apps_clk",
+	"gcc_blsp1_sleep_clk",
+	"gcc_blsp1_uart1_apps_clk",
+	"gcc_blsp1_uart1_sim_clk",
+	"gcc_blsp1_uart2_apps_clk",
+	"gcc_blsp1_uart2_sim_clk",
+	"gcc_blsp2_ahb_clk",
+	"gcc_blsp2_qup1_i2c_apps_clk",
+	"gcc_blsp2_qup1_spi_apps_clk",
+	"gcc_blsp2_qup2_i2c_apps_clk",
+	"gcc_blsp2_qup2_spi_apps_clk",
+	"gcc_blsp2_qup3_i2c_apps_clk",
+	"gcc_blsp2_qup3_spi_apps_clk",
+	"gcc_blsp2_sleep_clk",
+	"gcc_blsp2_uart1_apps_clk",
+	"gcc_blsp2_uart1_sim_clk",
+	"gcc_blsp2_uart2_apps_clk",
+	"gcc_blsp2_uart2_sim_clk",
+	"gcc_boot_rom_ahb_clk",
+	"gcc_camss_ahb_clk",
+	"gcc_camss_cci_ahb_clk",
+	"gcc_camss_cci_clk",
+	"gcc_camss_cpp_ahb_clk",
+	"gcc_camss_cpp_axi_clk",
+	"gcc_camss_cpp_clk",
+	"gcc_camss_csi0_ahb_clk",
+	"gcc_camss_csi0_clk",
+	"gcc_camss_csi0phy_clk",
+	"gcc_camss_csi0phytimer_clk",
+	"gcc_camss_csi0pix_clk",
+	"gcc_camss_csi0rdi_clk",
+	"gcc_camss_csi1_ahb_clk",
+	"gcc_camss_csi1_clk",
+	"gcc_camss_csi1phy_clk",
+	"gcc_camss_csi1phytimer_clk",
+	"gcc_camss_csi1pix_clk",
+	"gcc_camss_csi1rdi_clk",
+	"gcc_camss_csi2_ahb_clk",
+	"gcc_camss_csi2_clk",
+	"gcc_camss_csi2phy_clk",
+	"gcc_camss_csi2pix_clk",
+	"gcc_camss_csi2rdi_clk",
+	"gcc_camss_csi_vfe0_clk",
+	"gcc_camss_csi_vfe1_clk",
+	"gcc_camss_gp0_clk",
+	"gcc_camss_gp1_clk",
+	"gcc_camss_ispif_ahb_clk",
+	"gcc_camss_jpeg0_clk",
+	"gcc_camss_jpeg_ahb_clk",
+	"gcc_camss_jpeg_axi_clk",
+	"gcc_camss_mclk0_clk",
+	"gcc_camss_mclk1_clk",
+	"gcc_camss_mclk2_clk",
+	"gcc_camss_micro_ahb_clk",
+	"gcc_camss_top_ahb_clk",
+	"gcc_camss_vfe0_clk",
+	"gcc_camss_vfe1_ahb_clk",
+	"gcc_camss_vfe1_axi_clk",
+	"gcc_camss_vfe1_clk",
+	"gcc_camss_vfe_ahb_clk",
+	"gcc_camss_vfe_axi_clk",
+	"gcc_crypto_ahb_clk",
+	"gcc_crypto_axi_clk",
+	"gcc_crypto_clk",
+	"gcc_gp1_clk",
+	"gcc_gp2_clk",
+	"gcc_gp3_clk",
+	"gcc_im_sleep_clk",
+	"gcc_lpass_mport_axi_clk",
+	"gcc_lpass_q6_axi_clk",
+	"gcc_lpass_sway_clk",
+	"gcc_mdss_ahb_clk",
+	"gcc_mdss_axi_clk",
+	"gcc_mdss_byte0_clk",
+	"gcc_mdss_esc0_clk",
+	"gcc_mdss_mdp_clk",
+	"gcc_mdss_pclk0_clk",
+	"gcc_mdss_vsync_clk",
+	"gcc_mpm_ahb_clk",
+	"gcc_msg_ram_ahb_clk",
+	"gcc_oxili_ahb_clk",
+	"gcc_oxili_aon_clk",
+	"gcc_oxili_gfx3d_clk",
+	"gcc_pcnoc_mpu_cfg_ahb_clk",
+	"gcc_pdm2_clk",
+	"gcc_pdm_ahb_clk",
+	"gcc_pdm_xo4_clk",
+	"gcc_prng_ahb_clk",
+	"gcc_q6_mpu_cfg_ahb_clk",
+	"gcc_rpm_cfg_xpu_clk",
+	"gcc_sdcc1_ahb_clk",
+	"gcc_sdcc1_apps_clk",
+	"gcc_sdcc1_ice_core_clk",
+	"gcc_sdcc2_ahb_clk",
+	"gcc_sdcc2_apps_clk",
+	"gcc_sec_ctrl_acc_clk",
+	"gcc_sec_ctrl_ahb_clk",
+	"gcc_sec_ctrl_boot_rom_patch_clk",
+	"gcc_sec_ctrl_clk",
+	"gcc_sec_ctrl_sense_clk",
+	"gcc_tcsr_ahb_clk",
+	"gcc_tlmm_ahb_clk",
+	"gcc_tlmm_clk",
+	"gcc_usb2a_phy_sleep_clk",
+	"gcc_usb_hs_ahb_clk",
+	"gcc_usb_hs_inactivity_timers_clk",
+	"gcc_usb_hs_phy_cfg_ahb_clk",
+	"gcc_usb_hs_system_clk",
+	"gcc_venus0_ahb_clk",
+	"gcc_venus0_axi_clk",
+	"gcc_venus0_core0_vcodec0_clk",
+	"gcc_venus0_vcodec0_clk",
+	"gcc_xo_clk",
+	"gcc_xo_div4_clk",
+	"gcc_gfx_tbu_clk",
+	"gcc_gfx_tcu_clk",
+	"gcc_gtcu_ahb_clk",
+	"bimc_clk",
+	"gcc_smmu_cfg_clk",
+	"apss_cc_debug_mux",
+	"gcc_mdss_pclk1_clk",
+	"gcc_mdss_byte1_clk",
+	"gcc_mdss_esc1_clk",
+	"gcc_oxili_timer_clk",
+	"gcc_blsp1_qup1_spi_apps_clk",
+	"gcc_blsp1_qup1_i2c_apps_clk",
+	"gcc_blsp2_qup4_spi_apps_clk",
+	"gcc_blsp2_qup4_i2c_apps_clk",
+};
+
+static int gcc_debug_mux_sels[] = {
+	0x148,		/* gcc_ahb_clk */
+	0x168,		/* gcc_apss_ahb_clk */
+	0x169,		/* gcc_apss_axi_clk */
+	0x2D,		/* gcc_bimc_gfx_clk */
+	0x157,		/* gcc_bimc_gpu_clk */
+	0x88,		/* gcc_blsp1_ahb_clk */
+	0x90,		/* gcc_blsp1_qup2_i2c_apps_clk */
+	0x8E,		/* gcc_blsp1_qup2_spi_apps_clk */
+	0x94,		/* gcc_blsp1_qup3_i2c_apps_clk */
+	0x93,		/* gcc_blsp1_qup3_spi_apps_clk */
+	0x96,		/* gcc_blsp1_qup4_i2c_apps_clk */
+	0x95,		/* gcc_blsp1_qup4_spi_apps_clk */
+	0x89,		/* gcc_blsp1_sleep_clk */
+	0x8C,		/* gcc_blsp1_uart1_apps_clk */
+	0x8D,		/* gcc_blsp1_uart1_sim_clk */
+	0x91,		/* gcc_blsp1_uart2_apps_clk */
+	0x92,		/* gcc_blsp1_uart2_sim_clk */
+	0x98,		/* gcc_blsp2_ahb_clk */
+	0x9B,		/* gcc_blsp2_qup1_i2c_apps_clk */
+	0x9A,		/* gcc_blsp2_qup1_spi_apps_clk */
+	0xA0,		/* gcc_blsp2_qup2_i2c_apps_clk */
+	0x9E,		/* gcc_blsp2_qup2_spi_apps_clk */
+	0xA4,		/* gcc_blsp2_qup3_i2c_apps_clk */
+	0xA3,		/* gcc_blsp2_qup3_spi_apps_clk */
+	0x99,		/* gcc_blsp2_sleep_clk */
+	0x9C,		/* gcc_blsp2_uart1_apps_clk */
+	0x9D,		/* gcc_blsp2_uart1_sim_clk */
+	0x9A,		/* gcc_blsp2_uart2_apps_clk */
+	0xA2,		/* gcc_blsp2_uart2_sim_clk */
+	0xF8,		/* gcc_boot_rom_ahb_clk */
+	0xA8,		/* gcc_camss_ahb_clk */
+	0xB0,		/* gcc_camss_cci_ahb_clk */
+	0xAF,		/* gcc_camss_cci_clk */
+	0xBA,		/* gcc_camss_cpp_ahb_clk */
+	0x1A3,		/* gcc_camss_cpp_axi_clk */
+	0xB9,		/* gcc_camss_cpp_clk */
+	0xC1,		/* gcc_camss_csi0_ahb_clk */
+	0xC0,		/* gcc_camss_csi0_clk */
+	0xC2,		/* gcc_camss_csi0phy_clk */
+	0xB1,		/* gcc_camss_csi0phytimer_clk */
+	0xC4,		/* gcc_camss_csi0pix_clk */
+	0xC3,		/* gcc_camss_csi0rdi_clk */
+	0xC6,		/* gcc_camss_csi1_ahb_clk */
+	0xC5,		/* gcc_camss_csi1_clk */
+	0xC7,		/* gcc_camss_csi1phy_clk */
+	0xB2,		/* gcc_camss_csi1phytimer_clk */
+	0xE1,		/* gcc_camss_csi1pix_clk */
+	0xE0,		/* gcc_camss_csi1rdi_clk */
+	0xE4,		/* gcc_camss_csi2_ahb_clk */
+	0xE3,		/* gcc_camss_csi2_clk */
+	0xE5,		/* gcc_camss_csi2phy_clk */
+	0xE7,		/* gcc_camss_csi2pix_clk */
+	0xE6,		/* gcc_camss_csi2rdi_clk */
+	0xBF,		/* gcc_camss_csi_vfe0_clk */
+	0x1A0,		/* gcc_camss_csi_vfe1_clk */
+	0xAB,		/* gcc_camss_gp0_clk */
+	0xAC,		/* gcc_camss_gp1_clk */
+	0xE2,		/* gcc_camss_ispif_ahb_clk */
+	0xB3,		/* gcc_camss_jpeg0_clk */
+	0xB4,		/* gcc_camss_jpeg_ahb_clk */
+	0xB5,		/* gcc_camss_jpeg_axi_clk */
+	0xAD,		/* gcc_camss_mclk0_clk */
+	0xAE,		/* gcc_camss_mclk1_clk */
+	0x1BD,		/* gcc_camss_mclk2_clk */
+	0xAA,		/* gcc_camss_micro_ahb_clk */
+	0xA9,		/* gcc_camss_top_ahb_clk */
+	0xB8,		/* gcc_camss_vfe0_clk */
+	0x1A2,		/* gcc_camss_vfe1_ahb_clk */
+	0x1A4,		/* gcc_camss_vfe1_axi_clk */
+	0x1A1,		/* gcc_camss_vfe1_clk */
+	0xBB,		/* gcc_camss_vfe_ahb_clk */
+	0xBC,		/* gcc_camss_vfe_axi_clk */
+	0x13A,		/* gcc_crypto_ahb_clk */
+	0x139,		/* gcc_crypto_axi_clk */
+	0x138,		/* gcc_crypto_clk */
+	0x10,		/* gcc_gp1_clk */
+	0x11,		/* gcc_gp2_clk */
+	0x12,		/* gcc_gp3_clk */
+	0x14B,		/* gcc_im_sleep_clk */
+	0x162,		/* gcc_lpass_mport_axi_clk */
+	0x160,		/* gcc_lpass_q6_axi_clk */
+	0x163,		/* gcc_lpass_sway_clk */
+	0x1F6,		/* gcc_mdss_ahb_clk */
+	0x1F7,		/* gcc_mdss_axi_clk */
+	0x1FC,		/* gcc_mdss_byte0_clk */
+	0x1FD,		/* gcc_mdss_esc0_clk */
+	0x1F9,		/* gcc_mdss_mdp_clk */
+	0x1F8,		/* gcc_mdss_pclk0_clk */
+	0x1FB,		/* gcc_mdss_vsync_clk */
+	0x110,		/* gcc_mpm_ahb_clk */
+	0x100,		/* gcc_msg_ram_ahb_clk */
+	0x1EB,		/* gcc_oxili_ahb_clk */
+	0xEE,		/* gcc_oxili_aon_clk */
+	0x1EA,		/* gcc_oxili_gfx3d_clk */
+	0xC9,		/* gcc_pcnoc_mpu_cfg_ahb_clk */
+	0xD2,		/* gcc_pdm2_clk */
+	0xD0,		/* gcc_pdm_ahb_clk */
+	0xD1,		/* gcc_pdm_xo4_clk */
+	0xD8,		/* gcc_prng_ahb_clk */
+	0xC8,		/* gcc_q6_mpu_cfg_ahb_clk */
+	0x38,		/* gcc_rpm_cfg_xpu_clk */
+	0x69,		/* gcc_sdcc1_ahb_clk */
+	0x68,		/* gcc_sdcc1_apps_clk */
+	0x6A,		/* gcc_sdcc1_ice_core_clk */
+	0x71,		/* gcc_sdcc2_ahb_clk */
+	0x70,		/* gcc_sdcc2_apps_clk */
+	0x120,		/* gcc_sec_ctrl_acc_clk */
+	0x121,		/* gcc_sec_ctrl_ahb_clk */
+	0x124,		/* gcc_sec_ctrl_boot_rom_patch_clk */
+	0x122,		/* gcc_sec_ctrl_clk */
+	0x123,		/* gcc_sec_ctrl_sense_clk */
+	0xE8,		/* gcc_tcsr_ahb_clk */
+	0x108,		/* gcc_tlmm_ahb_clk */
+	0x109,		/* gcc_tlmm_clk */
+	0x63,		/* gcc_usb2a_phy_sleep_clk */
+	0x61,		/* gcc_usb_hs_ahb_clk */
+	0x62,		/* gcc_usb_hs_inactivity_timers_clk */
+	0x64,		/* gcc_usb_hs_phy_cfg_ahb_clk */
+	0x60,		/* gcc_usb_hs_system_clk */
+	0x1F3,		/* gcc_venus0_ahb_clk */
+	0x1F2,		/* gcc_venus0_axi_clk */
+	0x1B8,		/* gcc_venus0_core0_vcodec0_clk */
+	0x1F1,		/* gcc_venus0_vcodec0_clk */
+	0x149,		/* gcc_xo_clk */
+	0x14A,		/* gcc_xo_div4_clk */
+	0x52,		/* gcc_gfx_tbu_clk */
+	0x53,		/* gcc_gfx_tcu_clk */
+	0x58,		/* gcc_gtcu_ahb_clk */
+	0x15A,		/* bimc_clk */
+	0x5B,		/* gcc_smmu_cfg_clk */
+	0x16A,		/* apss_cc_debug_mux */
+	0x1e3,		/* gcc_mdss_pclk1_clk */
+	0x1e4,		/* gcc_mdss_byte1_clk */
+	0x1e5,		/* gcc_mdss_esc1_clk */
+	0x1e9,		/* gcc_oxili_timer_clk */
+	0x8a,		/* gcc_blsp1_qup1_spi_apps_clk */
+	0x8b,		/* gcc_blsp1_qup1_i2c_apps_clk */
+	0xa5,		/* gcc_blsp2_qup4_spi_apps_clk */
+	0xa6,		/* gcc_blsp2_qup4_i2c_apps_clk */
+};
+
+static struct clk_debug_mux gcc_debug_mux = {
+	.priv = &debug_mux_priv,
+	.en_mask = BIT(16),
+	.debug_offset = 0x74000,
+	.post_div_offset = 0x74000,
+	.cbcr_offset = 0x74000,
+	.src_sel_mask = 0x1FF,
+	.src_sel_shift = 0,
+	.post_div_mask = 0xF000,
+	.post_div_shift = 12,
+	.post_div_val = 1,
+	.mux_sels = gcc_debug_mux_sels,
+	.hw.init = &(struct clk_init_data){
+		.name = "gcc_debug_mux",
+		.ops = &clk_debug_mux_ops,
+		.parent_names = gcc_debug_mux_parent_names,
+		.num_parents = ARRAY_SIZE(gcc_debug_mux_parent_names),
+		.flags = CLK_IS_MEASURE,
+	},
+};
+
+static struct clk_dummy pwrcl_clk = {
+	.rrate = 1000,
+	.hw.init = &(struct clk_init_data){
+		.name = "pwrcl_clk",
+		.ops = &clk_dummy_ops,
+	},
+};
+
+static struct clk_dummy perfcl_clk = {
+	.rrate = 1000,
+	.hw.init = &(struct clk_init_data){
+		.name = "perfcl_clk",
+		.ops = &clk_dummy_ops,
+	},
+};
+
+struct clk_hw *debugcc_sdm439_hws[] = {
+	&pwrcl_clk.hw,
+	&perfcl_clk.hw,
+};
+
+static struct mux_regmap_names mux_list[] = {
+	{ .mux = &gcc_debug_mux, .regmap_name = "qcom,gcc" },
+	{ .mux = &apss_cc_debug_mux, .regmap_name = "qcom,cpu" },
+};
+
+static const struct of_device_id clk_debug_match_table[] = {
+	{ .compatible = "qcom,sdm439-debugcc" },
+	{ }
+};
+
+static int clk_debug_sdm429w_probe(struct platform_device *pdev)
+{
+	struct clk *clk;
+	int ret, i;
+
+	BUILD_BUG_ON(ARRAY_SIZE(gcc_debug_mux_parent_names) !=
+		ARRAY_SIZE(gcc_debug_mux_sels));
+
+	clk = devm_clk_get(&pdev->dev, "xo_clk_src");
+	if (IS_ERR(clk)) {
+		if (PTR_ERR(clk) != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "Unable to get xo clock\n");
+		return PTR_ERR(clk);
+	}
+
+	debug_mux_priv.cxo = clk;
+
+	for (i = 0; i < ARRAY_SIZE(mux_list); i++) {
+		ret = map_debug_bases(pdev, mux_list[i].regmap_name,
+				      mux_list[i].mux);
+		if (ret == -EBADR)
+			continue;
+		else if (ret)
+			return ret;
+
+		clk = devm_clk_register(&pdev->dev, &mux_list[i].mux->hw);
+		if (IS_ERR(clk)) {
+			dev_err(&pdev->dev, "Unable to register %s, err:(%d)\n",
+				clk_hw_get_name(&mux_list[i].mux->hw),
+				PTR_ERR(clk));
+			return PTR_ERR(clk);
+		}
+	}
+
+	for (i = 0; i < ARRAY_SIZE(debugcc_sdm439_hws); i++) {
+		clk = devm_clk_register(&pdev->dev,
+			debugcc_sdm439_hws[i]);
+		if (IS_ERR(clk)) {
+			dev_err(&pdev->dev, "Unable to register %s, err:(%d)\n",
+			debugcc_sdm439_hws[i]->init->name,
+			PTR_ERR(clk));
+			return PTR_ERR(clk);
+		}
+	}
+
+	ret = clk_debug_measure_register(&gcc_debug_mux.hw);
+	if (ret) {
+		dev_err(&pdev->dev, "Could not register Measure clocks\n");
+		return ret;
+	}
+
+	dev_info(&pdev->dev, "Registered debug measure clocks\n");
+
+	return ret;
+}
+
+static struct platform_driver clk_debug_driver = {
+	.probe = clk_debug_sdm429w_probe,
+	.driver = {
+		.name = "sdm439-debugcc",
+		.of_match_table = clk_debug_match_table,
+	},
+};
+
+static int __init clk_debug_sdm429w_init(void)
+{
+	return platform_driver_register(&clk_debug_driver);
+}
+fs_initcall(clk_debug_sdm429w_init);
+
+MODULE_DESCRIPTION("QTI DEBUG CC SDM429W Driver");
+MODULE_LICENSE("GPL v2");

drivers/clk/qcom/dispcc-khaje.c

@@ -0,0 +1,637 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,dispcc-khaje.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap.h"
+#include "common.h"
+#include "vdd-level-bengal.h"
+
+static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH + 1, 1, vdd_corner);
+
+
+enum {
+	P_BI_TCXO,
+	P_DISP_CC_PLL0_OUT_EVEN,
+	P_DISP_CC_PLL0_OUT_MAIN,
+	P_DSI0_PHY_PLL_OUT_BYTECLK,
+	P_DSI0_PHY_PLL_OUT_DSICLK,
+	P_GCC_DISP_GPLL0_DIV_CLK_SRC,
+};
+
+static const struct parent_map disp_cc_parent_map_0[] = {
+	{ P_BI_TCXO, 0 },
+	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
+};
+
+static const char * const disp_cc_parent_names_0[] = {
+	"bi_tcxo",
+	"dsi0_phy_pll_out_byteclk",
+};
+
+static const struct parent_map disp_cc_parent_map_1[] = {
+	{ P_BI_TCXO, 0 },
+	{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
+	{ P_GCC_DISP_GPLL0_DIV_CLK_SRC, 4 },
+	{ P_DISP_CC_PLL0_OUT_EVEN, 5 },
+};
+
+static const char * const disp_cc_parent_names_1[] = {
+	"bi_tcxo",
+	"disp_cc_pll0",
+	"gcc_disp_gpll0_div_clk_src",
+	"disp_cc_pll0",
+};
+
+static const struct parent_map disp_cc_parent_map_2[] = {
+	{ P_BI_TCXO, 0 },
+	{ P_GCC_DISP_GPLL0_DIV_CLK_SRC, 4 },
+};
+
+static const char * const disp_cc_parent_names_2[] = {
+	"bi_tcxo",
+	"gcc_disp_gpll0_div_clk_src",
+};
+
+static const struct parent_map disp_cc_parent_map_3[] = {
+	{ P_BI_TCXO, 0 },
+	{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
+};
+
+static const char * const disp_cc_parent_names_3[] = {
+	"bi_tcxo",
+	"dsi0_phy_pll_out_dsiclk",
+};
+
+static const struct parent_map disp_cc_parent_map_4[] = {
+	{ P_BI_TCXO, 0 },
+};
+
+static const char * const disp_cc_parent_names_4[] = {
+	"bi_tcxo",
+};
+
+static struct pll_vco lucid_vco[] = {
+	{ 249600000, 2000000000, 0 },
+};
+
+/* 615MHz configuration */
+static const struct alpha_pll_config disp_cc_pll0_config = {
+	.l = 0x20,
+	.alpha = 0x800,
+	.config_ctl_val = 0x20485699,
+	.config_ctl_hi_val = 0x00002261,
+	.config_ctl_hi1_val = 0x329A299C,
+	.user_ctl_val = 0x00000001,
+	.user_ctl_hi_val = 0x00000805,
+	.user_ctl_hi1_val = 0x00000000,
+};
+
+static struct clk_alpha_pll disp_cc_pll0 = {
+	.offset = 0x0,
+	.vco_table = lucid_vco,
+	.num_vco = ARRAY_SIZE(lucid_vco),
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+	.clkr = {
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_pll0",
+			.parent_names = (const char *[]){ "bi_tcxo" },
+			.num_parents = 1,
+			.ops = &clk_alpha_pll_lucid_ops,
+			.vdd_class = &vdd_cx,
+			.num_rate_max = VDD_NUM,
+			.rate_max = (unsigned long[VDD_NUM]) {
+				[VDD_MIN] = 615000000,
+				[VDD_LOW] = 1066000000,
+				[VDD_LOW_L1] = 1500000000,
+				[VDD_NOMINAL] = 1750000000,
+				[VDD_HIGH] = 2000000000},
+		},
+	},
+};
+
+static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
+	.reg = 0x10dc,
+	.shift = 0,
+	.width = 4,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "disp_cc_mdss_byte0_div_clk_src",
+		.parent_names =
+			(const char *[]){ "disp_cc_mdss_byte0_clk_src" },
+		.num_parents = 1,
+		.ops = &clk_regmap_div_ops,
+	},
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
+	F(19200000, P_BI_TCXO, 1, 0, 0),
+	F(37500000, P_GCC_DISP_GPLL0_DIV_CLK_SRC, 8, 0, 0),
+	F(75000000, P_GCC_DISP_GPLL0_DIV_CLK_SRC, 4, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
+	.cmd_rcgr = 0x115c,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = disp_cc_parent_map_2,
+	.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
+	.enable_safe_config = true,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "disp_cc_mdss_ahb_clk_src",
+		.parent_names = disp_cc_parent_names_2,
+		.num_parents = ARRAY_SIZE(disp_cc_parent_names_2),
+		.ops = &clk_rcg2_ops,
+		.vdd_class = &vdd_cx,
+		.num_rate_max = VDD_NUM,
+		.rate_max = (unsigned long[VDD_NUM]) {
+			[VDD_LOWER] = 19200000,
+			[VDD_LOW] = 37500000,
+			[VDD_NOMINAL] = 75000000},
+	},
+};
+
+static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
+	.cmd_rcgr = 0x10c4,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = disp_cc_parent_map_0,
+	.enable_safe_config = true,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "disp_cc_mdss_byte0_clk_src",
+		.parent_names = disp_cc_parent_names_0,
+		.num_parents = ARRAY_SIZE(disp_cc_parent_names_0),
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_byte2_ops,
+		.vdd_class = &vdd_cx,
+		.num_rate_max = VDD_NUM,
+		.rate_max = (unsigned long[VDD_NUM]) {
+			[VDD_LOWER] = 187500000,
+			[VDD_LOW] = 300000000,
+			[VDD_LOW_L1] = 358000000},
+	},
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
+	F(19200000, P_BI_TCXO, 1, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
+	.cmd_rcgr = 0x10e0,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = disp_cc_parent_map_0,
+	.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "disp_cc_mdss_esc0_clk_src",
+		.parent_names = disp_cc_parent_names_0,
+		.num_parents = ARRAY_SIZE(disp_cc_parent_names_0),
+		.ops = &clk_rcg2_ops,
+		.vdd_class = &vdd_cx,
+		.num_rate_max = VDD_NUM,
+		.rate_max = (unsigned long[VDD_NUM]) {
+			[VDD_LOWER] = 19200000},
+	},
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
+	F(19200000, P_BI_TCXO, 1, 0, 0),
+	F(200000000, P_GCC_DISP_GPLL0_DIV_CLK_SRC, 1.5, 0, 0),
+	F(300000000, P_GCC_DISP_GPLL0_DIV_CLK_SRC, 1, 0, 0),
+	F(383000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
+	F(470000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
+	F(560000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
+	.cmd_rcgr = 0x107c,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = disp_cc_parent_map_1,
+	.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
+	.enable_safe_config = true,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "disp_cc_mdss_mdp_clk_src",
+		.parent_names = disp_cc_parent_names_1,
+		.num_parents = ARRAY_SIZE(disp_cc_parent_names_1),
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_rcg2_ops,
+		.vdd_class = &vdd_cx,
+		.num_rate_max = VDD_NUM,
+		.rate_max = (unsigned long[VDD_NUM]) {
+			[VDD_LOWER] = 200000000,
+			[VDD_LOW] = 300000000,
+			[VDD_LOW_L1] = 383000000,
+			[VDD_NOMINAL] = 470000000,
+			[VDD_HIGH] = 560000000},
+	},
+};
+
+static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
+	.cmd_rcgr = 0x1064,
+	.mnd_width = 8,
+	.hid_width = 5,
+	.parent_map = disp_cc_parent_map_3,
+	.enable_safe_config = true,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "disp_cc_mdss_pclk0_clk_src",
+		.parent_names = disp_cc_parent_names_3,
+		.num_parents = ARRAY_SIZE(disp_cc_parent_names_3),
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_pixel_ops,
+		.vdd_class = &vdd_cx,
+		.num_rate_max = VDD_NUM,
+		.rate_max = (unsigned long[VDD_NUM]) {
+			[VDD_LOWER] = 300000000,
+			[VDD_LOW] = 525000000,
+			[VDD_LOW_L1] = 625000000},
+	},
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
+	F(19200000, P_BI_TCXO, 1, 0, 0),
+	F(200000000, P_GCC_DISP_GPLL0_DIV_CLK_SRC, 1.5, 0, 0),
+	F(300000000, P_GCC_DISP_GPLL0_DIV_CLK_SRC, 1, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
+	.cmd_rcgr = 0x1094,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = disp_cc_parent_map_1,
+	.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
+	.enable_safe_config = true,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "disp_cc_mdss_rot_clk_src",
+		.parent_names = disp_cc_parent_names_1,
+		.num_parents = ARRAY_SIZE(disp_cc_parent_names_1),
+		.ops = &clk_rcg2_ops,
+		.vdd_class = &vdd_cx,
+		.num_rate_max = VDD_NUM,
+		.rate_max = (unsigned long[VDD_NUM]) {
+			[VDD_LOWER] = 200000000,
+			[VDD_LOW] = 300000000},
+	},
+};
+
+static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
+	.cmd_rcgr = 0x10ac,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = disp_cc_parent_map_4,
+	.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "disp_cc_mdss_vsync_clk_src",
+		.parent_names = disp_cc_parent_names_4,
+		.num_parents = ARRAY_SIZE(disp_cc_parent_names_4),
+		.ops = &clk_rcg2_ops,
+		.vdd_class = &vdd_cx,
+		.num_rate_max = VDD_NUM,
+		.rate_max = (unsigned long[VDD_NUM]) {
+			[VDD_LOWER] = 19200000},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_ahb_clk = {
+	.halt_reg = 0x104c,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x104c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_ahb_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_ahb_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_byte0_clk = {
+	.halt_reg = 0x102c,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x102c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_byte0_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_byte0_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
+	.halt_reg = 0x1030,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1030,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_byte0_intf_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_byte0_div_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_esc0_clk = {
+	.halt_reg = 0x1034,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1034,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_esc0_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_esc0_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_mdp_clk = {
+	.halt_reg = 0x1010,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1010,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_mdp_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_mdp_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
+	.halt_reg = 0x1020,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x1020,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_mdp_lut_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_mdp_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
+	.halt_reg = 0x2004,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x2004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_non_gdsc_ahb_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_ahb_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_pclk0_clk = {
+	.halt_reg = 0x1168,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1168,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_pclk0_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_pclk0_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_rot_clk = {
+	.halt_reg = 0x1018,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1018,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_rot_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_rot_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
+	.halt_reg = 0x200c,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x200c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_rscc_ahb_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_ahb_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
+	.halt_reg = 0x2008,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x2008,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_rscc_vsync_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_vsync_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch disp_cc_mdss_vsync_clk = {
+	.halt_reg = 0x1028,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1028,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "disp_cc_mdss_vsync_clk",
+			.parent_names = (const char *[]){
+				"disp_cc_mdss_vsync_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_regmap *disp_cc_khaje_clocks[] = {
+	[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
+	[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
+	[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
+	[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
+	[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
+	[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
+	[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
+	[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
+	[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
+	[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
+	[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
+	[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
+	[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
+	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
+	[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
+	[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
+	[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
+	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
+	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
+	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
+	[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
+};
+
+static const struct regmap_config disp_cc_khaje_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x10000,
+	.fast_io = true,
+};
+
+static const struct qcom_cc_desc disp_cc_khaje_desc = {
+	.config = &disp_cc_khaje_regmap_config,
+	.clks = disp_cc_khaje_clocks,
+	.num_clks = ARRAY_SIZE(disp_cc_khaje_clocks),
+};
+
+static const struct of_device_id disp_cc_khaje_match_table[] = {
+	{ .compatible = "qcom,khaje-dispcc" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, disp_cc_khaje_match_table);
+
+static int disp_cc_khaje_probe(struct platform_device *pdev)
+{
+	struct regmap *regmap;
+	struct clk *clk;
+	int ret;
+
+	vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");
+	if (IS_ERR(vdd_cx.regulator[0])) {
+		if (PTR_ERR(vdd_cx.regulator[0]) != -EPROBE_DEFER)
+			dev_err(&pdev->dev,
+					"Unable to get vdd_cx regulator\n");
+		return PTR_ERR(vdd_cx.regulator[0]);
+	}
+
+	clk = clk_get(&pdev->dev, "cfg_ahb_clk");
+	if (IS_ERR(clk)) {
+		if (PTR_ERR(clk) != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "Unable to get ahb clock handle\n");
+		return PTR_ERR(clk);
+	}
+	clk_put(clk);
+
+	regmap = qcom_cc_map(pdev, &disp_cc_khaje_desc);
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	/*
+	 * Keep the clock always-ON
+	 * DISP_CC_SLEEP_CLK, DISP_CC_XO_CLK
+	 */
+	regmap_update_bits(regmap, 0x5004, BIT(0), BIT(0));
+	regmap_update_bits(regmap, 0x5008, BIT(0), BIT(0));
+
+	clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
+
+	ret = qcom_cc_really_probe(pdev, &disp_cc_khaje_desc, regmap);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
+		return ret;
+	}
+
+	dev_info(&pdev->dev, "Registered DISP CC clocks\n");
+
+	return ret;
+}
+
+static struct platform_driver disp_cc_khaje_driver = {
+	.probe = disp_cc_khaje_probe,
+	.driver = {
+		.name = "disp_cc-khaje",
+		.of_match_table = disp_cc_khaje_match_table,
+	},
+};
+
+static int __init disp_cc_khaje_init(void)
+{
+	return platform_driver_register(&disp_cc_khaje_driver);
+}
+subsys_initcall(disp_cc_khaje_init);
+
+static void __exit disp_cc_khaje_exit(void)
+{
+	platform_driver_unregister(&disp_cc_khaje_driver);
+}
+module_exit(disp_cc_khaje_exit);
+
+MODULE_DESCRIPTION("QTI DISP_CC KHAJE Driver");

drivers/clk/qcom/gcc-sdm429w.c

@@ -42,6 +42,7 @@ enum {
 	P_GPLL6_OUT_AUX,
 	P_GPLL6_OUT_MAIN,
 	P_SLEEP_CLK,
+	P_GPLL3_OUT_MAIN_DIV,
 };
 
 static const struct parent_map gcc_parent_map_0[] = {
@@ -240,7 +241,7 @@ static const char * const gcc_parent_names_12[] = {
 static const struct parent_map gcc_parent_map_14[] = {
 	{ P_BI_TCXO, 0 },
 	{ P_GPLL0_OUT_MAIN, 1 },
-	{ P_GPLL3_OUT_MAIN, 2 },
+	{ P_GPLL3_OUT_MAIN_DIV, 2 },
 	{ P_GPLL6_OUT_AUX, 3 },
 	{ P_GPLL4_OUT_AUX, 4 },
 	{ P_CORE_BI_PLL_TEST_SE, 7 },
@@ -249,7 +250,7 @@ static const struct parent_map gcc_parent_map_14[] = {
 static const struct parent_map gcc_parent_map_14_gfx3d[] = {
 	{ P_BI_TCXO, 0 },
 	{ P_GPLL0_OUT_MAIN, 5 },
-	{ P_GPLL3_OUT_MAIN, 2 },
+	{ P_GPLL3_OUT_MAIN_DIV, 2 },
 	{ P_GPLL6_OUT_AUX, 6 },
 	{ P_GPLL4_OUT_AUX, 4 },
 	{ P_CORE_BI_PLL_TEST_SE, 7 },
@@ -258,7 +259,7 @@ static const struct parent_map gcc_parent_map_14_gfx3d[] = {
 static const char * const gcc_parent_names_14[] = {
 	"bi_tcxo",
 	"gpll0_out_main",
-	"gpll3_out_main",
+	"gpll3_out_main_div",
 	"gpll6_out_aux",
 	"gpll4_out_aux",
 	"core_bi_pll_test_se",
@@ -466,6 +467,18 @@ static struct clk_alpha_pll gpll3_out_main = {
 	},
 };
 
+static struct clk_fixed_factor gpll3_out_main_div = {
+	.mult = 1,
+	.div = 2,
+	.hw.init = &(struct clk_init_data){
+		.name = "gpll3_out_main_div",
+		.parent_names = (const char *[]){ "gpll3_out_main" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_fixed_factor_ops,
+	},
+};
+
 static struct clk_alpha_pll gpll4_out_main = {
 	.offset = 0x24000,
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
@@ -501,17 +514,6 @@ static struct clk_pll gpll6 = {
 	},
 };
 
-static struct clk_regmap gpll6_out_main = {
-	.enable_reg = 0x45000,
-	.enable_mask = BIT(7),
-	.hw.init = &(struct clk_init_data){
-		.name = "gpll6_out_main",
-		.parent_names = (const char *[]){ "gpll6" },
-		.num_parents = 1,
-		.ops = &clk_pll_vote_ops,
-	},
-};
-
 static struct clk_regmap gpll6_out_aux = {
 	.enable_reg = 0x45000,
 	.enable_mask = BIT(7),
@@ -523,6 +525,17 @@ static struct clk_regmap gpll6_out_aux = {
 	},
 };
 
+static struct clk_fixed_factor gpll6_out_main = {
+	.mult = 1,
+	.div = 1,
+	.hw.init = &(struct clk_init_data){
+		.name = "gpll6_out_main",
+		.parent_names = (const char *[]){ "gpll6_out_aux" },
+		.num_parents = 1,
+		.ops = &clk_fixed_factor_ops,
+	},
+};
+
 static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
 	F(19200000, P_BI_TCXO, 1, 0, 0),
 	F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
@@ -1258,18 +1271,18 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
 };
 
 static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
-	F(57140000, P_GPLL0_OUT_MAIN, 14, 0, 0),
+	F(57142857, P_GPLL0_OUT_MAIN, 14, 0, 0),
 	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 	F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
-	F(177780000, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
+	F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
 	{ }
 };
 
 static const struct freq_tbl ftbl_usb_hs_system_clk_src_qm215[] = {
 	F( 80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 	F( 100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
-	F( 133330000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+	F( 133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
-	F( 177780000, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
+	F( 177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
 	{ }
 };
 
@@ -1536,7 +1549,7 @@ static struct clk_rcg2 csi0_clk_src = {
 		.rate_max = (unsigned long[VDD_NUM]) {
 			[VDD_LOW] = 100000000,
 			[VDD_LOW_L1] = 200000000,
-			[VDD_NOMINAL] = 266666667},
+			[VDD_NOMINAL] = 266670000},
 	},
 };
 
@@ -1592,7 +1605,7 @@ static struct clk_rcg2 csi1_clk_src = {
 		.rate_max = (unsigned long[VDD_NUM]) {
 			[VDD_LOW] = 100000000,
 			[VDD_LOW_L1] = 200000000,
-			[VDD_NOMINAL] = 266666667},
+			[VDD_NOMINAL] = 266670000},
 	},
 };
 
@@ -1633,7 +1646,7 @@ static struct clk_rcg2 csi2_clk_src = {
 		.rate_max = (unsigned long[VDD_NUM]) {
 			[VDD_LOW] = 100000000,
 			[VDD_LOW_L1] = 200000000,
-			[VDD_NOMINAL] = 266666667},
+			[VDD_NOMINAL] = 266670000},
 	},
 };
 
@@ -1706,13 +1719,13 @@ static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
 	F_SLEW(240000000, P_GPLL6_OUT_AUX, 4.5, 0, 0, FIXED_FREQ_SRC),
 	F_SLEW(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0, FIXED_FREQ_SRC),
 	F_SLEW(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0, FIXED_FREQ_SRC),
-	F_SLEW(355200000, P_GPLL3_OUT_MAIN, 1, 0, 0, 710400000),
+	F_SLEW(355200000, P_GPLL3_OUT_MAIN_DIV, 1, 0, 0, 710400000),
-	F_SLEW(375000000, P_GPLL3_OUT_MAIN, 1, 0, 0, 750000000),
+	F_SLEW(375000000, P_GPLL3_OUT_MAIN_DIV, 1, 0, 0, 750000000),
 	F_SLEW(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0, FIXED_FREQ_SRC),
-	F_SLEW(450000000, P_GPLL3_OUT_MAIN, 1, 0, 0, 900000000),
+	F_SLEW(450000000, P_GPLL3_OUT_MAIN_DIV, 1, 0, 0, 900000000),
-	F_SLEW(510000000, P_GPLL3_OUT_MAIN, 1, 0, 0, 1020000000),
+	F_SLEW(510000000, P_GPLL3_OUT_MAIN_DIV, 1, 0, 0, 1020000000),
-	F_SLEW(560000000, P_GPLL3_OUT_MAIN, 1, 0, 0, 1120000000),
+	F_SLEW(560000000, P_GPLL3_OUT_MAIN_DIV, 1, 0, 0, 1120000000),
-	F_SLEW(650000000, P_GPLL3_OUT_MAIN, 1, 0, 0, 1300000000),
+	F_SLEW(650000000, P_GPLL3_OUT_MAIN_DIV, 1, 0, 0, 1300000000),
 	{ }
 };
 
@@ -1729,6 +1742,12 @@ static struct freq_tbl ftbl_oxili_gfx3d_clk_src_qm215[] = {
 	F_SLEW( 270000000, P_GPLL6_OUT_AUX, 4, 0, 0, FIXED_FREQ_SRC),
 	F_SLEW( 320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0, FIXED_FREQ_SRC),
 	F_SLEW( 400000000, P_GPLL0_OUT_MAIN, 2, 0, 0, FIXED_FREQ_SRC),
+	F_SLEW( 465000000, P_GPLL3_OUT_MAIN_DIV, 1, 0, 0, 930000000),
+	F_SLEW( 484800000, P_GPLL3_OUT_MAIN_DIV, 1, 0, 0, 969600000),
+	F_SLEW( 500000000, P_GPLL3_OUT_MAIN_DIV, 1, 0, 0, 1000000000),
+	F_SLEW( 523200000, P_GPLL3_OUT_MAIN_DIV, 1, 0, 0, 1046400000),
+	F_SLEW( 550000000, P_GPLL3_OUT_MAIN_DIV, 1, 0, 0, 1100000000),
+	F_SLEW( 598000000, P_GPLL3_OUT_MAIN_DIV, 1, 0, 0, 1196000000),
 	{ }
 };
 
@@ -1743,6 +1762,7 @@ static struct clk_rcg2 gfx3d_clk_src = {
 		.name = "gfx3d_clk_src",
 		.parent_names = gcc_parent_names_14,
 		.num_parents = 6,
+		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -3920,6 +3940,7 @@ static struct clk_dummy wcnss_m_clk = {
 
 struct clk_hw *gcc_sdm429w_hws[] = {
 	[GPLL0_OUT_AUX] = &gpll0_out_aux.hw,
+	[GPLL6_OUT_MAIN] = &gpll6_out_main.hw,
 };
 
 static struct clk_regmap *gcc_sdm429w_clocks[] = {
@@ -4000,7 +4021,6 @@ static struct clk_regmap *gcc_sdm429w_clocks[] = {
 	[GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
 	[GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
 	[GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
-	[GPLL6_OUT_MAIN] = &gpll6_out_main,
 	[GPLL6] = &gpll6.clkr,
 	[GPLL6_OUT_AUX] = &gpll6_out_aux,
 	[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
@@ -4246,8 +4266,8 @@ static void fixup_for_qm215(struct platform_device *pdev,
 	sdcc1_apps_clk_src.clkr.hw.init->rate_max[VDD_NOMINAL] = 400000000;
 
 	usb_hs_system_clk_src.clkr.hw.init->rate_max[VDD_LOW] = 800000000;
-	usb_hs_system_clk_src.clkr.hw.init->rate_max[VDD_NOMINAL] = 133333000;
+	usb_hs_system_clk_src.clkr.hw.init->rate_max[VDD_NOMINAL] = 133333333;
-	usb_hs_system_clk_src.clkr.hw.init->rate_max[VDD_HIGH] = 177780000;
+	usb_hs_system_clk_src.clkr.hw.init->rate_max[VDD_HIGH] = 177777778;
 	usb_hs_system_clk_src.freq_tbl = ftbl_usb_hs_system_clk_src_qm215;
 
 	/*
@@ -4267,9 +4287,19 @@ static void fixup_for_qm215(struct platform_device *pdev,
 	gcc_sdm429w_desc.clks[GCC_MDSS_ESC1_CLK] = NULL;
 }
 
+static void fixup_for_sdm439_429(void)
+{
+	/*
+	 * Below clocks are not available on SDM429/439, thus mark them NULL.
+	 */
+	gcc_sdm429w_desc.clks[GCC_GFX_TCU_CLK] = NULL;
+	gcc_sdm429w_desc.clks[GCC_GFX_TBU_CLK] = NULL;
+	gcc_sdm429w_desc.clks[GCC_GTCU_AHB_CLK] = NULL;
+}
 static const struct of_device_id gcc_sdm429w_match_table[] = {
 	{ .compatible = "qcom,gcc-sdm429w" },
 	{ .compatible = "qcom,gcc-qm215" },
+	{ .compatible = "qcom,gcc-sdm439" },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, gcc_sdm429w_match_table);
@@ -4279,11 +4309,14 @@ static int gcc_sdm429w_probe(struct platform_device *pdev)
 	struct regmap *regmap;
 	struct clk *clk;
 	int ret, speed_bin;
-	bool qm215;
+	bool qm215, is_sdm439;
 
 	qm215 = of_device_is_compatible(pdev->dev.of_node,
 						"qcom,gcc-qm215");
 
+	is_sdm439 = of_device_is_compatible(pdev->dev.of_node,
+						"qcom,gcc-sdm439");
+
 	clk = clk_get(&pdev->dev, "bi_tcxo");
 	if (IS_ERR(clk)) {
 		if (PTR_ERR(clk) != -EPROBE_DEFER)
@@ -4313,6 +4346,9 @@ static int gcc_sdm429w_probe(struct platform_device *pdev)
 				0xff0, 0xff0);
 	}
 
+	if (is_sdm439)
+		fixup_for_sdm439_429();
+
 	clk_alpha_pll_configure(&gpll3_out_main, regmap, &gpll3_config);
 
 	clk = devm_clk_register(&pdev->dev, &wcnss_m_clk.hw);
@@ -4321,6 +4357,12 @@ static int gcc_sdm429w_probe(struct platform_device *pdev)
 		return PTR_ERR(clk);
 	}
 
+	ret = devm_clk_hw_register(&pdev->dev, &gpll3_out_main_div.hw);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to register hardware clock\n");
+		return ret;
+	}
+
 	ret = qcom_cc_really_probe(pdev, &gcc_sdm429w_desc, regmap);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to register GCC clocks\n");
@@ -4380,9 +4422,22 @@ static const struct qcom_cc_desc mdss_sdm429w_desc = {
 	.num_hwclks = ARRAY_SIZE(mdss_sdm429w_hws),
 };
 
+static void fixup_for_qm215_gcc_mdss(void)
+{
+	/*
+	 * Below clocks are not available on QM215, thus mark them NULL.
+	 */
+
+	mdss_sdm429w_desc.clks[BYTE1_CLK_SRC] = NULL;
+	mdss_sdm429w_desc.clks[PCLK1_CLK_SRC] = NULL;
+	mdss_sdm429w_desc.clks[GCC_MDSS_BYTE1_CLK] = NULL;
+	mdss_sdm429w_desc.clks[GCC_MDSS_PCLK1_CLK] = NULL;
+}
+
 static const struct of_device_id mdss_sdm429w_match_table[] = {
 	{ .compatible = "qcom,gcc-mdss-sdm429w" },
-	{ .compatible = "qcom,gcc-mdss-8917" },
+	{ .compatible = "qcom,gcc-mdss-qm215" },
+	{ .compatible = "qcom,gcc-mdss-sdm439" },
 	{}
 };
 MODULE_DEVICE_TABLE(of, mdss_sdm429w_match_table);
@@ -4394,6 +4449,10 @@ static int mdss_sdm429w_probe(struct platform_device *pdev)
 	struct resource *res;
 	void __iomem *base;
 	int ret;
+	bool is_qm215;
+
+	is_qm215 = of_device_is_compatible(pdev->dev.of_node,
+			"qcom,gcc-mdss-qm215");
 
 	clk = clk_get(&pdev->dev, "pclk0_src");
 	if (IS_ERR(clk)) {
@@ -4426,6 +4485,9 @@ static int mdss_sdm429w_probe(struct platform_device *pdev)
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
+	if (is_qm215)
+		fixup_for_qm215_gcc_mdss();
+
 	ret = qcom_cc_really_probe(pdev, &mdss_sdm429w_desc, regmap);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to register MDSS clocks\n");

drivers/clk/qcom/gcc-sdm660.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2016-2017, 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2017, 2019-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/bitops.h>
@@ -1901,6 +1901,7 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
 
 static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
 	.halt_reg = 0x8a004,
+	.halt_check = BRANCH_VOTED,
 	.clkr = {
 		.enable_reg = 0x8a004,
 		.enable_mask = BIT(0),

drivers/clk/qcom/gpucc-khaje.c

@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,gpucc-khaje.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "common.h"
+#include "vdd-level-bengal.h"
+
+#define CX_GMU_CBCR_SLEEP_MASK		0xf
+#define CX_GMU_CBCR_SLEEP_SHIFT		4
+#define CX_GMU_CBCR_WAKE_MASK		0xf
+#define CX_GMU_CBCR_WAKE_SHIFT		8
+
+static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH_L1 + 1, 1, vdd_corner);
+static DEFINE_VDD_REGULATORS(vdd_mx, VDD_HIGH_L1 + 1, 1, vdd_corner);
+
+enum {
+	P_BI_TCXO,
+	P_GPLL0_OUT_MAIN,
+	P_GPLL0_OUT_MAIN_DIV,
+	P_GPU_CC_PLL0_2X_DIV_CLK_SRC,
+	P_GPU_CC_PLL0_OUT_MAIN,
+	P_GPU_CC_PLL1_OUT_EVEN,
+	P_GPU_CC_PLL1_OUT_MAIN,
+	P_GPU_CC_PLL1_OUT_ODD,
+};
+
+static const struct parent_map gpu_cc_parent_map_0[] = {
+	{ P_BI_TCXO, 0 },
+	{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
+	{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
+	{ P_GPLL0_OUT_MAIN, 5 },
+	{ P_GPLL0_OUT_MAIN_DIV, 6 },
+};
+
+static const char * const gpu_cc_parent_names_0[] = {
+	"bi_tcxo",
+	"gpu_cc_pll0_out_main",
+	"gpu_cc_pll1",
+	"gcc_gpu_gpll0_clk_src",
+	"gcc_gpu_gpll0_div_clk_src",
+};
+
+static const struct parent_map gpu_cc_parent_map_1[] = {
+	{ P_BI_TCXO, 0 },
+	{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
+	{ P_GPU_CC_PLL0_2X_DIV_CLK_SRC, 2 },
+	{ P_GPU_CC_PLL1_OUT_EVEN, 3 },
+	{ P_GPU_CC_PLL1_OUT_ODD, 4 },
+	{ P_GPLL0_OUT_MAIN, 5 },
+};
+
+static const char * const gpu_cc_parent_names_1[] = {
+	"bi_tcxo",
+	"gpu_cc_pll0_out_main",
+	"gpu_cc_pll0",
+	"gpu_cc_pll1",
+	"gpu_cc_pll1",
+	"gcc_gpu_gpll0_clk_src",
+};
+
+static struct pll_vco lucid_vco[] = {
+	{ 249600000, 2000000000, 0 },
+};
+
+static struct pll_vco zonda_vco[] = {
+	{ 595200000, 3600000000, 0 },
+};
+
+/* 640MHz configuration */
+static const struct alpha_pll_config gpu_cc_pll0_config = {
+	.l = 0x21,
+	.alpha = 0x5555,
+	.config_ctl_val = 0x08200800,
+	.config_ctl_hi_val = 0x05022001,
+	.config_ctl_hi1_val = 0x00000010,
+	.user_ctl_val = 0x01000101,
+};
+
+static struct clk_alpha_pll gpu_cc_pll0 = {
+	.offset = 0x0,
+	.vco_table = zonda_vco,
+	.num_vco = ARRAY_SIZE(zonda_vco),
+	.flags = SUPPORTS_DYNAMIC_UPDATE,
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
+	.clkr = {
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_pll0",
+			.parent_names = (const char *[]){ "bi_tcxo" },
+			.num_parents = 1,
+			.ops = &clk_alpha_pll_zonda_ops,
+			.vdd_class = &vdd_mx,
+			.num_rate_max = VDD_NUM,
+			.rate_max = (unsigned long[VDD_NUM]) {
+				[VDD_LOWER] = 1800000000,
+				[VDD_LOW] = 2400000000,
+				[VDD_NOMINAL] = 3000000000,
+				[VDD_HIGH] = 3600000000},
+		},
+	},
+};
+
+static const struct clk_div_table post_div_table_gpu_cc_pll0_out_main[] = {
+	{ 0x1, 2 },
+	{ }
+};
+
+static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_main = {
+	.offset = 0x0,
+	.post_div_shift = 8,
+	.post_div_table = post_div_table_gpu_cc_pll0_out_main,
+	.num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_main),
+	.width = 2,
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "gpu_cc_pll0_out_main",
+		.parent_names = (const char *[]){ "gpu_cc_pll0" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_alpha_pll_postdiv_ro_ops,
+	},
+};
+
+/* 690MHz configuration */
+static const struct alpha_pll_config gpu_cc_pll1_config = {
+	.l = 0x23,
+	.alpha = 0xF000,
+	.config_ctl_val = 0x20485699,
+	.config_ctl_hi_val = 0x00002261,
+	.config_ctl_hi1_val = 0x329A299C,
+	.user_ctl_val = 0x00000001,
+	.user_ctl_hi_val = 0x00000805,
+	.user_ctl_hi1_val = 0x00000000,
+};
+
+static struct clk_alpha_pll gpu_cc_pll1 = {
+	.offset = 0x100,
+	.vco_table = lucid_vco,
+	.num_vco = ARRAY_SIZE(lucid_vco),
+	.flags = SUPPORTS_DYNAMIC_UPDATE,
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+	.clkr = {
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_pll1",
+			.parent_names = (const char *[]){ "bi_tcxo" },
+			.num_parents = 1,
+			.ops = &clk_alpha_pll_lucid_ops,
+			.vdd_class = &vdd_mx,
+			.num_rate_max = VDD_NUM,
+			.rate_max = (unsigned long[VDD_NUM]) {
+				[VDD_MIN] = 615000000,
+				[VDD_LOW] = 1066000000,
+				[VDD_LOW_L1] = 1500000000,
+				[VDD_NOMINAL] = 1750000000,
+				[VDD_HIGH] = 2000000000},
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
+	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 gpu_cc_gmu_clk_src = {
+	.cmd_rcgr = 0x1120,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = gpu_cc_parent_map_0,
+	.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
+	.enable_safe_config = true,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "gpu_cc_gmu_clk_src",
+		.parent_names = gpu_cc_parent_names_0,
+		.num_parents = ARRAY_SIZE(gpu_cc_parent_names_0),
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_rcg2_ops,
+		.vdd_class = &vdd_cx,
+		.num_rate_max = VDD_NUM,
+		.rate_max = (unsigned long[VDD_NUM]) {
+			[VDD_LOWER] = 200000000},
+	},
+};
+
+static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
+	F(320000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),
+	F(465000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),
+	F(600000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),
+	F(785000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),
+	F(820000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),
+	F(980000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),
+	F(1025000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),
+	F(1100000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),
+	F(1114800000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
+	.cmd_rcgr = 0x101c,
+	.mnd_width = 0,
+	.hid_width = 5,
+	.parent_map = gpu_cc_parent_map_1,
+	.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
+	.clkr.hw.init = &(struct clk_init_data){
+		.name = "gpu_cc_gx_gfx3d_clk_src",
+		.parent_names = gpu_cc_parent_names_1,
+		.num_parents = ARRAY_SIZE(gpu_cc_parent_names_1),
+		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+		.ops = &clk_rcg2_ops,
+		.vdd_class = &vdd_cx,
+		.num_rate_max = VDD_NUM,
+		.rate_max = (unsigned long[VDD_NUM]) {
+			[VDD_LOWER] = 320000097,
+			[VDD_LOW] = 465000000,
+			[VDD_LOW_L1] = 600000000,
+			[VDD_NOMINAL] = 785088000,
+			[VDD_HIGH] = 1025088000,
+			[VDD_HIGH_L1] = 1114800000},
+	},
+};
+
+static struct clk_branch gpu_cc_ahb_clk = {
+	.halt_reg = 0x1078,
+	.halt_check = BRANCH_HALT_DELAY,
+	.clkr = {
+		.enable_reg = 0x1078,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_ahb_clk",
+			.flags = CLK_IS_CRITICAL,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_crc_ahb_clk = {
+	.halt_reg = 0x107c,
+	.halt_check = BRANCH_HALT_DELAY,
+	.clkr = {
+		.enable_reg = 0x107c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_crc_ahb_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cx_gfx3d_clk = {
+	.halt_reg = 0x10a4,
+	.halt_check = BRANCH_HALT_DELAY,
+	.clkr = {
+		.enable_reg = 0x10a4,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cx_gfx3d_clk",
+			.parent_names = (const char *[]){
+				"gpu_cc_gx_gfx3d_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cx_gmu_clk = {
+	.halt_reg = 0x1098,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1098,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cx_gmu_clk",
+			.parent_names = (const char *[]){
+				"gpu_cc_gmu_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
+	.halt_reg = 0x108c,
+	.halt_check = BRANCH_HALT_DELAY,
+	.clkr = {
+		.enable_reg = 0x108c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cx_snoc_dvm_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cxo_aon_clk = {
+	.halt_reg = 0x1004,
+	.halt_check = BRANCH_HALT_DELAY,
+	.clkr = {
+		.enable_reg = 0x1004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cxo_aon_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_cxo_clk = {
+	.halt_reg = 0x109c,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x109c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_cxo_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_gx_gfx3d_clk = {
+	.halt_reg = 0x1054,
+	.halt_check = BRANCH_HALT_SKIP,
+	.clkr = {
+		.enable_reg = 0x1054,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_gx_gfx3d_clk",
+			.parent_names = (const char *[]){
+				"gpu_cc_gx_gfx3d_clk_src",
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_sleep_clk = {
+	.halt_reg = 0x1090,
+	.halt_check = BRANCH_HALT_DELAY,
+	.clkr = {
+		.enable_reg = 0x1090,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gpu_cc_sleep_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
+	.halt_reg = 0x5000,
+	.halt_check = BRANCH_VOTED,
+	.clkr = {
+		.enable_reg = 0x5000,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			 .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
+			 .ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_regmap *gpu_cc_khaje_clocks[] = {
+	[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
+	[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
+	[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
+	[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
+	[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
+	[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
+	[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
+	[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
+	[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
+	[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
+	[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
+	[GPU_CC_PLL0_OUT_MAIN] = &gpu_cc_pll0_out_main.clkr,
+	[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
+	[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
+	[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
+};
+
+static const struct regmap_config gpu_cc_khaje_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x7008,
+	.fast_io = true,
+};
+
+static const struct qcom_cc_desc gpu_cc_khaje_desc = {
+	.config = &gpu_cc_khaje_regmap_config,
+	.clks = gpu_cc_khaje_clocks,
+	.num_clks = ARRAY_SIZE(gpu_cc_khaje_clocks),
+};
+
+static const struct of_device_id gpu_cc_khaje_match_table[] = {
+	{ .compatible = "qcom,khaje-gpucc" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, gpu_cc_khaje_match_table);
+
+static int gpu_cc_khaje_probe(struct platform_device *pdev)
+{
+	struct regmap *regmap;
+	unsigned int value, mask;
+	int ret;
+
+	vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");
+	if (IS_ERR(vdd_cx.regulator[0])) {
+		if (PTR_ERR(vdd_cx.regulator[0]) != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "Unable to get vdd_cx regulator\n");
+		return PTR_ERR(vdd_cx.regulator[0]);
+	}
+
+	vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx");
+	if (IS_ERR(vdd_mx.regulator[0])) {
+		if (PTR_ERR(vdd_mx.regulator[0]) != -EPROBE_DEFER)
+			dev_err(&pdev->dev, "Unable to get vdd_mx regulator\n");
+		return PTR_ERR(vdd_mx.regulator[0]);
+	}
+
+	regmap = qcom_cc_map(pdev, &gpu_cc_khaje_desc);
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	/*
+	 * Keep the clock always-ON
+	 * GPU_CC_GX_CXO_CLK
+	 */
+	regmap_update_bits(regmap, 0x1060, BIT(0), BIT(0));
+
+	clk_zonda_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
+	clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
+
+	/* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
+	mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
+	mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
+	value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
+	regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg,
+								mask, value);
+
+	ret = qcom_cc_really_probe(pdev, &gpu_cc_khaje_desc, regmap);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to register GPUCC clocks\n");
+		return ret;
+	}
+
+	dev_info(&pdev->dev, "Registered GPU CC clocks\n");
+
+	return ret;
+}
+
+static struct platform_driver gpu_cc_khaje_driver = {
+	.probe = gpu_cc_khaje_probe,
+	.driver = {
+		.name = "gpu_cc-khaje",
+		.of_match_table = gpu_cc_khaje_match_table,
+	},
+};
+
+static int __init gpu_cc_khaje_init(void)
+{
+	return platform_driver_register(&gpu_cc_khaje_driver);
+}
+subsys_initcall(gpu_cc_khaje_init);
+
+static void __exit gpu_cc_khaje_exit(void)
+{
+	platform_driver_unregister(&gpu_cc_khaje_driver);
+}
+module_exit(gpu_cc_khaje_exit);
+
+MODULE_DESCRIPTION("QTI GPU_CC KHAJE Driver");
+MODULE_LICENSE("GPL v2");

drivers/clk/qcom/gpucc-sdm660.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/bitops.h>

drivers/clk/qcom/mdss/mdss-dsi-pll-12nm-util.c

@@ -15,17 +15,32 @@
 #define DSI_PLL_POLL_MAX_READS                  15
 #define DSI_PLL_POLL_TIMEOUT_US                 1000
 
+static void __mdss_dsi_get_pll_vco_cntrl(u64 target_freq, u32 post_div_mux,
+	u32 *vco_cntrl, u32 *cpbias_cntrl);
+
 int pixel_div_set_div(void *context, unsigned int reg,
 			unsigned int div)
 {
 	struct mdss_pll_resources *pll = context;
+	void __iomem *pll_base = pll->pll_base;
+	int rc;
+	char data = 0;
 	struct dsi_pll_db *pdb;
 
 	pdb = (struct dsi_pll_db *)pll->priv;
+	rc = mdss_pll_resource_enable(pll, true);
+	if (rc) {
+		pr_err("Failed to enable mdss dsi pll resources\n");
+		return rc;
+	}
 
 	/* Programming during vco_prepare. Keep this value */
-	pdb->param.pixel_divhf = (div - 1);
+	data = (div & 0x7f);
+	MDSS_PLL_REG_W(pll_base, DSIPHY_SSC9, data);
+	pdb->param.pixel_divhf = data;
+	pll->cached_postdiv3 = data;
 
+	mdss_pll_resource_enable(pll, false);
 	pr_debug("ndx=%d div=%d divhf=%d\n",
 			pll->index, div, pdb->param.pixel_divhf);
 
@@ -37,6 +52,7 @@ int pixel_div_get_div(void *context, unsigned int reg,
 {
 	int rc;
 	struct mdss_pll_resources *pll = context;
+	u32 val = 0;
 
 	if (is_gdsc_disabled(pll))
 		return 0;
@@ -47,8 +63,9 @@ int pixel_div_get_div(void *context, unsigned int reg,
 		return rc;
 	}
 
-	*div = (MDSS_PLL_REG_R(pll->pll_base, DSIPHY_SSC9) & 0x7F);
+	val = (MDSS_PLL_REG_R(pll->pll_base, DSIPHY_SSC9) & 0x7F);
-	pr_debug("pixel_div = %d\n", (*div+1));
+	*div = val;
+	pr_debug("pixel_div = %d\n", (*div));
 
 	mdss_pll_resource_enable(pll, false);
 
@@ -59,13 +76,33 @@ int set_post_div_mux_sel(void *context, unsigned int reg,
 			unsigned int sel)
 {
 	struct mdss_pll_resources *pll = context;
+	void __iomem *pll_base = pll->pll_base;
 	struct dsi_pll_db *pdb;
+	u64 target_freq = 0;
+	u32 vco_cntrl = 0, cpbias_cntrl = 0;
+	char data = 0;
 
 	pdb = (struct dsi_pll_db *)pll->priv;
 
 	/* Programming during vco_prepare. Keep this value */
 	pdb->param.post_div_mux = sel;
 
+	target_freq = div_u64(pll->vco_current_rate,
+		BIT(pdb->param.post_div_mux));
+	__mdss_dsi_get_pll_vco_cntrl(target_freq, pdb->param.post_div_mux,
+		&vco_cntrl, &cpbias_cntrl);
+
+	data = ((vco_cntrl & 0x3f) | BIT(6));
+	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_VCO_CTRL, data);
+	pr_debug("%s: vco_cntrl 0x%x\n", __func__, vco_cntrl);
+	pll->cached_cfg0 = data;
+	wmb(); /* make sure register committed before preparing the clocks */
+
+	data = ((cpbias_cntrl & 0x1) << 6) | BIT(4);
+	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_CHAR_PUMP_BIAS_CTRL, data);
+	pr_debug("%s: cpbias_cntrl 0x%x\n", __func__, cpbias_cntrl);
+
+	pll->cached_cfg1 = data;
 	pr_debug("ndx=%d post_div_mux_sel=%d p_div=%d\n",
 			pll->index, sel, (u32) BIT(sel));
 
@@ -90,6 +127,7 @@ int get_post_div_mux_sel(void *context, unsigned int reg,
 
 	vco_cntrl = MDSS_PLL_REG_R(pll->pll_base, DSIPHY_PLL_VCO_CTRL);
 	vco_cntrl &= 0x30;
+	pr_debug("%s: vco_cntrl 0x%x\n", __func__, vco_cntrl);
 
 	cpbias_cntrl = MDSS_PLL_REG_R(pll->pll_base,
 		DSIPHY_PLL_CHAR_PUMP_BIAS_CTRL);
@@ -112,6 +150,7 @@ int get_post_div_mux_sel(void *context, unsigned int reg,
 	}
 
 	mdss_pll_resource_enable(pll, false);
+	pr_debug("%s: sel = %d\n", __func__, *sel);
 
 	return 0;
 }
@@ -120,16 +159,25 @@ int set_gp_mux_sel(void *context, unsigned int reg,
 			unsigned int sel)
 {
 	struct mdss_pll_resources *pll = context;
-	struct dsi_pll_db *pdb;
+	void __iomem *pll_base = pll->pll_base;
+	char data = 0;
+	int rc;
 
-	pdb = (struct dsi_pll_db *)pll->priv;
+	rc = mdss_pll_resource_enable(pll, true);
+	if (rc) {
+		pr_err("Failed to enable mdss dsi pll resources\n");
+		return rc;
+	}
 
 	/* Programming during vco_prepare. Keep this value */
-	pdb->param.gp_div_mux = sel;
+	data = ((sel & 0x7) << 5) | 0x5;
+	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_CTRL, data);
+	pll->cached_postdiv1 = data;
 
 	pr_debug("ndx=%d gp_div_mux_sel=%d gp_cntrl=%d\n",
 			pll->index, sel, (u32) BIT(sel));
 
+	mdss_pll_resource_enable(pll, false);
 	return 0;
 }
 
@@ -175,7 +223,9 @@ static bool pll_is_pll_locked_12nm(struct mdss_pll_resources *pll,
 			pr_err("DSI PLL ndx=%d status=%x failed to Lock\n",
 				pll->index, status);
 		pll_locked = false;
+		pr_debug("%s: not locked\n", __func__);
 	} else {
+		pr_debug("%s: locked\n", __func__);
 		pll_locked = true;
 	}
 
@@ -542,13 +592,13 @@ static void mdss_dsi_pll_12nm_calc_reg(struct mdss_pll_resources *pll,
 {
 	struct dsi_pll_param *param = &pdb->param;
 	u64 target_freq = 0;
+	u32 post_div_mux = 0;
 
+	get_post_div_mux_sel(pll, 0, &post_div_mux);
 	target_freq = div_u64(pll->vco_current_rate,
-		BIT(pdb->param.post_div_mux));
+		BIT(post_div_mux));
 
 	param->hsfreqrange = __mdss_dsi_get_hsfreqrange(target_freq);
-	__mdss_dsi_get_pll_vco_cntrl(target_freq, param->post_div_mux,
-		&param->vco_cntrl, &param->cpbias_cntrl);
 	param->osc_freq_target = __mdss_dsi_get_osc_freq_target(target_freq);
 	param->m_div = (u32) __mdss_dsi_pll_get_m_div(pll->vco_current_rate);
 	param->fsm_ovr_ctrl = __mdss_dsi_get_fsm_ovr_ctrl(target_freq);
@@ -707,9 +757,6 @@ static void pll_db_commit_12nm(struct mdss_pll_resources *pll,
 	data = ((param->hsfreqrange & 0x7f) | BIT(7));
 	MDSS_PLL_REG_W(pll_base, DSIPHY_HS_FREQ_RAN_SEL, data);
 
-	data = ((param->vco_cntrl & 0x3f) | BIT(6));
-	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_VCO_CTRL, data);
-
 	data = (param->osc_freq_target & 0x7f);
 	MDSS_PLL_REG_W(pll_base, DSIPHY_SLEWRATE_DDL_CYC_FRQ_ADJ_0, data);
 
@@ -733,15 +780,6 @@ static void pll_db_commit_12nm(struct mdss_pll_resources *pll,
 	data = ((param->gmp_cntrl & 0x3) << 4);
 	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_GMP_CTRL_DIG_TST, data);
 
-	data = ((param->cpbias_cntrl & 0x1) << 6) | BIT(4);
-	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_CHAR_PUMP_BIAS_CTRL, data);
-
-	data = ((param->gp_div_mux & 0x7) << 5) | 0x5;
-	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_CTRL, data);
-
-	data = (param->pixel_divhf & 0x7f);
-	MDSS_PLL_REG_W(pll_base, DSIPHY_SSC9, data);
-
 	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_ANA_PROG_CTRL, 0x03);
 	MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_ANA_TST_LOCK_ST_OVR_CTRL, 0x50);
 	MDSS_PLL_REG_W(pll_base,
@@ -779,6 +817,14 @@ int pll_vco_set_rate_12nm(struct clk_hw *hw, unsigned long rate,
 
 	pll->vco_current_rate = rate;
 	pll->vco_ref_clk_rate = vco->ref_clk_rate;
+
+	mdss_dsi_pll_12nm_calc_reg(pll, pdb);
+	if (pll->ssc_en)
+		mdss_dsi_pll_12nm_calc_ssc(pll, pdb);
+
+	/* commit DSI vco  */
+	pll_db_commit_12nm(pll, pdb);
+
 error:
 	return rc;
 }
@@ -791,9 +837,13 @@ static unsigned long pll_vco_get_rate_12nm(struct clk_hw *hw)
 	u64 ref_clk = vco->ref_clk_rate;
 	int rc;
 	struct mdss_pll_resources *pll = vco->priv;
+	u32 post_div_mux;
+	u32 cpbias_cntrl = 0;
 
-	if (is_gdsc_disabled(pll))
+	if (is_gdsc_disabled(pll)) {
+		pr_err("%s:gdsc disabled\n", __func__);
 		return 0;
+	}
 
 	rc = mdss_pll_resource_enable(pll, true);
 	if (rc) {
@@ -811,6 +861,16 @@ static unsigned long pll_vco_get_rate_12nm(struct clk_hw *hw)
 	m_div_11_6 &= 0x3f;
 	pr_debug("m_div_11_6 = 0x%x\n", m_div_11_6);
 
+	post_div_mux = MDSS_PLL_REG_R(pll->pll_base,
+			DSIPHY_PLL_VCO_CTRL);
+
+	pr_debug("post_div_mux = 0x%x\n", post_div_mux);
+
+	cpbias_cntrl = MDSS_PLL_REG_R(pll->pll_base,
+		DSIPHY_PLL_CHAR_PUMP_BIAS_CTRL);
+	cpbias_cntrl = ((cpbias_cntrl >> 6) & 0x1);
+	pr_debug("cpbias_cntrl = 0x%x\n", cpbias_cntrl);
+
 	m_div = ((m_div_11_6 << 6) | (m_div_5_0));
 
 	vco_rate = div_u64((ref_clk * m_div), 4);
@@ -845,12 +905,21 @@ unsigned long vco_12nm_recalc_rate(struct clk_hw *hw,
 	struct mdss_pll_resources *pll = vco->priv;
 	unsigned long rate = 0;
 	int rc;
+	struct dsi_pll_db *pdb;
+
+	pdb = (struct dsi_pll_db *)pll->priv;
 
 	if (!pll && is_gdsc_disabled(pll)) {
 		pr_err("gdsc disabled\n");
 		return 0;
 	}
 
+	if (pll->vco_current_rate != 0) {
+		pr_debug("%s:returning vco rate = %lld\n", __func__,
+				pll->vco_current_rate);
+		return pll->vco_current_rate;
+	}
+
 	rc = mdss_pll_resource_enable(pll, true);
 	if (rc) {
 		pr_err("Failed to enable mdss dsi pll=%d\n", pll->index);
@@ -861,6 +930,7 @@ unsigned long vco_12nm_recalc_rate(struct clk_hw *hw,
 		pll->handoff_resources = true;
 		pll->pll_on = true;
 		rate = pll_vco_get_rate_12nm(hw);
+		pr_debug("%s: pll locked. rate %lu\n", __func__, rate);
 	} else {
 		mdss_pll_resource_enable(pll, false);
 	}
@@ -881,6 +951,13 @@ int pll_vco_prepare_12nm(struct clk_hw *hw)
 		return -EINVAL;
 	}
 
+	/* Skip vco recalculation for continuous splash use case */
+	if (pll->handoff_resources) {
+		pr_debug("%s: Skip recalculation during cont splash\n",
+						__func__);
+		return rc;
+	}
+
 	pdb = (struct dsi_pll_db *)pll->priv;
 	if (!pdb) {
 		pr_err("No prov found\n");
@@ -905,6 +982,22 @@ int pll_vco_prepare_12nm(struct clk_hw *hw)
 		}
 	}
 
+	if (!pll->handoff_resources) {
+		pr_debug("%s ndx = %d cache PLL regs\n", __func__, pll->index);
+		MDSS_PLL_REG_W(pll->pll_base,
+			DSIPHY_PLL_VCO_CTRL, pll->cached_cfg0);
+		udelay(1);
+		MDSS_PLL_REG_W(pll->pll_base,
+			DSIPHY_PLL_CHAR_PUMP_BIAS_CTRL, pll->cached_cfg1);
+		udelay(1);
+		MDSS_PLL_REG_W(pll->pll_base,
+			 DSIPHY_PLL_CTRL, pll->cached_postdiv1);
+		udelay(1);
+		MDSS_PLL_REG_W(pll->pll_base,
+			 DSIPHY_SSC9, pll->cached_postdiv3);
+		udelay(5); /* h/w recommended delay */
+	}
+
 	/*
 	 * For cases where  DSI PHY is already enabled like:
 	 * 1.) LP-11 during static screen
@@ -921,15 +1014,7 @@ int pll_vco_prepare_12nm(struct clk_hw *hw)
 			goto end;
 	}
 
-	mdss_dsi_pll_12nm_calc_reg(pll, pdb);
-	if (pll->ssc_en)
-		mdss_dsi_pll_12nm_calc_ssc(pll, pdb);
-
-	/* commit DSI vco  */
-	pll_db_commit_12nm(pll, pdb);
-
 	rc = dsi_pll_enable(hw);
-
 error:
 	if (rc) {
 		mdss_pll_resource_enable(pll, false);
@@ -951,6 +1036,12 @@ void pll_vco_unprepare_12nm(struct clk_hw *hw)
 	}
 
 	pll->vco_cached_rate = clk_hw_get_rate(hw);
+
+	pll->cached_cfg0 = MDSS_PLL_REG_R(pll->pll_base, DSIPHY_PLL_VCO_CTRL);
+	pll->cached_cfg1 = MDSS_PLL_REG_R(pll->pll_base,
+					DSIPHY_PLL_CHAR_PUMP_BIAS_CTRL);
+	pll->cached_postdiv1 = MDSS_PLL_REG_R(pll->pll_base, DSIPHY_PLL_CTRL);
+	pll->cached_postdiv3 = MDSS_PLL_REG_R(pll->pll_base, DSIPHY_SSC9);
 	dsi_pll_disable(hw);
 }
 

drivers/clk/qcom/mdss/mdss-dsi-pll-12nm.c

@@ -27,6 +27,7 @@ static const struct clk_ops clk_ops_vco_12nm = {
 	.round_rate = pll_vco_round_rate_12nm,
 	.prepare = pll_vco_prepare_12nm,
 	.unprepare = pll_vco_unprepare_12nm,
+	.enable = pll_vco_enable_12nm,
 };
 
 static struct regmap_bus pclk_div_regmap_bus = {
@@ -206,8 +207,8 @@ static struct clk_fixed_factor dsi0pll_post_div32 = {
 
 static struct clk_regmap_mux dsi0pll_post_div_mux = {
 	.reg = DSIPHY_PLL_VCO_CTRL,
-	.shift = 4,
+	.shift = 0,
-	.width = 2,
+	.width = 3,
 	.clkr = {
 		.hw.init = &(struct clk_init_data){
 			.name = "dsi0pll_post_div_mux",
@@ -298,8 +299,8 @@ static struct clk_fixed_factor dsi1pll_post_div32 = {
 
 static struct clk_regmap_mux dsi1pll_post_div_mux = {
 	.reg = DSIPHY_PLL_VCO_CTRL,
-	.shift = 4,
+	.shift = 0,
-	.width = 2,
+	.width = 3,
 	.clkr = {
 		.hw.init = &(struct clk_init_data){
 			.name = "dsi1pll_post_div_mux",
@@ -390,7 +391,7 @@ static struct clk_fixed_factor dsi0pll_gp_div32 = {
 
 static struct clk_regmap_mux dsi0pll_gp_div_mux = {
 	.reg = DSIPHY_PLL_CTRL,
-	.shift = 5,
+	.shift = 0,
 	.width = 3,
 	.clkr = {
 		.hw.init = &(struct clk_init_data){
@@ -482,7 +483,7 @@ static struct clk_fixed_factor dsi1pll_gp_div32 = {
 
 static struct clk_regmap_mux dsi1pll_gp_div_mux = {
 	.reg = DSIPHY_PLL_CTRL,
-	.shift = 5,
+	.shift = 0,
 	.width = 3,
 	.clkr = {
 		.hw.init = &(struct clk_init_data){
@@ -503,10 +504,10 @@ static struct clk_regmap_mux dsi1pll_gp_div_mux = {
 static struct clk_regmap_div dsi0pll_pclk_src = {
 	.reg = DSIPHY_SSC9,
 	.shift = 0,
-	.width = 6,
+	.width = 3,
 	.clkr = {
 		.hw.init = &(struct clk_init_data){
-			.name = "dsi0pll_pclk_src",
+			.name = "dsi0_phy_pll_out_dsiclk",
 			.parent_names = (const char *[]){
 					"dsi0pll_gp_div_mux"},
 			.num_parents = 1,
@@ -519,10 +520,10 @@ static struct clk_regmap_div dsi0pll_pclk_src = {
 static struct clk_regmap_div dsi1pll_pclk_src = {
 	.reg = DSIPHY_SSC9,
 	.shift = 0,
-	.width = 6,
+	.width = 3,
 	.clkr = {
 		.hw.init = &(struct clk_init_data){
-			.name = "dsi1pll_pclk_src",
+			.name = "dsi1_phy_pll_out_dsiclk",
 			.parent_names = (const char *[]){
 					"dsi1pll_gp_div_mux"},
 			.num_parents = 1,
@@ -536,7 +537,7 @@ static struct clk_fixed_factor dsi0pll_byte_clk_src = {
 	.div = 4,
 	.mult = 1,
 	.hw.init = &(struct clk_init_data){
-		.name = "dsi0pll_byte_clk_src",
+		.name = "dsi0_phy_pll_out_byteclk",
 		.parent_names = (const char *[]){"dsi0pll_post_div_mux"},
 		.num_parents = 1,
 		.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
@@ -548,7 +549,7 @@ static struct clk_fixed_factor dsi1pll_byte_clk_src = {
 	.div = 4,
 	.mult = 1,
 	.hw.init = &(struct clk_init_data){
-		.name = "dsi1pll_byte_clk_src",
+		.name = "dsi1_phy_pll_out_byteclk",
 		.parent_names = (const char *[]){"dsi1pll_post_div_mux"},
 		.num_parents = 1,
 		.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
@@ -556,7 +557,6 @@ static struct clk_fixed_factor dsi1pll_byte_clk_src = {
 	},
 };
 
-
 static struct clk_hw *mdss_dsi_pllcc_12nm[] = {
 	[VCO_CLK_0] = &dsi0pll_vco_clk.hw,
 	[POST_DIV1_0_CLK] = &dsi0pll_post_div1.hw,
@@ -598,14 +598,14 @@ int dsi_pll_clock_register_12nm(struct platform_device *pdev,
 				  struct mdss_pll_resources *pll_res)
 {
 	int rc = 0, ndx, i;
-	struct clk *clk;
+	struct clk *clk = NULL;
 	struct clk_onecell_data *clk_data;
 	int num_clks = ARRAY_SIZE(mdss_dsi_pllcc_12nm);
 	struct regmap *rmap;
 	struct dsi_pll_db *pdb;
 
 	if (!pdev || !pdev->dev.of_node ||
-		!pll_res || !pll_res->pll_base || !pll_res->phy_base) {
+		!pll_res || !pll_res->pll_base) {
 		pr_err("Invalid params\n");
 		return -EINVAL;
 	}
@@ -637,7 +637,7 @@ int dsi_pll_clock_register_12nm(struct platform_device *pdev,
 	clk_data->clk_num = num_clks;
 
 	/* Establish client data */
-	if (ndx == 0) {
+	if (pll_res->index == 0) {
 		rmap = devm_regmap_init(&pdev->dev, &post_div_mux_regmap_bus,
 				pll_res, &dsi_pll_12nm_config);
 		dsi0pll_post_div_mux.clkr.regmap = rmap;
@@ -700,8 +700,8 @@ int dsi_pll_clock_register_12nm(struct platform_device *pdev,
 				of_clk_src_onecell_get, clk_data);
 	}
 	if (!rc) {
-		pr_info("Registered DSI PLL ndx=%d,clocks successfully\n", ndx);
+		pr_info("Registered DSI PLL ndx=%d, clocks successfully\n",
-
+				pll_res->index);
 		return rc;
 	}
 clk_register_fail:

drivers/clk/qcom/mdss/mdss-dsi-pll-28lpm.c

@@ -17,7 +17,7 @@
 #include <linux/kernel.h>
 #include <linux/err.h>
 #include <linux/delay.h>
-#include <dt-bindings/clock/mdss-28nm-pll-clk.h>
+#include <dt-bindings/clock/mdss-28nm-pll-clk-legacy.h>
 
 #include "mdss-pll.h"
 #include "mdss-dsi-pll.h"
@@ -388,13 +388,13 @@ static struct clk_regmap_div dsi1pll_pclk_src = {
 };
 
 static struct clk_hw *mdss_dsi_pllcc_28lpm[] = {
-	[VCO_CLK_0] = &dsi0pll_vco_clk.hw,
+	[VCOCLK_0] = &dsi0pll_vco_clk.hw,
 	[ANALOG_POSTDIV_0_CLK] = &dsi0pll_analog_postdiv.clkr.hw,
 	[INDIRECT_PATH_SRC_0_CLK] = &dsi0pll_indirect_path_src.hw,
 	[BYTECLK_SRC_MUX_0_CLK] = &dsi0pll_byteclk_src_mux.clkr.hw,
 	[BYTECLK_SRC_0_CLK] = &dsi0pll_byteclk_src.hw,
 	[PCLK_SRC_0_CLK] = &dsi0pll_pclk_src.clkr.hw,
-	[VCO_CLK_1] = &dsi1pll_vco_clk.hw,
+	[VCOCLK_1] = &dsi1pll_vco_clk.hw,
 	[ANALOG_POSTDIV_1_CLK] = &dsi1pll_analog_postdiv.clkr.hw,
 	[INDIRECT_PATH_SRC_1_CLK] = &dsi1pll_indirect_path_src.hw,
 	[BYTECLK_SRC_MUX_1_CLK] = &dsi1pll_byteclk_src_mux.clkr.hw,
@@ -486,7 +486,7 @@ int dsi_pll_clock_register_28lpm(struct platform_device *pdev,
 		dsi0pll_pclk_src.clkr.regmap = rmap;
 
 		dsi0pll_vco_clk.priv = pll_res;
-		for (i = VCO_CLK_0; i <= PCLK_SRC_0_CLK; i++) {
+		for (i = VCOCLK_0; i <= PCLK_SRC_0_CLK; i++) {
 			clk = devm_clk_register(&pdev->dev,
 						mdss_dsi_pllcc_28lpm[i]);
 			if (IS_ERR(clk)) {
@@ -531,7 +531,7 @@ int dsi_pll_clock_register_28lpm(struct platform_device *pdev,
 		dsi1pll_pclk_src.clkr.regmap = rmap;
 
 		dsi1pll_vco_clk.priv = pll_res;
-		for (i = VCO_CLK_1; i <= PCLK_SRC_1_CLK; i++) {
+		for (i = VCOCLK_1; i <= PCLK_SRC_1_CLK; i++) {
 			clk = devm_clk_register(&pdev->dev,
 						mdss_dsi_pllcc_28lpm[i]);
 			if (IS_ERR(clk)) {

drivers/clk/qcom/mdss/mdss-pll.c

@@ -128,7 +128,9 @@ static int mdss_pll_resource_parse(struct platform_device *pdev,
 		pll_res->pll_interface_type = MDSS_DP_PLL_14NM;
 		pll_res->target_id = MDSS_PLL_TARGET_SDM660;
 		pll_res->revision = 2;
-	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_28lpm"))
+	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_12nm"))
+		pll_res->pll_interface_type = MDSS_DSI_PLL_12NM;
+	else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_28lpm"))
 		pll_res->pll_interface_type = MDSS_DSI_PLL_28LPM;
 	else
 		goto err;

drivers/clk/qcom/mdss/mdss-pll.h

@@ -220,12 +220,13 @@ static inline bool is_gdsc_disabled(struct mdss_pll_resources *pll_res)
 		return true;
 	}
 	if ((pll_res->target_id == MDSS_PLL_TARGET_SDM660) ||
-			(pll_res->pll_interface_type == MDSS_DSI_PLL_28LPM))
+			(pll_res->pll_interface_type == MDSS_DSI_PLL_28LPM) ||
+			(pll_res->pll_interface_type == MDSS_DSI_PLL_12NM))
 		ret = ((readl_relaxed(pll_res->gdsc_base + 0x4) & BIT(31)) &&
 		(!(readl_relaxed(pll_res->gdsc_base) & BIT(0)))) ? false : true;
 	else
 		ret = readl_relaxed(pll_res->gdsc_base) & BIT(31) ?
-			 false : true;
+			false : true;
 	return ret;
 }
 

drivers/clk/qcom/mmcc-sdm660.c

@@ -2798,7 +2798,7 @@ static struct clk_branch mmss_snoc_dvm_axi_clk = {
 
 static struct clk_branch mmss_video_ahb_clk = {
 	.halt_reg = 0x1030,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_VOTED,
 	.clkr = {
 		.enable_reg = 0x1030,
 		.enable_mask = BIT(0),

drivers/cpuidle/lpm-levels-of.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 
 /*
- * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2019,2021, The Linux Foundation. All rights reserved.
  */
 
 #define pr_fmt(fmt) "%s: " fmt, KBUILD_MODNAME
@@ -638,6 +638,7 @@ struct lpm_cluster *parse_cluster(struct device_node *node,
 	if (ret)
 		return NULL;
 
+	INIT_LIST_HEAD(&c->list);
 	INIT_LIST_HEAD(&c->child);
 	INIT_LIST_HEAD(&c->cpu);
 	c->parent = parent;

drivers/crypto/msm/ice.c

@@ -2,7 +2,7 @@
 /*
  * QTI Inline Crypto Engine (ICE) driver
  *
- * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2020, 2021 The Linux Foundation. All rights reserved.
  */
 
 #include <linux/module.h>
@@ -59,6 +59,8 @@
 #define ICE_CRYPTO_CXT_FDE 1
 #define ICE_CRYPTO_CXT_FBE 2
 
+#define ICE_FDE_KEY_INDEX 31
+
 static int ice_fde_flag;
 
 struct ice_clk_info {
@@ -103,6 +105,11 @@ static int qti_ice_setting_config(struct request *req,
 			setting->encr_bypass = true;
 			setting->decr_bypass = true;
 		}
+		/* Qseecom now sets the FDE key to slot 31 by default, instead
+		 * of slot 0, so use the same slot here during read/write
+		 */
+		if (cxt == ICE_CRYPTO_CXT_FDE)
+			setting->crypto_data.key_index = ICE_FDE_KEY_INDEX;
 	}
 
 	return 0;

drivers/dma-buf/dma-buf.c

@@ -102,35 +102,12 @@ static char *dmabuffs_dname(struct dentry *dentry, char *buffer, int buflen)
 			     dentry->d_name.name, ret > 0 ? name : "");
 }
 
-static const struct dentry_operations dma_buf_dentry_ops = {
+static void dma_buf_release(struct dentry *dentry)
-	.d_dname = dmabuffs_dname,
-};
-
-static struct vfsmount *dma_buf_mnt;
-
-static struct dentry *dma_buf_fs_mount(struct file_system_type *fs_type,
-		int flags, const char *name, void *data)
-{
-	return mount_pseudo(fs_type, "dmabuf:", NULL, &dma_buf_dentry_ops,
-			DMA_BUF_MAGIC);
-}
-
-static struct file_system_type dma_buf_fs_type = {
-	.name = "dmabuf",
-	.mount = dma_buf_fs_mount,
-	.kill_sb = kill_anon_super,
-};
-
-static int dma_buf_release(struct inode *inode, struct file *file)
 {
 	struct dma_buf *dmabuf;
-	struct dentry *dentry = file->f_path.dentry;
 	int dtor_ret = 0;
 
-	if (!is_dma_buf_file(file))
+	dmabuf = dentry->d_fsdata;
-		return -EINVAL;
-
-	dmabuf = file->private_data;
 
 	spin_lock(&dentry->d_lock);
 	dentry->d_fsdata = NULL;
@@ -167,9 +144,28 @@ static int dma_buf_release(struct inode *inode, struct file *file)
 
 	module_put(dmabuf->owner);
 	dmabuf_dent_put(dmabuf);
-	return 0;
 }
 
+static const struct dentry_operations dma_buf_dentry_ops = {
+	.d_dname = dmabuffs_dname,
+	.d_release = dma_buf_release,
+};
+
+static struct vfsmount *dma_buf_mnt;
+
+static struct dentry *dma_buf_fs_mount(struct file_system_type *fs_type,
+		int flags, const char *name, void *data)
+{
+	return mount_pseudo(fs_type, "dmabuf:", NULL, &dma_buf_dentry_ops,
+			DMA_BUF_MAGIC);
+}
+
+static struct file_system_type dma_buf_fs_type = {
+	.name = "dmabuf",
+	.mount = dma_buf_fs_mount,
+	.kill_sb = kill_anon_super,
+};
+
 static int dma_buf_mmap_internal(struct file *file, struct vm_area_struct *vma)
 {
 	struct dma_buf *dmabuf;
@@ -488,7 +484,6 @@ static void dma_buf_show_fdinfo(struct seq_file *m, struct file *file)
 }
 
 static const struct file_operations dma_buf_fops = {
-	.release	= dma_buf_release,
 	.mmap		= dma_buf_mmap_internal,
 	.llseek		= dma_buf_llseek,
 	.poll		= dma_buf_poll,

drivers/extcon/extcon.c

@@ -1324,8 +1324,10 @@ int extcon_dev_register(struct extcon_dev *edev)
 		goto err_dev;
 	}
 
-	for (index = 0; index < edev->max_supported; index++)
+	for (index = 0; index < edev->max_supported; index++) {
 		RAW_INIT_NOTIFIER_HEAD(&edev->nh[index]);
+		BLOCKING_INIT_NOTIFIER_HEAD(&edev->bnh[index]);
+	}
 
 	RAW_INIT_NOTIFIER_HEAD(&edev->nh_all);
 

drivers/gpu/msm/Makefile

@@ -17,7 +17,8 @@ msm_kgsl_core-y = \
 	kgsl_rgmu.o \
 	kgsl_hfi.o \
 	kgsl_pool.o \
-	kgsl_reclaim.o
+	kgsl_reclaim.o \
+	kgsl_timeline.o
 
 msm_kgsl_core-$(CONFIG_QCOM_KGSL_IOMMU) += kgsl_iommu.o
 msm_kgsl_core-$(CONFIG_DEBUG_FS) += kgsl_debugfs.o

drivers/gpu/msm/adreno-gpulist.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2002,2007-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2002,2007-2021, The Linux Foundation. All rights reserved.
  */
 
 #define ANY_ID (~0)
@@ -272,9 +272,9 @@ static const struct adreno_reglist a50x_hwcg_regs[] = {
 	{A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}
 };
 
-static const struct adreno_a5xx_core adreno_gpu_core_a505 = {
+static const struct adreno_a5xx_core adreno_gpu_core_a504 = {
 	.base = {
-		DEFINE_ADRENO_REV(ADRENO_REV_A505, 5, 0, 5, ANY_ID),
+		DEFINE_ADRENO_REV(ADRENO_REV_A504, 5, 0, 4, ANY_ID),
 		.features = ADRENO_PREEMPTION | ADRENO_64BIT,
 		.gpudev = &adreno_a5xx_gpudev,
 		.gmem_size = (SZ_128K + SZ_8K),
@@ -289,6 +289,25 @@ static const struct adreno_a5xx_core adreno_gpu_core_a505 = {
 	.vbif_count = ARRAY_SIZE(a530_vbif_regs),
 };
 
+static const struct adreno_a5xx_core adreno_gpu_core_a505 = {
+	.base = {
+		DEFINE_ADRENO_REV(ADRENO_REV_A505, 5, 0, 5, ANY_ID),
+		.features = ADRENO_PREEMPTION | ADRENO_64BIT |
+			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,
+		.gpudev = &adreno_a5xx_gpudev,
+		.gmem_size = (SZ_128K + SZ_8K),
+		.busy_mask = 0xfffffffe,
+		.bus_width = 16,
+	},
+	.pm4fw_name = "a530_pm4.fw",
+	.pfpfw_name = "a530_pfp.fw",
+	.zap_name = "a506_zap",
+	.hwcg = a50x_hwcg_regs,
+	.hwcg_count = ARRAY_SIZE(a50x_hwcg_regs),
+	.vbif = a530_vbif_regs,
+	.vbif_count = ARRAY_SIZE(a530_vbif_regs),
+};
+
 static const struct adreno_a5xx_core adreno_gpu_core_a506 = {
 	.base = {
 		DEFINE_ADRENO_REV(ADRENO_REV_A506, 5, 0, 6, ANY_ID),
@@ -919,7 +938,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a619 = {
 	},
 	.prim_fifo_threshold = 0x0018000,
 	.gmu_major = 1,
-	.gmu_minor = 10,
+	.gmu_minor = 11,
 	.sqefw_name = "a630_sqe.fw",
 	.gmufw_name = "a619_gmu.bin",
 	.zap_name = "a615_zap",
@@ -1496,6 +1515,7 @@ static const struct adreno_gpu_core *adreno_gpulist[] = {
 	&adreno_gpu_core_a540v2.base,
 	&adreno_gpu_core_a512.base,
 	&adreno_gpu_core_a508.base,
+	&adreno_gpu_core_a504.base,
 	&adreno_gpu_core_a630v1,	/* Deprecated */
 	&adreno_gpu_core_a630v2.base,
 	&adreno_gpu_core_a615.base,

drivers/gpu/msm/adreno.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2002,2007-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2002,2007-2021, The Linux Foundation. All rights reserved.
  */
 #include <linux/delay.h>
 #include <linux/input.h>
@@ -240,6 +240,56 @@ int adreno_efuse_read_u32(struct adreno_device *adreno_dev, unsigned int offset,
 	return 0;
 }
 
+void adreno_efuse_speed_bin_array(struct adreno_device *adreno_dev)
+{
+	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
+	int ret, count, i = 0;
+	unsigned int val, vector_size = 3;
+	unsigned int *bin_vector;
+
+	/*
+	 * Here count is no of 32 bit elements in the
+	 * speed-bin-vector array. If there are two fuses
+	 * i.e If no of fuses are 2 then no of elements will be
+	 * 2 * 3 = 6(elements of 32 bit each).
+	 */
+	count = of_property_count_u32_elems(device->pdev->dev.of_node,
+				"qcom,gpu-speed-bin-vectors");
+
+	if ((count <= 0) || (count % vector_size))
+		return;
+
+	bin_vector = kmalloc_array(count, sizeof(unsigned int), GFP_KERNEL);
+	if (bin_vector == NULL)
+		return;
+
+	if (of_property_read_u32_array(device->pdev->dev.of_node,
+			"qcom,gpu-speed-bin-vectors",
+			bin_vector, count)) {
+		dev_err(device->dev,
+				"Speed-bin-vectors is invalid\n");
+		kfree(bin_vector);
+		return;
+	}
+
+	/*
+	 * Final value of adreno_dev->speed_bin is the value formed by
+	 * OR'ing the values read from all the fuses.
+	 */
+	while (i < count) {
+		ret = adreno_efuse_read_u32(adreno_dev, bin_vector[i], &val);
+
+		if (ret < 0)
+			break;
+
+		adreno_dev->speed_bin |= (val & bin_vector[i+1])
+				>> bin_vector[i+2];
+		i += vector_size;
+	}
+
+	kfree(bin_vector);
+}
+
 static int _get_counter(struct adreno_device *adreno_dev,
 		int group, int countable, unsigned int *lo,
 		unsigned int *hi)

drivers/gpu/msm/adreno.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2008-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2008-2021, The Linux Foundation. All rights reserved.
  */
 #ifndef __ADRENO_H
 #define __ADRENO_H
@@ -202,6 +202,7 @@ enum adreno_gpurev {
 	ADRENO_REV_A418 = 418,
 	ADRENO_REV_A420 = 420,
 	ADRENO_REV_A430 = 430,
+	ADRENO_REV_A504 = 504,
 	ADRENO_REV_A505 = 505,
 	ADRENO_REV_A506 = 506,
 	ADRENO_REV_A508 = 508,
@@ -1107,6 +1108,7 @@ int adreno_efuse_map(struct adreno_device *adreno_dev);
 int adreno_efuse_read_u32(struct adreno_device *adreno_dev, unsigned int offset,
 		unsigned int *val);
 void adreno_efuse_unmap(struct adreno_device *adreno_dev);
+void adreno_efuse_speed_bin_array(struct adreno_device *adreno_dev);
 
 bool adreno_is_cx_dbgc_register(struct kgsl_device *device,
 		unsigned int offset);
@@ -1150,6 +1152,7 @@ static inline int adreno_is_a5xx(struct adreno_device *adreno_dev)
 			ADRENO_GPUREV(adreno_dev) < 600;
 }
 
+ADRENO_TARGET(a504, ADRENO_REV_A504)
 ADRENO_TARGET(a505, ADRENO_REV_A505)
 ADRENO_TARGET(a506, ADRENO_REV_A506)
 ADRENO_TARGET(a508, ADRENO_REV_A508)
@@ -1170,9 +1173,9 @@ static inline int adreno_is_a530v3(struct adreno_device *adreno_dev)
 		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 2);
 }
 
-static inline int adreno_is_a505_or_a506(struct adreno_device *adreno_dev)
+static inline int adreno_is_a504_to_a506(struct adreno_device *adreno_dev)
 {
-	return ADRENO_GPUREV(adreno_dev) >= 505 &&
+	return ADRENO_GPUREV(adreno_dev) >= 504 &&
 			ADRENO_GPUREV(adreno_dev) <= 506;
 }
 

drivers/gpu/msm/adreno_a5xx.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/clk/qcom.h>
@@ -89,13 +89,34 @@ static void a530_efuse_speed_bin(struct adreno_device *adreno_dev)
 	adreno_dev->speed_bin = (val & speed_bin[1]) >> speed_bin[2];
 }
 
+static void a5xx_efuse_speed_bin(struct adreno_device *adreno_dev)
+{
+	unsigned int val;
+	unsigned int speed_bin[3];
+	struct kgsl_device *device = &adreno_dev->dev;
+
+	if (of_get_property(device->pdev->dev.of_node,
+			"qcom,gpu-speed-bin-vectors", NULL)) {
+		adreno_efuse_speed_bin_array(adreno_dev);
+		return;
+	}
+
+	if (!of_property_read_u32_array(device->pdev->dev.of_node,
+			"qcom,gpu-speed-bin", speed_bin, 3)) {
+		adreno_efuse_read_u32(adreno_dev, speed_bin[0], &val);
+		adreno_dev->speed_bin = (val & speed_bin[1]) >> speed_bin[2];
+		return;
+	}
+}
+
 static const struct {
 	int (*check)(struct adreno_device *adreno_dev);
 	void (*func)(struct adreno_device *adreno_dev);
 } a5xx_efuse_funcs[] = {
 	{ adreno_is_a530, a530_efuse_leakage },
 	{ adreno_is_a530, a530_efuse_speed_bin },
-	{ adreno_is_a505, a530_efuse_speed_bin },
+	{ adreno_is_a504, a5xx_efuse_speed_bin },
+	{ adreno_is_a505, a5xx_efuse_speed_bin },
 	{ adreno_is_a512, a530_efuse_speed_bin },
 	{ adreno_is_a508, a530_efuse_speed_bin },
 };
@@ -119,7 +140,7 @@ static void a5xx_platform_setup(struct adreno_device *adreno_dev)
 {
 	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
 
-	if (adreno_is_a505_or_a506(adreno_dev) || adreno_is_a508(adreno_dev)) {
+	if (adreno_is_a504_to_a506(adreno_dev) || adreno_is_a508(adreno_dev)) {
 		gpudev->snapshot_data->sect_sizes->cp_meq = 32;
 		gpudev->snapshot_data->sect_sizes->cp_merciu = 1024;
 		gpudev->snapshot_data->sect_sizes->roq = 256;
@@ -1525,7 +1546,7 @@ static void a5xx_start(struct adreno_device *adreno_dev)
 	 * Below CP registers are 0x0 by default, program init
 	 * values based on a5xx flavor.
 	 */
-	if (adreno_is_a505_or_a506(adreno_dev) || adreno_is_a508(adreno_dev)) {
+	if (adreno_is_a504_to_a506(adreno_dev) || adreno_is_a508(adreno_dev)) {
 		kgsl_regwrite(device, A5XX_CP_MEQ_THRESHOLDS, 0x20);
 		kgsl_regwrite(device, A5XX_CP_MERCIU_SIZE, 0x400);
 		kgsl_regwrite(device, A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030);
@@ -1551,7 +1572,7 @@ static void a5xx_start(struct adreno_device *adreno_dev)
 	 * vtxFifo and primFifo thresholds default values
 	 * are different.
 	 */
-	if (adreno_is_a505_or_a506(adreno_dev) || adreno_is_a508(adreno_dev))
+	if (adreno_is_a504_to_a506(adreno_dev) || adreno_is_a508(adreno_dev))
 		kgsl_regwrite(device, A5XX_PC_DBG_ECO_CNTL,
 						(0x100 << 11 | 0x100 << 22));
 	else if (adreno_is_a510(adreno_dev) || adreno_is_a512(adreno_dev))
@@ -1832,6 +1853,7 @@ static int _me_init_ucode_workarounds(struct adreno_device *adreno_dev)
 	switch (ADRENO_GPUREV(adreno_dev)) {
 	case ADRENO_REV_A510:
 		return 0x00000001; /* Ucode workaround for token end syncs */
+	case ADRENO_REV_A504:
 	case ADRENO_REV_A505:
 	case ADRENO_REV_A506:
 	case ADRENO_REV_A530:

drivers/gpu/msm/adreno_a6xx.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/firmware.h>
@@ -89,9 +89,27 @@ static u32 a6xx_ifpc_pwrup_reglist[] = {
 };
 
 /* Applicable to a620 and a650 */
+static u32 a650_ifpc_pwrup_reglist[] = {
+	A6XX_CP_PROTECT_REG+32,
+	A6XX_CP_PROTECT_REG+33,
+	A6XX_CP_PROTECT_REG+34,
+	A6XX_CP_PROTECT_REG+35,
+	A6XX_CP_PROTECT_REG+36,
+	A6XX_CP_PROTECT_REG+37,
+	A6XX_CP_PROTECT_REG+38,
+	A6XX_CP_PROTECT_REG+39,
+	A6XX_CP_PROTECT_REG+40,
+	A6XX_CP_PROTECT_REG+41,
+	A6XX_CP_PROTECT_REG+42,
+	A6XX_CP_PROTECT_REG+43,
+	A6XX_CP_PROTECT_REG+44,
+	A6XX_CP_PROTECT_REG+45,
+	A6XX_CP_PROTECT_REG+46,
+	A6XX_CP_PROTECT_REG+47,
+};
+
 static u32 a650_pwrup_reglist[] = {
 	A6XX_RBBM_GBIF_CLIENT_QOS_CNTL,
-	A6XX_CP_PROTECT_REG + 47,         /* Programmed for infinite span */
 	A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0,
 	A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
 	A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
@@ -351,14 +369,21 @@ struct a6xx_reglist_list {
 
 static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev)
 {
-	struct a6xx_reglist_list reglist[3];
+	struct a6xx_reglist_list reglist[4];
 	void *ptr = adreno_dev->pwrup_reglist.hostptr;
 	struct cpu_gpu_lock *lock = ptr;
 	int items = 0, i, j;
 	u32 *dest = ptr + sizeof(*lock);
+	u16 list_offset = 0;
 
 	/* Static IFPC-only registers */
-	reglist[items++] = REGLIST(a6xx_ifpc_pwrup_reglist);
+	reglist[items] = REGLIST(a6xx_ifpc_pwrup_reglist);
+	list_offset += reglist[items++].count * 2;
+
+	if (adreno_is_a650_family(adreno_dev)) {
+		reglist[items] = REGLIST(a650_ifpc_pwrup_reglist);
+		list_offset += reglist[items++].count * 2;
+	}
 
 	/* Static IFPC + preemption registers */
 	reglist[items++] = REGLIST(a6xx_pwrup_reglist);
@@ -401,7 +426,7 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev)
 	 * all the lists and list_offset should be specified as the size in
 	 * dwords of the first entry in the list.
 	 */
-	lock->list_offset = reglist[0].count * 2;
+	lock->list_offset = list_offset;
 }
 
 /*

drivers/gpu/msm/adreno_debugfs.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2002,2008-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2002,2008-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/debugfs.h>
@@ -147,11 +147,22 @@ static void sync_event_print(struct seq_file *s,
 		break;
 	}
 	case KGSL_CMD_SYNCPOINT_TYPE_FENCE: {
+		struct event_fence_info *info = sync_event ?
+				sync_event->priv : NULL;
 		int i;
 
-		for (i = 0; i < sync_event->info.num_fences; i++)
+		for (i = 0; info && i < info->num_fences; i++)
 			seq_printf(s, "sync: %s",
-				sync_event->info.fences[i].name);
+				info->fences[i].name);
+		break;
+	}
+	case KGSL_CMD_SYNCPOINT_TYPE_TIMELINE: {
+		struct event_timeline_info *info = sync_event->priv;
+		int j;
+
+		for (j = 0; info && info[j].timeline; j++)
+			seq_printf(s, "timeline: %d seqno: %d",
+				info[j].timeline, info[j].seqno);
 		break;
 	}
 	default:

drivers/gpu/msm/adreno_dispatch.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/slab.h>
@@ -8,6 +8,7 @@
 #include "adreno.h"
 #include "adreno_trace.h"
 #include "kgsl_gmu_core.h"
+#include "kgsl_timeline.h"
 
 #define DRAWQUEUE_NEXT(_i, _s) (((_i) + 1) % (_s))
 
@@ -276,6 +277,7 @@ static void _retire_timestamp(struct kgsl_drawobj *drawobj)
 		KGSL_MEMSTORE_OFFSET(context->id, eoptimestamp),
 		drawobj->timestamp);
 
+	drawctxt->submitted_timestamp = drawobj->timestamp;
 
 	/* Retire pending GPU events for the object */
 	kgsl_process_event_group(device, &context->events);
@@ -342,12 +344,14 @@ static void _retire_sparseobj(struct kgsl_drawobj_sparse *sparseobj,
 	_retire_timestamp(DRAWOBJ(sparseobj));
 }
 
-static int _retire_markerobj(struct kgsl_drawobj_cmd *cmdobj,
+static int dispatch_retire_markerobj(struct kgsl_drawobj *drawobj,
 				struct adreno_context *drawctxt)
 {
+	struct kgsl_drawobj_cmd *cmdobj = CMDOBJ(drawobj);
+
 	if (_marker_expired(cmdobj)) {
 		_pop_drawobj(drawctxt);
-		_retire_timestamp(DRAWOBJ(cmdobj));
+		_retire_timestamp(drawobj);
 		return 0;
 	}
 
@@ -363,12 +367,14 @@ static int _retire_markerobj(struct kgsl_drawobj_cmd *cmdobj,
 	return test_bit(CMDOBJ_SKIP, &cmdobj->priv) ? 1 : -EAGAIN;
 }
 
-static int _retire_syncobj(struct kgsl_drawobj_sync *syncobj,
+static int dispatch_retire_syncobj(struct kgsl_drawobj *drawobj,
 				struct adreno_context *drawctxt)
 {
+	struct kgsl_drawobj_sync *syncobj = SYNCOBJ(drawobj);
+
 	if (!kgsl_drawobj_events_pending(syncobj)) {
 		_pop_drawobj(drawctxt);
-		kgsl_drawobj_destroy(DRAWOBJ(syncobj));
+		kgsl_drawobj_destroy(drawobj);
 		return 0;
 	}
 
@@ -384,6 +390,22 @@ static int _retire_syncobj(struct kgsl_drawobj_sync *syncobj,
 	return -EAGAIN;
 }
 
+static int drawqueue_retire_timelineobj(struct kgsl_drawobj *drawobj,
+		struct adreno_context *drawctxt)
+{
+	struct kgsl_drawobj_timeline *timelineobj = TIMELINEOBJ(drawobj);
+	int i;
+
+	for (i = 0; i < timelineobj->count; i++)
+		kgsl_timeline_signal(timelineobj->timelines[i].timeline,
+			timelineobj->timelines[i].seqno);
+
+	_pop_drawobj(drawctxt);
+	_retire_timestamp(drawobj);
+
+	return 0;
+}
+
 /*
  * Retires all expired marker and sync objs from the context
  * queue and returns one of the below
@@ -397,35 +419,40 @@ static struct kgsl_drawobj *_process_drawqueue_get_next_drawobj(
 {
 	struct kgsl_drawobj *drawobj;
 	unsigned int i = drawctxt->drawqueue_head;
-	int ret = 0;
 
 	if (drawctxt->drawqueue_head == drawctxt->drawqueue_tail)
 		return NULL;
 
 	for (i = drawctxt->drawqueue_head; i != drawctxt->drawqueue_tail;
 			i = DRAWQUEUE_NEXT(i, ADRENO_CONTEXT_DRAWQUEUE_SIZE)) {
+		int ret = 0;
 
 		drawobj = drawctxt->drawqueue[i];
-
+		if (!drawobj)
-		if (drawobj == NULL)
 			return NULL;
 
-		if (drawobj->type == CMDOBJ_TYPE)
+		switch (drawobj->type) {
+		case CMDOBJ_TYPE:
 			return drawobj;
-		else if (drawobj->type == MARKEROBJ_TYPE) {
+		case MARKEROBJ_TYPE:
-			ret = _retire_markerobj(CMDOBJ(drawobj), drawctxt);
+			ret = dispatch_retire_markerobj(drawobj, drawctxt);
 			/* Special case where marker needs to be sent to GPU */
 			if (ret == 1)
 				return drawobj;
-		} else if (drawobj->type == SYNCOBJ_TYPE)
+			break;
-			ret = _retire_syncobj(SYNCOBJ(drawobj), drawctxt);
+		case SYNCOBJ_TYPE:
-		else
+			ret = dispatch_retire_syncobj(drawobj, drawctxt);
-			return ERR_PTR(-EINVAL);
+			break;
+		case TIMELINEOBJ_TYPE:
+			ret = drawqueue_retire_timelineobj(drawobj, drawctxt);
+			break;
+		default:
+			ret = -EINVAL;
+			break;
+		}
 
-		if (ret == -EAGAIN)
+		if (ret)
-			return ERR_PTR(-EAGAIN);
+			return ERR_PTR(ret);
-
-		continue;
 	}
 
 	return NULL;
@@ -696,7 +723,7 @@ static struct kgsl_drawobj_sparse *_get_next_sparseobj(
 			return NULL;
 
 		if (drawobj->type == SYNCOBJ_TYPE)
-			ret = _retire_syncobj(SYNCOBJ(drawobj), drawctxt);
+			ret = dispatch_retire_syncobj(drawobj, drawctxt);
 		else if (drawobj->type == SPARSEOBJ_TYPE)
 			return SPARSEOBJ(drawobj);
 		else
@@ -1247,12 +1274,27 @@ static int _queue_sparseobj(struct adreno_device *adreno_dev,
 	return 0;
 }
 
+static int drawctxt_queue_auxobj(struct adreno_device *adreno_dev,
+		struct adreno_context *drawctxt, struct kgsl_drawobj *drawobj,
+		u32 *timestamp, u32 user_ts)
+{
+	int ret;
 
-static int _queue_markerobj(struct adreno_device *adreno_dev,
+	ret = get_timestamp(drawctxt, drawobj, timestamp, user_ts);
-	struct adreno_context *drawctxt, struct kgsl_drawobj_cmd *markerobj,
+	if (ret)
+		return ret;
+
+	drawctxt->queued_timestamp = *timestamp;
+	_queue_drawobj(drawctxt, drawobj);
+
+	return 0;
+}
+
+static int drawctxt_queue_markerobj(struct adreno_device *adreno_dev,
+	struct adreno_context *drawctxt, struct kgsl_drawobj *drawobj,
 	uint32_t *timestamp, unsigned int user_ts)
 {
-	struct kgsl_drawobj *drawobj = DRAWOBJ(markerobj);
+	struct kgsl_drawobj_cmd *markerobj = CMDOBJ(drawobj);
 	int ret;
 
 	ret = get_timestamp(drawctxt, drawobj, timestamp, user_ts);
@@ -1285,11 +1327,11 @@ static int _queue_markerobj(struct adreno_device *adreno_dev,
 	return 0;
 }
 
-static int _queue_cmdobj(struct adreno_device *adreno_dev,
+static int drawctxt_queue_cmdobj(struct adreno_device *adreno_dev,
-	struct adreno_context *drawctxt, struct kgsl_drawobj_cmd *cmdobj,
+	struct adreno_context *drawctxt, struct kgsl_drawobj *drawobj,
 	uint32_t *timestamp, unsigned int user_ts)
 {
-	struct kgsl_drawobj *drawobj = DRAWOBJ(cmdobj);
+	struct kgsl_drawobj_cmd *cmdobj = CMDOBJ(drawobj);
 	unsigned int j;
 	int ret;
 
@@ -1323,11 +1365,9 @@ static int _queue_cmdobj(struct adreno_device *adreno_dev,
 	return 0;
 }
 
-static void _queue_syncobj(struct adreno_context *drawctxt,
+static void drawctxt_queue_syncobj(struct adreno_context *drawctxt,
-	struct kgsl_drawobj_sync *syncobj, uint32_t *timestamp)
+	struct kgsl_drawobj *drawobj, uint32_t *timestamp)
 {
-	struct kgsl_drawobj *drawobj = DRAWOBJ(syncobj);
-
 	*timestamp = 0;
 	drawobj->timestamp = 0;
 
@@ -1401,29 +1441,34 @@ int adreno_dispatcher_queue_cmds(struct kgsl_device_private *dev_priv,
 
 		switch (drawobj[i]->type) {
 		case MARKEROBJ_TYPE:
-			ret = _queue_markerobj(adreno_dev, drawctxt,
+			ret = drawctxt_queue_markerobj(adreno_dev, drawctxt,
-					CMDOBJ(drawobj[i]),
+				drawobj[i], timestamp, user_ts);
-					timestamp, user_ts);
+			if (ret)
-			if (ret == 1) {
 				spin_unlock(&drawctxt->lock);
+
+			if (ret == 1)
 				goto done;
-			} else if (ret) {
+			else if (ret)
-				spin_unlock(&drawctxt->lock);
 				return ret;
-			}
 			break;
 		case CMDOBJ_TYPE:
-			ret = _queue_cmdobj(adreno_dev, drawctxt,
+			ret = drawctxt_queue_cmdobj(adreno_dev, drawctxt,
-						CMDOBJ(drawobj[i]),
+				drawobj[i], timestamp, user_ts);
-						timestamp, user_ts);
 			if (ret) {
 				spin_unlock(&drawctxt->lock);
 				return ret;
 			}
 			break;
 		case SYNCOBJ_TYPE:
-			_queue_syncobj(drawctxt, SYNCOBJ(drawobj[i]),
+			drawctxt_queue_syncobj(drawctxt, drawobj[i], timestamp);
-						timestamp);
+			break;
+		case TIMELINEOBJ_TYPE:
+			ret = drawctxt_queue_auxobj(adreno_dev,
+				drawctxt, drawobj[i], timestamp, user_ts);
+			if (ret) {
+				spin_unlock(&drawctxt->lock);
+				return ret;
+			}
 			break;
 		case SPARSEOBJ_TYPE:
 			ret = _queue_sparseobj(adreno_dev, drawctxt,

drivers/gpu/msm/adreno_ioctl.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2002,2007-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2002,2007-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/slab.h>
@@ -183,11 +183,8 @@ long adreno_ioctl_helper(struct kgsl_device_private *dev_priv,
 			break;
 	}
 
-	if (i == len) {
+	if (i == len)
-		dev_err(dev_priv->device->dev,
-			     "invalid ioctl code 0x%08X\n", cmd);
 		return -ENOIOCTLCMD;
-	}
 
 	if (_IOC_SIZE(cmds[i].cmd > sizeof(data))) {
 		dev_err_ratelimited(dev_priv->device->dev,

drivers/gpu/msm/adreno_snapshot.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/msm-bus.h>
@@ -195,7 +195,17 @@ static inline void parse_ib(struct kgsl_device *device,
 	 * then push it into the static blob otherwise put it in the dynamic
 	 * list
 	 */
-	if (gpuaddr == snapshot->ib1base) {
+	if (kgsl_addr_range_overlap(gpuaddr, dwords,
+		snapshot->ib1base, snapshot->ib1size)) {
+		/*
+		 * During restore after preemption, ib1base in the register
+		 * can be updated by CP. In such scenarios, to dump complete
+		 * IB1 in snapshot, we should consider ib1base from ringbuffer.
+		 */
+		if (gpuaddr != snapshot->ib1base) {
+			snapshot->ib1base = gpuaddr;
+			snapshot->ib1size = dwords;
+		}
 		kgsl_snapshot_push_object(device, process, gpuaddr, dwords);
 		return;
 	}
@@ -309,16 +319,29 @@ static void snapshot_rb_ibs(struct kgsl_device *device,
 		}
 
 		if (adreno_cmd_is_ib(adreno_dev, rbptr[index])) {
-			if (ADRENO_LEGACY_PM4(adreno_dev)) {
+			uint64_t ibaddr;
-				if (rbptr[index + 1] == snapshot->ib1base)
+			uint64_t ibsize;
-					break;
-			} else {
-				uint64_t ibaddr;
 
+			if (ADRENO_LEGACY_PM4(adreno_dev)) {
+				ibaddr = rbptr[index + 1];
+				ibsize = rbptr[index + 2];
+			} else {
 				ibaddr = rbptr[index + 2];
 				ibaddr = ibaddr << 32 | rbptr[index + 1];
-				if (ibaddr == snapshot->ib1base)
+				ibsize = rbptr[index + 3];
-					break;
+			}
+
+			if (kgsl_addr_range_overlap(ibaddr, ibsize,
+				snapshot->ib1base, snapshot->ib1size)) {
+				/*
+				 * During restore after preemption, ib1base in
+				 * the register can be updated by CP. In such
+				 * scenario, to dump complete IB1 in snapshot,
+				 * we should consider ib1base from ringbuffer.
+				 */
+				snapshot->ib1base = ibaddr;
+				snapshot->ib1size = ibsize;
+				break;
 			}
 		}
 	} while (index != rb->wptr);
@@ -916,8 +939,7 @@ void adreno_snapshot(struct kgsl_device *device, struct kgsl_snapshot *snapshot,
 	 * figure how often this really happens.
 	 */
 
-	if (-ENOENT == find_object(snapshot->ib1base, snapshot->process) &&
+	if (-ENOENT == find_object(snapshot->ib1base, snapshot->process)) {
-			snapshot->ib1size) {
 		struct kgsl_mem_entry *entry;
 		u64 ibsize;
 

drivers/gpu/msm/kgsl.c

@@ -293,8 +293,12 @@ static void remove_dmabuf_list(struct kgsl_dma_buf_meta *meta)
 }
 
 #ifdef CONFIG_DMA_SHARED_BUFFER
-static void kgsl_destroy_ion(struct kgsl_dma_buf_meta *meta)
+static void kgsl_destroy_ion(struct kgsl_memdesc *memdesc)
 {
+	struct kgsl_mem_entry *entry = container_of(memdesc,
+				struct kgsl_mem_entry, memdesc);
+	struct kgsl_dma_buf_meta *meta = entry->priv_data;
+
 	if (meta != NULL) {
 		remove_dmabuf_list(meta);
 		dma_buf_unmap_attachment(meta->attach, meta->table,
@@ -303,14 +307,45 @@ static void kgsl_destroy_ion(struct kgsl_dma_buf_meta *meta)
 		dma_buf_put(meta->dmabuf);
 		kfree(meta);
 	}
-}
-#else
-static void kgsl_destroy_ion(struct kgsl_dma_buf_meta *meta)
-{
 
+	/*
+	 * Ion takes care of freeing the sg_table for us so
+	 * clear the sg table to ensure kgsl_sharedmem_free
+	 * doesn't try to free it again
+	 */
+	memdesc->sgt = NULL;
 }
+
+static struct kgsl_memdesc_ops kgsl_dmabuf_ops = {
+	.free = kgsl_destroy_ion,
+};
 #endif
 
+static void kgsl_destroy_anon(struct kgsl_memdesc *memdesc)
+{
+	int i = 0, j;
+	struct scatterlist *sg;
+	struct page *page;
+
+	for_each_sg(memdesc->sgt->sgl, sg, memdesc->sgt->nents, i) {
+		page = sg_page(sg);
+		for (j = 0; j < (sg->length >> PAGE_SHIFT); j++) {
+			/*
+			 * Mark the page in the scatterlist as dirty if they
+			 * were writable by the GPU.
+			 */
+			if (!(memdesc->flags & KGSL_MEMFLAGS_GPUREADONLY))
+				set_page_dirty_lock(nth_page(page, j));
+
+			/*
+			 * Put the page reference taken using get_user_pages
+			 * during memdesc_sg_virt.
+			 */
+			put_page(nth_page(page, j));
+		}
+	}
+}
+
 static void mem_entry_destroy(struct kgsl_mem_entry *entry)
 {
 	unsigned int memtype;
@@ -329,41 +364,8 @@ static void mem_entry_destroy(struct kgsl_mem_entry *entry)
 		atomic_long_sub(entry->memdesc.size,
 			&kgsl_driver.stats.mapped);
 
-	/*
-	 * Ion takes care of freeing the sg_table for us so
-	 * clear the sg table before freeing the sharedmem
-	 * so kgsl_sharedmem_free doesn't try to free it again
-	 */
-	if (memtype == KGSL_MEM_ENTRY_ION)
-		entry->memdesc.sgt = NULL;
-
-	if ((memtype == KGSL_MEM_ENTRY_USER)
-		&& !(entry->memdesc.flags & KGSL_MEMFLAGS_GPUREADONLY)) {
-		int i = 0, j;
-		struct scatterlist *sg;
-		struct page *page;
-		/*
-		 * Mark all of pages in the scatterlist as dirty since they
-		 * were writable by the GPU.
-		 */
-		for_each_sg(entry->memdesc.sgt->sgl, sg,
-			    entry->memdesc.sgt->nents, i) {
-			page = sg_page(sg);
-			for (j = 0; j < (sg->length >> PAGE_SHIFT); j++)
-				set_page_dirty_lock(nth_page(page, j));
-		}
-	}
-
 	kgsl_sharedmem_free(&entry->memdesc);
 
-	switch (memtype) {
-	case KGSL_MEM_ENTRY_ION:
-		kgsl_destroy_ion(entry->priv_data);
-		break;
-	default:
-		break;
-	}
-
 	kfree(entry);
 }
 
@@ -696,8 +698,7 @@ void kgsl_context_detach(struct kgsl_context *context)
 	/* Remove the event group from the list */
 	kgsl_del_event_group(&context->events);
 
-	kgsl_sync_timeline_put(context->ktimeline);
+	kgsl_sync_timeline_detach(context->ktimeline);
-
 	kgsl_context_put(context);
 }
 
@@ -716,6 +717,8 @@ kgsl_context_destroy(struct kref *kref)
 	 */
 	BUG_ON(!kgsl_context_detached(context));
 
+	kgsl_sync_timeline_put(context->ktimeline);
+
 	write_lock(&device->context_lock);
 	if (context->id != KGSL_CONTEXT_INVALID) {
 
@@ -739,7 +742,6 @@ kgsl_context_destroy(struct kref *kref)
 		context->id = KGSL_CONTEXT_INVALID;
 	}
 	write_unlock(&device->context_lock);
-	kgsl_sync_timeline_destroy(context);
 	kgsl_process_private_put(context->proc_priv);
 
 	device->ftbl->drawctxt_destroy(context);
@@ -904,11 +906,27 @@ static void kgsl_destroy_process_private(struct kref *kref)
 	struct kgsl_process_private *private = container_of(kref,
 			struct kgsl_process_private, refcount);
 
+	mutex_lock(&kgsl_driver.process_mutex);
+
+	debugfs_remove_recursive(private->debug_root);
+	kgsl_process_uninit_sysfs(private);
+
+	/* When using global pagetables, do not detach global pagetable */
+	if (private->pagetable->name != KGSL_MMU_GLOBAL_PT)
+		kgsl_mmu_detach_pagetable(private->pagetable);
+
+	/* Remove the process struct from the master list */
+	spin_lock(&kgsl_driver.proclist_lock);
+	list_del(&private->list);
+	spin_unlock(&kgsl_driver.proclist_lock);
+
+	mutex_unlock(&kgsl_driver.process_mutex);
+
 	put_pid(private->pid);
 	idr_destroy(&private->mem_idr);
 	idr_destroy(&private->syncsource_idr);
 
-	/* When using global pagetables, do not detach global pagetable */
+	/* When using global pagetables, do not put global pagetable */
 	if (private->pagetable->name != KGSL_MMU_GLOBAL_PT)
 		kgsl_mmu_putpagetable(private->pagetable);
 
@@ -951,13 +969,6 @@ static struct kgsl_process_private *kgsl_process_private_new(
 	struct kgsl_process_private *private;
 	struct pid *cur_pid = get_task_pid(current->group_leader, PIDTYPE_PID);
 
-	/*
-	 * Flush mem_workqueue to make sure that any lingering
-	 * structs (process pagetable etc) are released before
-	 * starting over again.
-	 */
-	flush_workqueue(kgsl_driver.mem_workqueue);
-
 	/* Search in the process list */
 	list_for_each_entry(private, &kgsl_driver.process_list, list) {
 		if (private->pid == cur_pid) {
@@ -1006,9 +1017,17 @@ static struct kgsl_process_private *kgsl_process_private_new(
 		put_pid(private->pid);
 
 		kfree(private);
-		private = ERR_PTR(err);
+		return ERR_PTR(err);
 	}
 
+	/* create the debug directories and add it to the process list */
+	kgsl_process_init_sysfs(device, private);
+	kgsl_process_init_debugfs(private);
+
+	spin_lock(&kgsl_driver.proclist_lock);
+	list_add(&private->list, &kgsl_driver.process_list);
+	spin_unlock(&kgsl_driver.proclist_lock);
+
 	return private;
 }
 
@@ -1057,30 +1076,13 @@ static void kgsl_process_private_close(struct kgsl_device_private *dev_priv,
 	 * directories and garbage collect any outstanding resources
 	 */
 
-	kgsl_process_uninit_sysfs(private);
+	process_release_memory(private);
 
 	/* Release all syncsource objects from process private */
 	kgsl_syncsource_process_release_syncsources(private);
 
-	/* When using global pagetables, do not detach global pagetable */
-	if (private->pagetable->name != KGSL_MMU_GLOBAL_PT)
-		kgsl_mmu_detach_pagetable(private->pagetable);
-
-	/* Remove the process struct from the master list */
-	spin_lock(&kgsl_driver.proclist_lock);
-	list_del(&private->list);
-	spin_unlock(&kgsl_driver.proclist_lock);
-
-	/*
-	 * Unlock the mutex before releasing the memory and the debugfs
-	 * nodes - this prevents deadlocks with the IOMMU and debugfs
-	 * locks.
-	 */
 	mutex_unlock(&kgsl_driver.process_mutex);
 
-	process_release_memory(private);
-	debugfs_remove_recursive(private->debug_root);
-
 	kgsl_process_private_put(private);
 }
 
@@ -1090,25 +1092,20 @@ static struct kgsl_process_private *kgsl_process_private_open(
 {
 	struct kgsl_process_private *private;
 
+	/*
+	 * Flush mem_workqueue to make sure that any lingering
+	 * structs (process pagetable etc) are released before
+	 * starting over again.
+	 */
+	flush_workqueue(kgsl_driver.mem_workqueue);
+
 	mutex_lock(&kgsl_driver.process_mutex);
 	private = kgsl_process_private_new(device);
 
 	if (IS_ERR(private))
 		goto done;
 
-	/*
+	private->fd_count++;
-	 * If this is a new process create the debug directories and add it to
-	 * the process list
-	 */
-
-	if (private->fd_count++ == 0) {
-		kgsl_process_init_sysfs(device, private);
-		kgsl_process_init_debugfs(private);
-
-		spin_lock(&kgsl_driver.proclist_lock);
-		list_add(&private->list, &kgsl_driver.process_list);
-		spin_unlock(&kgsl_driver.proclist_lock);
-	}
 
 done:
 	mutex_unlock(&kgsl_driver.process_mutex);
@@ -2110,6 +2107,129 @@ long kgsl_ioctl_gpu_command(struct kgsl_device_private *dev_priv,
 	return result;
 }
 
+long kgsl_ioctl_gpu_aux_command(struct kgsl_device_private *dev_priv,
+		unsigned int cmd, void *data)
+{
+	struct kgsl_gpu_aux_command *param = data;
+	struct kgsl_device *device = dev_priv->device;
+	struct kgsl_context *context;
+	struct kgsl_drawobj **drawobjs;
+	struct kgsl_drawobj_sync *tsobj;
+	void __user *cmdlist;
+	u32 queued, count;
+	int i, index = 0;
+	long ret;
+	struct kgsl_gpu_aux_command_generic generic;
+
+	/* We support only one aux command */
+	if (param->numcmds != 1)
+		return -EINVAL;
+
+	if (!(param->flags & KGSL_GPU_AUX_COMMAND_TIMELINE))
+		return -EINVAL;
+
+	context = kgsl_context_get_owner(dev_priv, param->context_id);
+	if (!context)
+		return -EINVAL;
+
+	/*
+	 * param->numcmds is always one and we have one additional drawobj
+	 * for the timestamp sync if KGSL_GPU_AUX_COMMAND_SYNC flag is passed.
+	 * On top of that we make an implicit sync object for the last queued
+	 * timestamp on this context.
+	 */
+	count = (param->flags & KGSL_GPU_AUX_COMMAND_SYNC) ? 3 : 2;
+
+	drawobjs = kvcalloc(count, sizeof(*drawobjs), GFP_KERNEL);
+
+	if (!drawobjs) {
+		kgsl_context_put(context);
+		return -ENOMEM;
+	}
+
+	trace_kgsl_aux_command(context->id, param->numcmds, param->flags,
+		param->timestamp);
+
+	if (param->flags & KGSL_GPU_AUX_COMMAND_SYNC) {
+		struct kgsl_drawobj_sync *syncobj =
+			kgsl_drawobj_sync_create(device, context);
+
+		if (IS_ERR(syncobj)) {
+			ret = PTR_ERR(syncobj);
+			goto err;
+		}
+
+		drawobjs[index++] = DRAWOBJ(syncobj);
+
+		ret = kgsl_drawobj_sync_add_synclist(device, syncobj,
+				u64_to_user_ptr(param->synclist),
+				param->syncsize, param->numsyncs);
+		if (ret)
+			goto err;
+	}
+
+	kgsl_readtimestamp(device, context, KGSL_TIMESTAMP_QUEUED, &queued);
+
+	/*
+	 * Make an implicit sync object for the last queued timestamp on this
+	 * context
+	 */
+	tsobj = kgsl_drawobj_create_timestamp_syncobj(device,
+		context, queued);
+
+	if (IS_ERR(tsobj)) {
+		ret = PTR_ERR(tsobj);
+		goto err;
+	}
+
+	drawobjs[index++] = DRAWOBJ(tsobj);
+
+	cmdlist = u64_to_user_ptr(param->cmdlist);
+
+	/* Create a draw object for KGSL_GPU_AUX_COMMAND_TIMELINE */
+	if (kgsl_copy_struct_from_user(&generic, sizeof(generic),
+		cmdlist, param->cmdsize)) {
+		ret = -EFAULT;
+		goto err;
+	}
+
+	if (generic.type == KGSL_GPU_AUX_COMMAND_TIMELINE) {
+		struct kgsl_drawobj_timeline *timelineobj;
+
+		timelineobj = kgsl_drawobj_timeline_create(device,
+			context);
+
+		if (IS_ERR(timelineobj)) {
+			ret = PTR_ERR(timelineobj);
+			goto err;
+		}
+
+		drawobjs[index++] = DRAWOBJ(timelineobj);
+
+		ret = kgsl_drawobj_add_timeline(dev_priv, timelineobj,
+			u64_to_user_ptr(generic.priv), generic.size);
+		if (ret)
+			goto err;
+	} else {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	ret = device->ftbl->queue_cmds(dev_priv, context,
+		drawobjs, index, &param->timestamp);
+
+err:
+	kgsl_context_put(context);
+
+	if (ret && ret != -EPROTO) {
+		for (i = 0; i < count; i++)
+			kgsl_drawobj_destroy(drawobjs[i]);
+	}
+
+	kvfree(drawobjs);
+	return ret;
+}
+
 long kgsl_ioctl_cmdstream_readtimestamp_ctxtid(struct kgsl_device_private
 						*dev_priv, unsigned int cmd,
 						void *data)
@@ -2501,6 +2621,10 @@ static int memdesc_sg_virt(struct kgsl_memdesc *memdesc, unsigned long useraddr)
 	return ret;
 }
 
+static struct kgsl_memdesc_ops kgsl_usermem_ops = {
+	.free = kgsl_destroy_anon,
+};
+
 static int kgsl_setup_anon_useraddr(struct kgsl_pagetable *pagetable,
 	struct kgsl_mem_entry *entry, unsigned long hostptr,
 	size_t offset, size_t size)
@@ -2515,12 +2639,19 @@ static int kgsl_setup_anon_useraddr(struct kgsl_pagetable *pagetable,
 	entry->memdesc.pagetable = pagetable;
 	entry->memdesc.size = (uint64_t) size;
 	entry->memdesc.flags |= (uint64_t)KGSL_MEMFLAGS_USERMEM_ADDR;
+	entry->memdesc.ops = &kgsl_usermem_ops;
 
 	if (kgsl_memdesc_use_cpu_map(&entry->memdesc)) {
 		/* Register the address in the database */
 		ret = kgsl_mmu_set_svm_region(pagetable,
 			(uint64_t) hostptr, (uint64_t) size);
 
+		/* if OOM, retry once after flushing mem_workqueue */
+		if (ret == -ENOMEM) {
+			flush_workqueue(kgsl_driver.mem_workqueue);
+			ret = kgsl_mmu_set_svm_region(pagetable,
+				(uint64_t) hostptr, (uint64_t) size);
+		}
 		if (ret)
 			return ret;
 
@@ -2834,11 +2965,6 @@ long kgsl_ioctl_gpuobj_import(struct kgsl_device_private *dev_priv,
 	return 0;
 
 unmap:
-	if (kgsl_memdesc_usermem_type(&entry->memdesc) == KGSL_MEM_ENTRY_ION) {
-		kgsl_destroy_ion(entry->priv_data);
-		entry->memdesc.sgt = NULL;
-	}
-
 	kgsl_sharedmem_free(&entry->memdesc);
 
 out:
@@ -2943,6 +3069,7 @@ static int kgsl_setup_dma_buf(struct kgsl_device *device,
 	entry->priv_data = meta;
 	entry->memdesc.pagetable = pagetable;
 	entry->memdesc.size = 0;
+	entry->memdesc.ops = &kgsl_dmabuf_ops;
 	/* USE_CPU_MAP is not impemented for ION. */
 	entry->memdesc.flags &= ~((uint64_t) KGSL_MEMFLAGS_USE_CPU_MAP);
 	entry->memdesc.flags |= (uint64_t)KGSL_MEMFLAGS_USERMEM_ION;
@@ -3148,14 +3275,6 @@ long kgsl_ioctl_map_user_mem(struct kgsl_device_private *dev_priv,
 	return result;
 
 error_attach:
-	switch (kgsl_memdesc_usermem_type(&entry->memdesc)) {
-	case KGSL_MEM_ENTRY_ION:
-		kgsl_destroy_ion(entry->priv_data);
-		entry->memdesc.sgt = NULL;
-		break;
-	default:
-		break;
-	}
 	kgsl_sharedmem_free(&entry->memdesc);
 error:
 	/* Clear gpuaddr here so userspace doesn't get any wrong ideas */
@@ -4894,6 +5013,11 @@ kgsl_get_unmapped_area(struct file *file, unsigned long addr,
 						pgoff, len, (int) val);
 	} else {
 		val = _get_svm_area(private, entry, addr, len, flags);
+		/* if OOM, retry once after flushing mem_workqueue */
+		if (val == -ENOMEM) {
+			flush_workqueue(kgsl_driver.mem_workqueue);
+			val = _get_svm_area(private, entry, addr, len, flags);
+		}
 		if (IS_ERR_VALUE(val))
 			dev_err_ratelimited(device->dev,
 					       "_get_svm_area: pid %d mmap_base %lx addr %lx pgoff %lx len %ld failed error %d\n",
@@ -5221,6 +5345,9 @@ int kgsl_device_platform_probe(struct kgsl_device *device)
 	if (status)
 		goto error_close_mmu;
 
+	idr_init(&device->timelines);
+	spin_lock_init(&device->timelines_lock);
+
 	/*
 	 * The default request type PM_QOS_REQ_ALL_CORES is
 	 * applicable to all CPU cores that are online and
@@ -5295,6 +5422,7 @@ void kgsl_device_platform_remove(struct kgsl_device *device)
 		pm_qos_remove_request(&device->pwrctrl.l2pc_cpus_qos);
 
 	idr_destroy(&device->context_idr);
+	idr_destroy(&device->timelines);
 
 	kgsl_mmu_close(device);
 

drivers/gpu/msm/kgsl.h

@@ -425,6 +425,20 @@ long kgsl_ioctl_gpu_command(struct kgsl_device_private *dev_priv,
 				unsigned int cmd, void *data);
 long kgsl_ioctl_gpuobj_set_info(struct kgsl_device_private *dev_priv,
 				unsigned int cmd, void *data);
+long kgsl_ioctl_gpu_aux_command(struct kgsl_device_private *dev_priv,
+		unsigned int cmd, void *data);
+long kgsl_ioctl_timeline_create(struct kgsl_device_private *dev_priv,
+		unsigned int cmd, void *data);
+long kgsl_ioctl_timeline_wait(struct kgsl_device_private *dev_priv,
+		unsigned int cmd, void *data);
+long kgsl_ioctl_timeline_query(struct kgsl_device_private *dev_priv,
+		unsigned int cmd, void *data);
+long kgsl_ioctl_timeline_fence_get(struct kgsl_device_private *dev_priv,
+		unsigned int cmd, void *data);
+long kgsl_ioctl_timeline_signal(struct kgsl_device_private *dev_priv,
+		unsigned int cmd, void *data);
+long kgsl_ioctl_timeline_destroy(struct kgsl_device_private *dev_priv,
+		unsigned int cmd, void *data);
 
 long kgsl_ioctl_sparse_phys_alloc(struct kgsl_device_private *dev_priv,
 					unsigned int cmd, void *data);

drivers/gpu/msm/kgsl_compat.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2019, 2021, The Linux Foundation. All rights reserved.
  */
 
 #include "kgsl_device.h"
@@ -352,6 +352,20 @@ static const struct kgsl_ioctl kgsl_compat_ioctl_funcs[] = {
 			kgsl_ioctl_sparse_bind),
 	KGSL_IOCTL_FUNC(IOCTL_KGSL_GPU_SPARSE_COMMAND,
 			kgsl_ioctl_gpu_sparse_command),
+	KGSL_IOCTL_FUNC(IOCTL_KGSL_GPU_AUX_COMMAND,
+			kgsl_ioctl_gpu_aux_command),
+	KGSL_IOCTL_FUNC(IOCTL_KGSL_TIMELINE_CREATE,
+			kgsl_ioctl_timeline_create),
+	KGSL_IOCTL_FUNC(IOCTL_KGSL_TIMELINE_WAIT,
+			kgsl_ioctl_timeline_wait),
+	KGSL_IOCTL_FUNC(IOCTL_KGSL_TIMELINE_FENCE_GET,
+			kgsl_ioctl_timeline_fence_get),
+	KGSL_IOCTL_FUNC(IOCTL_KGSL_TIMELINE_QUERY,
+			kgsl_ioctl_timeline_query),
+	KGSL_IOCTL_FUNC(IOCTL_KGSL_TIMELINE_SIGNAL,
+			kgsl_ioctl_timeline_signal),
+	KGSL_IOCTL_FUNC(IOCTL_KGSL_TIMELINE_DESTROY,
+			kgsl_ioctl_timeline_destroy),
 };
 
 long kgsl_compat_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
@@ -370,8 +384,6 @@ long kgsl_compat_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
 	if (ret == -ENOIOCTLCMD) {
 		if (device->ftbl->compat_ioctl != NULL)
 			return device->ftbl->compat_ioctl(dev_priv, cmd, arg);
-
-		dev_err(device->dev, "invalid ioctl code 0x%08X\n", cmd);
 	}
 
 	return ret;

drivers/gpu/msm/kgsl_device.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2002,2007-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2002,2007-2021, The Linux Foundation. All rights reserved.
  */
 #ifndef __KGSL_DEVICE_H
 #define __KGSL_DEVICE_H
@@ -16,6 +16,73 @@
 	[_IOC_NR((_cmd))] = \
 		{ .cmd = (_cmd), .func = (_func) }
 
+/**
+ * kgsl_copy_struct_from_user: copy a struct from userspace
+ * @dst:   Destination address, in kernel space. This buffer must be @ksize
+ *         bytes long.
+ * @ksize: Size of @dst struct.
+ * @src:   Source address, in userspace.
+ * @usize: (Alleged) size of @src struct.
+ *
+ * Copies a struct from userspace to kernel space, in a way that guarantees
+ * backwards-compatibility for struct syscall arguments (as long as future
+ * struct extensions are made such that all new fields are *appended* to the
+ * old struct, and zeroed-out new fields have the same meaning as the old
+ * struct).
+ *
+ * @ksize is just sizeof(*dst), and @usize should've been passed by userspace.
+ * The recommended usage is something like the following:
+ *
+ *   SYSCALL_DEFINE2(foobar, const struct foo __user *, uarg, size_t, usize)
+ *   {
+ *      int err;
+ *      struct foo karg = {};
+ *
+ *      if (usize > PAGE_SIZE)
+ *        return -E2BIG;
+ *      if (usize < FOO_SIZE_VER0)
+ *        return -EINVAL;
+ *
+ *      err = kgsl_copy_struct_from_user(&karg, sizeof(karg), uarg, usize);
+ *      if (err)
+ *        return err;
+ *
+ *      // ...
+ *   }
+ *
+ * There are three cases to consider:
+ *  * If @usize == @ksize, then it's copied verbatim.
+ *  * If @usize < @ksize, then the userspace has passed an old struct to a
+ *    newer kernel. The rest of the trailing bytes in @dst (@ksize - @usize)
+ *    are to be zero-filled.
+ *  * If @usize > @ksize, then the userspace has passed a new struct to an
+ *    older kernel. The trailing bytes unknown to the kernel (@usize - @ksize)
+ *    are checked to ensure they are zeroed, otherwise -E2BIG is returned.
+ *
+ * Returns (in all cases, some data may have been copied):
+ *  * -E2BIG:  (@usize > @ksize) and there are non-zero trailing bytes in @src.
+ *  * -EFAULT: access to userspace failed.
+ */
+static __always_inline __must_check int
+kgsl_copy_struct_from_user(void *dst, size_t ksize, const void __user *src,
+		      size_t usize)
+{
+	size_t size = min(ksize, usize);
+	size_t rest = max(ksize, usize) - size;
+
+	/* Deal with trailing bytes. */
+	if (usize < ksize) {
+		memset(dst + size, 0, rest);
+	} else if (usize > ksize) {
+		if (memchr_inv(src + size, 0, rest))
+			return -E2BIG;
+	}
+	/* Copy the interoperable parts of the struct. */
+	if (copy_from_user(dst, src, size))
+		return -EFAULT;
+	return 0;
+}
+
 /*
  * KGSL device state is initialized to INIT when platform_probe		*
  * successfully initialized the device.  Once a device has been opened	*
@@ -322,6 +389,10 @@ struct kgsl_device {
 	unsigned int num_l3_pwrlevels;
 	/* store current L3 vote to determine if we should change our vote */
 	unsigned int cur_l3_pwrlevel;
+	/** @timelines: Iterator for assigning IDs to timelines */
+	struct idr timelines;
+	/** @timelines_lock: Spinlock to protect the timelines idr */
+	spinlock_t timelines_lock;
 };
 
 #define KGSL_MMU_DEVICE(_mmu) \

drivers/gpu/msm/kgsl_drawobj.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  */
 
 /*
@@ -19,12 +19,14 @@
  */
 
 #include <linux/slab.h>
+#include <linux/dma-fence-array.h>
 
 #include "adreno_drawctxt.h"
 #include "kgsl_compat.h"
 #include "kgsl_device.h"
 #include "kgsl_drawobj.h"
 #include "kgsl_sync.h"
+#include "kgsl_timeline.h"
 #include "kgsl_trace.h"
 
 /*
@@ -34,41 +36,53 @@
 static struct kmem_cache *memobjs_cache;
 static struct kmem_cache *sparseobjs_cache;
 
-static void free_fence_names(struct kgsl_drawobj_sync *syncobj)
+static void syncobj_destroy_object(struct kgsl_drawobj *drawobj)
 {
-	unsigned int i;
+	struct kgsl_drawobj_sync *syncobj = SYNCOBJ(drawobj);
+	int i;
 
 	for (i = 0; i < syncobj->numsyncs; i++) {
 		struct kgsl_drawobj_sync_event *event = &syncobj->synclist[i];
 
-		if (event->type == KGSL_CMD_SYNCPOINT_TYPE_FENCE)
+		if (event->type == KGSL_CMD_SYNCPOINT_TYPE_FENCE) {
-			kfree(event->info.fences);
+			struct event_fence_info *priv = event ?
+					event->priv : NULL;
+
+			if (priv) {
+				kfree(priv->fences);
+				kfree(priv);
+			}
+		} else if (event->type == KGSL_CMD_SYNCPOINT_TYPE_TIMELINE) {
+			kfree(event->priv);
+		}
 	}
+
+	kfree(syncobj->synclist);
+	kfree(syncobj);
+}
+
+static void cmdobj_destroy_object(struct kgsl_drawobj *drawobj)
+{
+	kfree(CMDOBJ(drawobj));
+}
+
+static void timelineobj_destroy_object(struct kgsl_drawobj *drawobj)
+{
+	kfree(TIMELINEOBJ(drawobj));
+}
+
+static void sparseobj_destroy_object(struct kgsl_drawobj *drawobj)
+{
+	kfree(SPARSEOBJ(drawobj));
 }
 
 void kgsl_drawobj_destroy_object(struct kref *kref)
 {
 	struct kgsl_drawobj *drawobj = container_of(kref,
 		struct kgsl_drawobj, refcount);
-	struct kgsl_drawobj_sync *syncobj;
 
 	kgsl_context_put(drawobj->context);
-
+	drawobj->destroy_object(drawobj);
-	switch (drawobj->type) {
-	case SYNCOBJ_TYPE:
-		syncobj = SYNCOBJ(drawobj);
-		free_fence_names(syncobj);
-		kfree(syncobj->synclist);
-		kfree(syncobj);
-		break;
-	case CMDOBJ_TYPE:
-	case MARKEROBJ_TYPE:
-		kfree(CMDOBJ(drawobj));
-		break;
-	case SPARSEOBJ_TYPE:
-		kfree(SPARSEOBJ(drawobj));
-		break;
-	}
 }
 
 void kgsl_dump_syncpoints(struct kgsl_device *device,
@@ -99,13 +113,23 @@ void kgsl_dump_syncpoints(struct kgsl_device *device,
 		}
 		case KGSL_CMD_SYNCPOINT_TYPE_FENCE: {
 			int j;
-			struct event_fence_info *info = &event->info;
+			struct event_fence_info *info = event ?
+					event->priv : NULL;
 
-			for (j = 0; j < info->num_fences; j++)
+			for (j = 0; info && j < info->num_fences; j++)
 				dev_err(device->dev, "[%d]  fence: %s\n",
 					i, info->fences[j].name);
 			break;
 		}
+		case KGSL_CMD_SYNCPOINT_TYPE_TIMELINE: {
+			int j;
+			struct event_timeline_info *info = event->priv;
+
+			for (j = 0; info && info[j].timeline; j++)
+				dev_err(device->dev, "[%d]  timeline: %d seqno %lld\n",
+					i, info[j].timeline, info[j].seqno);
+			break;
+		}
 		}
 	}
 }
@@ -156,13 +180,27 @@ static void syncobj_timer(struct timer_list *t)
 			break;
 		case KGSL_CMD_SYNCPOINT_TYPE_FENCE: {
 			int j;
-			struct event_fence_info *info = &event->info;
+			struct event_fence_info *info = event ?
+					event->priv : NULL;
 
-			for (j = 0; j < info->num_fences; j++)
+			for (j = 0; info && j < info->num_fences; j++)
 				dev_err(device->dev, "       [%u] FENCE %s\n",
 					i, info->fences[j].name);
 			break;
 		}
+		case KGSL_CMD_SYNCPOINT_TYPE_TIMELINE: {
+			int j;
+			struct event_timeline_info *info = event->priv;
+
+			dev_err(device->dev, "       [%u] FENCE %s\n",
+				i, dma_fence_is_signaled(event->fence) ?
+					"signaled" : "not signaled");
+
+			for (j = 0; info && info[j].timeline; j++)
+				dev_err(device->dev, "       TIMELINE %d SEQNO %lld\n",
+					info[j].timeline, info[j].seqno);
+			break;
+		}
 		}
 	}
 
@@ -247,7 +285,30 @@ static void drawobj_destroy_sparse(struct kgsl_drawobj *drawobj)
 	}
 }
 
-static void drawobj_destroy_sync(struct kgsl_drawobj *drawobj)
+static void drawobj_sync_timeline_fence_work(struct irq_work *work)
+{
+	struct kgsl_drawobj_sync_event *event = container_of(work,
+		struct kgsl_drawobj_sync_event, work);
+
+	dma_fence_put(event->fence);
+	kgsl_drawobj_put(&event->syncobj->base);
+}
+
+static void drawobj_sync_timeline_fence_callback(struct dma_fence *f,
+		struct dma_fence_cb *cb)
+{
+	struct kgsl_drawobj_sync_event *event = container_of(cb,
+		struct kgsl_drawobj_sync_event, cb);
+
+	/*
+	 * Mark the event as synced and then fire off a worker to handle
+	 * removing the fence
+	 */
+	if (drawobj_sync_expire(event->device, event))
+		irq_work_queue(&event->work);
+}
+
+static void syncobj_destroy(struct kgsl_drawobj *drawobj)
 {
 	struct kgsl_drawobj_sync *syncobj = SYNCOBJ(drawobj);
 	unsigned int i;
@@ -285,6 +346,11 @@ static void drawobj_destroy_sync(struct kgsl_drawobj *drawobj)
 			kgsl_sync_fence_async_cancel(event->handle);
 			kgsl_drawobj_put(drawobj);
 			break;
+		case KGSL_CMD_SYNCPOINT_TYPE_TIMELINE:
+			dma_fence_remove_callback(event->fence, &event->cb);
+			dma_fence_put(event->fence);
+			kgsl_drawobj_put(drawobj);
+			break;
 		}
 	}
 
@@ -299,7 +365,20 @@ static void drawobj_destroy_sync(struct kgsl_drawobj *drawobj)
 
 }
 
-static void drawobj_destroy_cmd(struct kgsl_drawobj *drawobj)
+static void timelineobj_destroy(struct kgsl_drawobj *drawobj)
+{
+	struct kgsl_drawobj_timeline *timelineobj = TIMELINEOBJ(drawobj);
+	int i;
+
+	for (i = 0; i < timelineobj->count; i++)
+		kgsl_timeline_put(timelineobj->timelines[i].timeline);
+
+	kvfree(timelineobj->timelines);
+	timelineobj->timelines = NULL;
+	timelineobj->count = 0;
+}
+
+static void cmdobj_destroy(struct kgsl_drawobj *drawobj)
 {
 	struct kgsl_drawobj_cmd *cmdobj = CMDOBJ(drawobj);
 
@@ -330,17 +409,10 @@ static void drawobj_destroy_cmd(struct kgsl_drawobj *drawobj)
  */
 void kgsl_drawobj_destroy(struct kgsl_drawobj *drawobj)
 {
-	if (!drawobj)
+	if (IS_ERR_OR_NULL(drawobj))
 		return;
 
-	if (drawobj->type & SYNCOBJ_TYPE)
+	drawobj->destroy(drawobj);
-		drawobj_destroy_sync(drawobj);
-	else if (drawobj->type & (CMDOBJ_TYPE | MARKEROBJ_TYPE))
-		drawobj_destroy_cmd(drawobj);
-	else if (drawobj->type == SPARSEOBJ_TYPE)
-		drawobj_destroy_sparse(drawobj);
-	else
-		return;
 
 	kgsl_drawobj_put(drawobj);
 }
@@ -349,11 +421,12 @@ EXPORT_SYMBOL(kgsl_drawobj_destroy);
 static bool drawobj_sync_fence_func(void *priv)
 {
 	struct kgsl_drawobj_sync_event *event = priv;
+	struct event_fence_info *info = event ? event->priv : NULL;
 	int i;
 
-	for (i = 0; i < event->info.num_fences; i++)
+	for (i = 0; info && i < info->num_fences; i++)
 		trace_syncpoint_fence_expire(event->syncobj,
-			event->info.fences[i].name);
+			info->fences[i].name);
 
 	/*
 	 * Only call kgsl_drawobj_put() if it's not marked for cancellation
@@ -366,21 +439,108 @@ static bool drawobj_sync_fence_func(void *priv)
 	return false;
 }
 
-/* drawobj_add_sync_fence() - Add a new sync fence syncpoint
+static struct event_timeline_info *
- * @device: KGSL device
+drawobj_get_sync_timeline_priv(void __user *uptr, u64 usize, u32 count)
- * @syncobj: KGSL sync obj to add the sync point to
- * @priv: Private structure passed by the user
- *
- * Add a new fence sync syncpoint to the sync obj.
- */
-static int drawobj_add_sync_fence(struct kgsl_device *device,
-		struct kgsl_drawobj_sync *syncobj, void *priv)
 {
-	struct kgsl_cmd_syncpoint_fence *sync = priv;
+	int i;
+	struct event_timeline_info *priv;
+
+	/* Make sure we don't accidently overflow count */
+	if (count == UINT_MAX)
+		return NULL;
+
+	priv = kcalloc(count + 1, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return NULL;
+
+	for (i = 0; i < count; i++, uptr += usize) {
+		struct kgsl_timeline_val val;
+
+		if (kgsl_copy_struct_from_user(&val, sizeof(val), uptr, usize))
+			continue;
+
+		priv[i].timeline = val.timeline;
+		priv[i].seqno = val.seqno;
+	}
+
+	priv[i].timeline = 0;
+	return priv;
+}
+
+static int drawobj_add_sync_timeline(struct kgsl_device *device,
+
+		struct kgsl_drawobj_sync *syncobj, void __user *uptr,
+		u64 usize)
+{
+	struct kgsl_drawobj *drawobj = DRAWOBJ(syncobj);
+	struct kgsl_cmd_syncpoint_timeline sync;
+	struct kgsl_drawobj_sync_event *event;
+	struct dma_fence *fence;
+	unsigned int id;
+	int ret;
+
+	if (kgsl_copy_struct_from_user(&sync, sizeof(sync), uptr, usize))
+		return -EFAULT;
+
+	fence = kgsl_timelines_to_fence_array(device, sync.timelines,
+		sync.count, sync.timelines_size, false);
+	if (IS_ERR(fence))
+		return PTR_ERR(fence);
+
+	kref_get(&drawobj->refcount);
+
+	id = syncobj->numsyncs++;
+
+	event = &syncobj->synclist[id];
+
+	event->id = id;
+	event->type = KGSL_CMD_SYNCPOINT_TYPE_TIMELINE;
+	event->syncobj = syncobj;
+	event->device = device;
+	event->context = NULL;
+	event->fence = fence;
+	init_irq_work(&event->work, drawobj_sync_timeline_fence_work);
+
+	INIT_LIST_HEAD(&event->cb.node);
+
+	event->priv =
+		drawobj_get_sync_timeline_priv(u64_to_user_ptr(sync.timelines),
+			sync.timelines_size, sync.count);
+
+	/* Set pending flag before adding callback to avoid race */
+	set_bit(event->id, &syncobj->pending);
+
+	ret = dma_fence_add_callback(event->fence,
+		&event->cb, drawobj_sync_timeline_fence_callback);
+
+	if (ret) {
+		clear_bit(event->id, &syncobj->pending);
+
+		if (dma_fence_is_signaled(event->fence)) {
+			trace_syncpoint_fence_expire(syncobj, "signaled");
+			dma_fence_put(event->fence);
+			ret = 0;
+		}
+
+		kgsl_drawobj_put(drawobj);
+	}
+
+	return ret;
+}
+
+static int drawobj_add_sync_fence(struct kgsl_device *device,
+		struct kgsl_drawobj_sync *syncobj, void __user *data,
+		u64 datasize)
+{
+	struct kgsl_cmd_syncpoint_fence sync;
 	struct kgsl_drawobj *drawobj = DRAWOBJ(syncobj);
 	struct kgsl_drawobj_sync_event *event;
+	struct event_fence_info *priv;
 	unsigned int id, i;
 
+	if (kgsl_copy_struct_from_user(&sync, sizeof(sync), data, datasize))
+		return -EFAULT;
+
 	kref_get(&drawobj->refcount);
 
 	id = syncobj->numsyncs++;
@@ -393,11 +553,14 @@ static int drawobj_add_sync_fence(struct kgsl_device *device,
 	event->device = device;
 	event->context = NULL;
 
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+
 	set_bit(event->id, &syncobj->pending);
 
-	event->handle = kgsl_sync_fence_async_wait(sync->fd,
+	event->handle = kgsl_sync_fence_async_wait(sync.fd,
-				drawobj_sync_fence_func, event,
+				drawobj_sync_fence_func, event, priv);
-				&event->info);
+
+	event->priv = priv;
 
 	if (IS_ERR_OR_NULL(event->handle)) {
 		int ret = PTR_ERR(event->handle);
@@ -417,8 +580,8 @@ static int drawobj_add_sync_fence(struct kgsl_device *device,
 		return ret;
 	}
 
-	for (i = 0; i < event->info.num_fences; i++)
+	for (i = 0; priv && i < priv->num_fences; i++)
-		trace_syncpoint_fence(syncobj, event->info.fences[i].name);
+		trace_syncpoint_fence(syncobj, priv->fences[i].name);
 
 	return 0;
 }
@@ -431,12 +594,13 @@ static int drawobj_add_sync_fence(struct kgsl_device *device,
  * Add a new sync point timestamp event to the sync obj.
  */
 static int drawobj_add_sync_timestamp(struct kgsl_device *device,
-		struct kgsl_drawobj_sync *syncobj, void *priv)
+		struct kgsl_drawobj_sync *syncobj,
+		struct kgsl_cmd_syncpoint_timestamp *timestamp)
+
 {
-	struct kgsl_cmd_syncpoint_timestamp *sync = priv;
 	struct kgsl_drawobj *drawobj = DRAWOBJ(syncobj);
 	struct kgsl_context *context = kgsl_context_get(device,
-		sync->context_id);
+		timestamp->context_id);
 	struct kgsl_drawobj_sync_event *event;
 	int ret = -EINVAL;
 	unsigned int id;
@@ -457,10 +621,10 @@ static int drawobj_add_sync_timestamp(struct kgsl_device *device,
 		kgsl_readtimestamp(device, context, KGSL_TIMESTAMP_QUEUED,
 			&queued);
 
-		if (timestamp_cmp(sync->timestamp, queued) > 0) {
+		if (timestamp_cmp(timestamp->timestamp, queued) > 0) {
 			dev_err(device->dev,
 				     "Cannot create syncpoint for future timestamp %d (current %d)\n",
-				     sync->timestamp, queued);
+				     timestamp->timestamp, queued);
 			goto done;
 		}
 	}
@@ -475,19 +639,20 @@ static int drawobj_add_sync_timestamp(struct kgsl_device *device,
 	event->type = KGSL_CMD_SYNCPOINT_TYPE_TIMESTAMP;
 	event->syncobj = syncobj;
 	event->context = context;
-	event->timestamp = sync->timestamp;
+	event->timestamp = timestamp->timestamp;
 	event->device = device;
 
 	set_bit(event->id, &syncobj->pending);
 
-	ret = kgsl_add_event(device, &context->events, sync->timestamp,
+	ret = kgsl_add_event(device, &context->events, timestamp->timestamp,
 		drawobj_sync_func, event);
 
 	if (ret) {
 		clear_bit(event->id, &syncobj->pending);
 		kgsl_drawobj_put(drawobj);
 	} else {
-		trace_syncpoint_timestamp(syncobj, context, sync->timestamp);
+		trace_syncpoint_timestamp(syncobj, context,
+			timestamp->timestamp);
 	}
 
 done:
@@ -497,6 +662,19 @@ static int drawobj_add_sync_timestamp(struct kgsl_device *device,
 	return ret;
 }
 
+static int drawobj_add_sync_timestamp_from_user(struct kgsl_device *device,
+		struct kgsl_drawobj_sync *syncobj, void __user *data,
+		u64 datasize)
+{
+	struct kgsl_cmd_syncpoint_timestamp timestamp;
+
+	if (kgsl_copy_struct_from_user(&timestamp, sizeof(timestamp),
+			data, datasize))
+		return -EFAULT;
+
+	return drawobj_add_sync_timestamp(device, syncobj, &timestamp);
+}
+
 /**
  * kgsl_drawobj_sync_add_sync() - Add a sync point to a command
  * batch
@@ -511,44 +689,22 @@ int kgsl_drawobj_sync_add_sync(struct kgsl_device *device,
 	struct kgsl_drawobj_sync *syncobj,
 	struct kgsl_cmd_syncpoint *sync)
 {
-	void *priv;
-	int ret, psize;
 	struct kgsl_drawobj *drawobj = DRAWOBJ(syncobj);
-	int (*func)(struct kgsl_device *device,
-			struct kgsl_drawobj_sync *syncobj,
-			void *priv);
 
-	switch (sync->type) {
+	if (sync->type == KGSL_CMD_SYNCPOINT_TYPE_TIMESTAMP)
-	case KGSL_CMD_SYNCPOINT_TYPE_TIMESTAMP:
+		return drawobj_add_sync_timestamp_from_user(device,
-		psize = sizeof(struct kgsl_cmd_syncpoint_timestamp);
+			syncobj, sync->priv, sync->size);
-		func = drawobj_add_sync_timestamp;
+	else if (sync->type == KGSL_CMD_SYNCPOINT_TYPE_FENCE)
-		break;
+		return drawobj_add_sync_fence(device,
-	case KGSL_CMD_SYNCPOINT_TYPE_FENCE:
+			syncobj, sync->priv, sync->size);
-		psize = sizeof(struct kgsl_cmd_syncpoint_fence);
+	else if (sync->type == KGSL_CMD_SYNCPOINT_TYPE_TIMELINE)
-		func = drawobj_add_sync_fence;
+		return drawobj_add_sync_timeline(device,
-		break;
+			syncobj, sync->priv, sync->size);
-	default:
-		dev_err(device->dev,
-			     "bad syncpoint type ctxt %d type 0x%x size %zu\n",
-			     drawobj->context->id, sync->type, sync->size);
-		return -EINVAL;
-	}
 
-	if (sync->size != psize) {
+	dev_err(device->dev, "bad syncpoint type %d for ctxt %d\n",
-		dev_err(device->dev,
+		sync->type, drawobj->context->id);
-			     "bad syncpoint size ctxt %d type 0x%x size %zu\n",
-			     drawobj->context->id, sync->type, sync->size);
-		return -EINVAL;
-	}
 
-	priv = memdup_user(sync->priv, sync->size);
+	return -EINVAL;
-	if (IS_ERR(priv))
-		return PTR_ERR(priv);
-
-	ret = func(device, syncobj, priv);
-	kfree(priv);
-
-	return ret;
 }
 
 static void add_profiling_buffer(struct kgsl_device *device,
@@ -558,6 +714,7 @@ static void add_profiling_buffer(struct kgsl_device *device,
 {
 	struct kgsl_mem_entry *entry;
 	struct kgsl_drawobj *drawobj = DRAWOBJ(cmdobj);
+	u64 start;
 
 	if (!(drawobj->flags & KGSL_DRAWOBJ_PROFILING))
 		return;
@@ -574,7 +731,14 @@ static void add_profiling_buffer(struct kgsl_device *device,
 			gpuaddr);
 
 	if (entry != NULL) {
-		if (!kgsl_gpuaddr_in_memdesc(&entry->memdesc, gpuaddr, size)) {
+		start = id ? (entry->memdesc.gpuaddr + offset) : gpuaddr;
+		/*
+		 * Make sure there is enough room in the object to store the
+		 * entire profiling buffer object
+		 */
+		if (!kgsl_gpuaddr_in_memdesc(&entry->memdesc, gpuaddr, size) ||
+			!kgsl_gpuaddr_in_memdesc(&entry->memdesc, start,
+				sizeof(struct kgsl_drawobj_profiling_buffer))) {
 			kgsl_mem_entry_put(entry);
 			entry = NULL;
 		}
@@ -587,28 +751,7 @@ static void add_profiling_buffer(struct kgsl_device *device,
 		return;
 	}
 
-
+	cmdobj->profiling_buffer_gpuaddr = start;
-	if (!id) {
-		cmdobj->profiling_buffer_gpuaddr = gpuaddr;
-	} else {
-		u64 off = offset + sizeof(struct kgsl_drawobj_profiling_buffer);
-
-		/*
-		 * Make sure there is enough room in the object to store the
-		 * entire profiling buffer object
-		 */
-		if (off < offset || off >= entry->memdesc.size) {
-			dev_err(device->dev,
-				"ignore invalid profile offset ctxt %d id %d offset %lld gpuaddr %llx size %lld\n",
-			drawobj->context->id, id, offset, gpuaddr, size);
-			kgsl_mem_entry_put(entry);
-			return;
-		}
-
-		cmdobj->profiling_buffer_gpuaddr =
-			entry->memdesc.gpuaddr + offset;
-	}
-
 	cmdobj->profiling_buf_entry = entry;
 }
 
@@ -673,26 +816,16 @@ int kgsl_drawobj_cmd_add_ibdesc(struct kgsl_device *device,
 	return 0;
 }
 
-static void *_drawobj_create(struct kgsl_device *device,
+static int drawobj_init(struct kgsl_device *device,
-	struct kgsl_context *context, unsigned int size,
+	struct kgsl_context *context, struct kgsl_drawobj *drawobj,
-	unsigned int type)
+	int type)
 {
-	void *obj = kzalloc(size, GFP_KERNEL);
-	struct kgsl_drawobj *drawobj;
-
-	if (obj == NULL)
-		return ERR_PTR(-ENOMEM);
-
 	/*
 	 * Increase the reference count on the context so it doesn't disappear
 	 * during the lifetime of this object
 	 */
-	if (!_kgsl_context_get(context)) {
+	if (!_kgsl_context_get(context))
-		kfree(obj);
+		return -ENOENT;
-		return ERR_PTR(-ENOENT);
-	}
-
-	drawobj = obj;
 
 	kref_init(&drawobj->refcount);
 
@@ -700,7 +833,92 @@ static void *_drawobj_create(struct kgsl_device *device,
 	drawobj->context = context;
 	drawobj->type = type;
 
-	return obj;
+	return 0;
+}
+
+struct kgsl_drawobj_timeline *
+kgsl_drawobj_timeline_create(struct kgsl_device *device,
+		struct kgsl_context *context)
+{
+	int ret;
+	struct kgsl_drawobj_timeline *timelineobj =
+		kzalloc(sizeof(*timelineobj), GFP_KERNEL);
+
+	if (!timelineobj)
+		return ERR_PTR(-ENOMEM);
+
+	ret = drawobj_init(device, context, &timelineobj->base,
+		TIMELINEOBJ_TYPE);
+	if (ret) {
+		kfree(timelineobj);
+		return ERR_PTR(ret);
+	}
+
+	timelineobj->base.destroy = timelineobj_destroy;
+	timelineobj->base.destroy_object = timelineobj_destroy_object;
+
+	return timelineobj;
+}
+
+int kgsl_drawobj_add_timeline(struct kgsl_device_private *dev_priv,
+		struct kgsl_drawobj_timeline *timelineobj,
+		void __user *src, u64 cmdsize)
+{
+	struct kgsl_gpu_aux_command_timeline cmd;
+	int i, ret;
+
+	if (kgsl_copy_struct_from_user(&cmd, sizeof(cmd), src, cmdsize))
+		return -EFAULT;
+
+	if (!cmd.count)
+		return -EINVAL;
+
+	timelineobj->timelines = kvcalloc(cmd.count,
+		sizeof(*timelineobj->timelines),
+		GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN);
+	if (!timelineobj->timelines)
+		return -ENOMEM;
+
+	src = u64_to_user_ptr(cmd.timelines);
+
+	for (i = 0; i < cmd.count; i++) {
+		struct kgsl_timeline_val val;
+
+		if (kgsl_copy_struct_from_user(&val, sizeof(val), src,
+			cmd.timelines_size)) {
+			ret = -EFAULT;
+			goto err;
+		}
+
+		if (val.padding) {
+			ret = -EINVAL;
+			goto err;
+		}
+
+		timelineobj->timelines[i].timeline =
+			kgsl_timeline_by_id(dev_priv->device,
+				val.timeline);
+
+		if (!timelineobj->timelines[i].timeline) {
+			ret = -ENODEV;
+			goto err;
+		}
+
+		trace_kgsl_drawobj_timeline(val.timeline, val.seqno);
+		timelineobj->timelines[i].seqno = val.seqno;
+
+		src += cmd.timelines_size;
+	}
+
+	timelineobj->count = cmd.count;
+	return 0;
+err:
+	for (i = 0; i < cmd.count; i++)
+		kgsl_timeline_put(timelineobj->timelines[i].timeline);
+
+	kvfree(timelineobj->timelines);
+	timelineobj->timelines = NULL;
+	return ret;
 }
 
 /**
@@ -715,11 +933,24 @@ struct kgsl_drawobj_sparse *kgsl_drawobj_sparse_create(
 		struct kgsl_device *device,
 		struct kgsl_context *context, unsigned int flags)
 {
-	struct kgsl_drawobj_sparse *sparseobj = _drawobj_create(device,
+	int ret;
-		context, sizeof(*sparseobj), SPARSEOBJ_TYPE);
+	struct kgsl_drawobj_sparse *sparseobj =
+			kzalloc(sizeof(*sparseobj), GFP_KERNEL);
 
-	if (!IS_ERR(sparseobj))
+	if (!sparseobj)
-		INIT_LIST_HEAD(&sparseobj->sparselist);
+		return ERR_PTR(-ENOMEM);
+
+	ret = drawobj_init(device,
+		context, &sparseobj->base, SPARSEOBJ_TYPE);
+	if (ret) {
+		kfree(sparseobj);
+		return ERR_PTR(ret);
+	}
+
+	INIT_LIST_HEAD(&sparseobj->sparselist);
+
+	sparseobj->base.destroy = drawobj_destroy_sparse;
+	sparseobj->base.destroy_object = sparseobj_destroy_object;
 
 	return sparseobj;
 }
@@ -735,12 +966,23 @@ struct kgsl_drawobj_sparse *kgsl_drawobj_sparse_create(
 struct kgsl_drawobj_sync *kgsl_drawobj_sync_create(struct kgsl_device *device,
 		struct kgsl_context *context)
 {
-	struct kgsl_drawobj_sync *syncobj = _drawobj_create(device,
+	struct kgsl_drawobj_sync *syncobj =
-		context, sizeof(*syncobj), SYNCOBJ_TYPE);
+		kzalloc(sizeof(*syncobj), GFP_KERNEL);
+	int ret;
 
-	/* Add a timer to help debug sync deadlocks */
+	if (!syncobj)
-	if (!IS_ERR(syncobj))
+		return ERR_PTR(-ENOMEM);
-		timer_setup(&syncobj->timer, syncobj_timer, 0);
+
+	ret = drawobj_init(device, context, &syncobj->base, SYNCOBJ_TYPE);
+	if (ret) {
+		kfree(syncobj);
+		return ERR_PTR(ret);
+	}
+
+	syncobj->base.destroy = syncobj_destroy;
+	syncobj->base.destroy_object = syncobj_destroy_object;
+
+	timer_setup(&syncobj->timer, syncobj_timer, 0);
 
 	return syncobj;
 }
@@ -759,27 +1001,37 @@ struct kgsl_drawobj_cmd *kgsl_drawobj_cmd_create(struct kgsl_device *device,
 		struct kgsl_context *context, unsigned int flags,
 		unsigned int type)
 {
-	struct kgsl_drawobj_cmd *cmdobj = _drawobj_create(device,
+	struct kgsl_drawobj_cmd *cmdobj = kzalloc(sizeof(*cmdobj), GFP_KERNEL);
-		context, sizeof(*cmdobj),
+	int ret;
+
+	if (!cmdobj)
+		return ERR_PTR(-ENOMEM);
+
+	ret = drawobj_init(device, context, &cmdobj->base,
 		(type & (CMDOBJ_TYPE | MARKEROBJ_TYPE)));
-
+	if (ret) {
-	if (!IS_ERR(cmdobj)) {
+		kfree(cmdobj);
-		/* sanitize our flags for drawobj's */
+		return ERR_PTR(ret);
-		cmdobj->base.flags = flags & (KGSL_DRAWOBJ_CTX_SWITCH
-				| KGSL_DRAWOBJ_MARKER
-				| KGSL_DRAWOBJ_END_OF_FRAME
-				| KGSL_DRAWOBJ_PWR_CONSTRAINT
-				| KGSL_DRAWOBJ_MEMLIST
-				| KGSL_DRAWOBJ_PROFILING
-				| KGSL_DRAWOBJ_PROFILING_KTIME);
-
-		INIT_LIST_HEAD(&cmdobj->cmdlist);
-		INIT_LIST_HEAD(&cmdobj->memlist);
-
-		if (type & CMDOBJ_TYPE)
-			atomic_inc(&context->proc_priv->cmd_count);
 	}
 
+	cmdobj->base.destroy = cmdobj_destroy;
+	cmdobj->base.destroy_object = cmdobj_destroy_object;
+
+	/* sanitize our flags for drawobjs */
+	cmdobj->base.flags = flags & (KGSL_DRAWOBJ_CTX_SWITCH
+		| KGSL_DRAWOBJ_MARKER
+		| KGSL_DRAWOBJ_END_OF_FRAME
+		| KGSL_DRAWOBJ_PWR_CONSTRAINT
+		| KGSL_DRAWOBJ_MEMLIST
+		| KGSL_DRAWOBJ_PROFILING
+		| KGSL_DRAWOBJ_PROFILING_KTIME);
+
+	INIT_LIST_HEAD(&cmdobj->cmdlist);
+	INIT_LIST_HEAD(&cmdobj->memlist);
+
+	if (type & CMDOBJ_TYPE)
+		atomic_inc(&context->proc_priv->cmd_count);
+
 	return cmdobj;
 }
 
@@ -1114,6 +1366,36 @@ int kgsl_drawobj_cmd_add_memlist(struct kgsl_device *device,
 	return 0;
 }
 
+struct kgsl_drawobj_sync *
+kgsl_drawobj_create_timestamp_syncobj(struct kgsl_device *device,
+		struct kgsl_context *context, unsigned int timestamp)
+{
+	struct kgsl_drawobj_sync *syncobj;
+	struct kgsl_cmd_syncpoint_timestamp priv;
+	int ret;
+
+	syncobj = kgsl_drawobj_sync_create(device, context);
+	if (IS_ERR(syncobj))
+		return syncobj;
+
+	syncobj->synclist = kzalloc(sizeof(*syncobj->synclist), GFP_KERNEL);
+	if (!syncobj->synclist) {
+		kgsl_drawobj_destroy(DRAWOBJ(syncobj));
+		return ERR_PTR(-ENOMEM);
+	}
+
+	priv.timestamp = timestamp;
+	priv.context_id = context->id;
+
+	ret = drawobj_add_sync_timestamp(device, syncobj, &priv);
+	if (ret) {
+		kgsl_drawobj_destroy(DRAWOBJ(syncobj));
+		return ERR_PTR(ret);
+	}
+
+	return syncobj;
+}
+
 int kgsl_drawobj_sync_add_synclist(struct kgsl_device *device,
 		struct kgsl_drawobj_sync *syncobj, void __user *ptr,
 		unsigned int size, unsigned int count)

drivers/gpu/msm/kgsl_drawobj.h

@@ -1,11 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2019, 2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef __KGSL_DRAWOBJ_H
 #define __KGSL_DRAWOBJ_H
 
+#include <linux/dma-fence.h>
+#include <linux/irq_work.h>
 #include <linux/kref.h>
 
 #define DRAWOBJ(obj) (&obj->base)
@@ -15,11 +17,14 @@
 	container_of(obj, struct kgsl_drawobj_cmd, base)
 #define SPARSEOBJ(obj) \
 	container_of(obj, struct kgsl_drawobj_sparse, base)
+#define TIMELINEOBJ(obj) \
+	container_of(obj, struct kgsl_drawobj_timeline, base)
 
 #define CMDOBJ_TYPE     BIT(0)
 #define MARKEROBJ_TYPE  BIT(1)
 #define SYNCOBJ_TYPE    BIT(2)
 #define SPARSEOBJ_TYPE  BIT(3)
+#define TIMELINEOBJ_TYPE    BIT(4)
 
 /**
  * struct kgsl_drawobj - KGSL drawobj descriptor
@@ -37,6 +42,10 @@ struct kgsl_drawobj {
 	uint32_t timestamp;
 	unsigned long flags;
 	struct kref refcount;
+	/** @destroy: Callback function to take down the object */
+	void (*destroy)(struct kgsl_drawobj *drawobj);
+	/** @destroy_object: Callback function to free the object memory */
+	void (*destroy_object)(struct kgsl_drawobj *drawobj);
 };
 
 /**
@@ -100,6 +109,22 @@ struct kgsl_drawobj_sync {
 	unsigned long timeout_jiffies;
 };
 
+/**
+ * struct kgsl_drawobj_timeline - KGSL timeline signal operation
+ */
+struct kgsl_drawobj_timeline {
+	/** @base: &struct kgsl_drawobj container */
+	struct kgsl_drawobj base;
+	struct {
+		/** @timeline: Pointer to a &struct kgsl_timeline */
+		struct kgsl_timeline *timeline;
+		/** @seqno: Sequence number to signal */
+		u64 seqno;
+	} *timelines;
+	/** @count: Number of items in timelines */
+	int count;
+};
+
 #define KGSL_FENCE_NAME_LEN 74
 
 struct fence_info {
@@ -111,9 +136,14 @@ struct event_fence_info {
 	int num_fences;
 };
 
+struct event_timeline_info {
+	u64 seqno;
+	u32 timeline;
+};
+
 /**
  * struct kgsl_drawobj_sync_event
- * @id: identifer (positiion within the pending bitmap)
+ * @id: Identifer (position within the pending bitmap)
  * @type: Syncpoint type
  * @syncobj: Pointer to the syncobj that owns the sync event
  * @context: KGSL context for whose timestamp we want to
@@ -121,7 +151,6 @@ struct event_fence_info {
  * @timestamp: Pending timestamp for the event
  * @handle: Pointer to a sync fence handle
  * @device: Pointer to the KGSL device
- * @info: structure to hold info about the fence
  */
 struct kgsl_drawobj_sync_event {
 	unsigned int id;
@@ -131,7 +160,17 @@ struct kgsl_drawobj_sync_event {
 	unsigned int timestamp;
 	struct kgsl_sync_fence_cb *handle;
 	struct kgsl_device *device;
-	struct event_fence_info info;
+	/** @priv: Type specific private information */
+	void *priv;
+	/**
+	 * @fence: Pointer to a dma fence for KGSL_CMD_SYNCPOINT_TYPE_TIMELINE
+	 * events
+	 */
+	struct dma_fence *fence;
+	/** @cb: Callback struct for KGSL_CMD_SYNCPOINT_TYPE_TIMELINE */
+	struct dma_fence_cb cb;
+	/** @work : irq worker for KGSL_CMD_SYNCPOINT_TYPE_TIMELINE */
+	struct irq_work work;
 };
 
 /**
@@ -240,4 +279,44 @@ static inline void kgsl_drawobj_put(struct kgsl_drawobj *drawobj)
 		kref_put(&drawobj->refcount, kgsl_drawobj_destroy_object);
 }
 
+/**
+ * kgsl_drawobj_create_timestamp_syncobj - Create a syncobj for a timestamp
+ * @device: A GPU device handle
+ * @context: Draw context for the syncobj
+ * @timestamp: Timestamp to sync on
+ *
+ * Create a sync object for @timestamp on @context.
+ * Return: A pointer to the sync object
+ */
+struct kgsl_drawobj_sync *
+kgsl_drawobj_create_timestamp_syncobj(struct kgsl_device *device,
+		struct kgsl_context *context, unsigned int timestamp);
+
+
+/**
+ * kgsl_drawobj_timeline_create - Create a timeline draw object
+ * @device: A GPU device handle
+ * @context: Draw context for the drawobj
+ *
+ * Create a timeline draw object on @context.
+ * Return: A pointer to the draw object
+ */
+struct kgsl_drawobj_timeline *
+kgsl_drawobj_timeline_create(struct kgsl_device *device,
+		struct kgsl_context *context);
+
+/**
+ * kgsl_drawobj_add_timeline - Add a timeline to a timeline drawobj
+ * @dev_priv: Pointer to the process private data
+ * @timelineobj: Pointer to a timeline drawobject
+ * @src: Ponter to the &struct kgsl_timeline_val from userspace
+ * @cmdsize: size of the object in @src
+ *
+ * Add a timeline to an draw object.
+ * Return: 0 on success or negative on failure
+ */
+int kgsl_drawobj_add_timeline(struct kgsl_device_private *dev_priv,
+		struct kgsl_drawobj_timeline *timelineobj,
+		void __user *src, u64 cmdsize);
+
 #endif /* __KGSL_DRAWOBJ_H */

drivers/gpu/msm/kgsl_ioctl.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2008-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2008-2019, 2021, The Linux Foundation. All rights reserved.
  */
 
 #include "kgsl_device.h"
@@ -84,6 +84,20 @@ static const struct kgsl_ioctl kgsl_ioctl_funcs[] = {
 			kgsl_ioctl_sparse_bind),
 	KGSL_IOCTL_FUNC(IOCTL_KGSL_GPU_SPARSE_COMMAND,
 			kgsl_ioctl_gpu_sparse_command),
+	KGSL_IOCTL_FUNC(IOCTL_KGSL_GPU_AUX_COMMAND,
+			kgsl_ioctl_gpu_aux_command),
+	KGSL_IOCTL_FUNC(IOCTL_KGSL_TIMELINE_CREATE,
+			kgsl_ioctl_timeline_create),
+	KGSL_IOCTL_FUNC(IOCTL_KGSL_TIMELINE_WAIT,
+			kgsl_ioctl_timeline_wait),
+	KGSL_IOCTL_FUNC(IOCTL_KGSL_TIMELINE_FENCE_GET,
+			kgsl_ioctl_timeline_fence_get),
+	KGSL_IOCTL_FUNC(IOCTL_KGSL_TIMELINE_QUERY,
+			kgsl_ioctl_timeline_query),
+	KGSL_IOCTL_FUNC(IOCTL_KGSL_TIMELINE_SIGNAL,
+			kgsl_ioctl_timeline_signal),
+	KGSL_IOCTL_FUNC(IOCTL_KGSL_TIMELINE_DESTROY,
+			kgsl_ioctl_timeline_destroy),
 };
 
 long kgsl_ioctl_copy_in(unsigned int kernel_cmd, unsigned int user_cmd,
@@ -167,8 +181,6 @@ long kgsl_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
 			return device->ftbl->compat_ioctl(dev_priv, cmd, arg);
 		else if (device->ftbl->ioctl != NULL)
 			return device->ftbl->ioctl(dev_priv, cmd, arg);
-
-		dev_err(device->dev, "invalid ioctl code 0x%08X\n", cmd);
 	}
 
 	return ret;

drivers/gpu/msm/kgsl_pool.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <asm/cacheflush.h>
@@ -176,9 +176,7 @@ kgsl_pool_reduce(unsigned int target_pages, bool exit)
 		if (!pool->allocation_allowed && !exit)
 			continue;
 
-		total_pages -= pcount;
+		nr_removed = total_pages - target_pages - pcount;
-
-		nr_removed = total_pages - target_pages;
 		if (nr_removed <= 0)
 			return pcount;
 

drivers/gpu/msm/kgsl_sharedmem.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2002,2007-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2002,2007-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <asm/cacheflush.h>
@@ -171,7 +171,18 @@ imported_mem_show(struct kgsl_process_private *priv,
 			}
 		}
 
-		kgsl_mem_entry_put(entry);
+		/*
+		 * If refcount on mem entry is the last refcount, we will
+		 * call kgsl_mem_entry_destroy and detach it from process
+		 * list. When there is no refcount on the process private,
+		 * we will call kgsl_destroy_process_private to do cleanup.
+		 * During cleanup, we will try to remove the same sysfs
+		 * node which is in use by the current thread and this
+		 * situation will end up in a deadloack.
+		 * To avoid this situation, use a worker to put the refcount
+		 * on mem entry.
+		 */
+		kgsl_mem_entry_put_deferred(entry);
 		spin_lock(&priv->mem_lock);
 	}
 	spin_unlock(&priv->mem_lock);
@@ -247,13 +258,9 @@ static ssize_t process_sysfs_store(struct kobject *kobj,
 	return -EIO;
 }
 
+/* Dummy release function - we have nothing to do here */
 static void process_sysfs_release(struct kobject *kobj)
 {
-	struct kgsl_process_private *priv;
-
-	priv = container_of(kobj, struct kgsl_process_private, kobj);
-	/* Put the refcount we got in kgsl_process_init_sysfs */
-	kgsl_process_private_put(priv);
 }
 
 static const struct sysfs_ops process_sysfs_ops = {
@@ -301,9 +308,6 @@ void kgsl_process_init_sysfs(struct kgsl_device *device,
 {
 	int i;
 
-	/* Keep private valid until the sysfs enries are removed. */
-	kgsl_process_private_get(private);
-
 	if (kobject_init_and_add(&private->kobj, &process_ktype,
 		kgsl_driver.prockobj, "%d", pid_nr(private->pid))) {
 		dev_err(device->dev, "Unable to add sysfs for process %d\n",
@@ -1236,7 +1240,8 @@ void kgsl_sharedmem_free(struct kgsl_memdesc *memdesc)
 
 	if (memdesc->sgt) {
 		sg_free_table(memdesc->sgt);
-		kvfree(memdesc->sgt);
+		kfree(memdesc->sgt);
+		memdesc->sgt = NULL;
 	}
 
 	memdesc->page_count = 0;