[PATCH] sky2: receive queue watermark tweak
This patch makes the receive performance on some systems go from 714MB/s to 941MB/s. It adjusts the watermark of the receive queue to be lower, thereby avoiding excess hardware flow control. This is most important on the systems which have little/no additional buffering. Signed-off-by: Stephen Hemminger <shemminger@osdl.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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2 changed files with 9 additions and 3 deletions
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@ -1062,11 +1062,16 @@ static int sky2_rx_start(struct sky2_port *sky2)
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sky2->rx_put = sky2->rx_next = 0;
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sky2_qset(hw, rxq);
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/* On PCI express lowering the watermark gives better performance */
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if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
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sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
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/* These chips have no ram buffer?
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* MAC Rx RAM Read is controlled by hardware */
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if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
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(hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) {
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/* MAC Rx RAM Read is controlled by hardware */
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(hw->chip_rev == CHIP_REV_YU_EC_U_A1
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|| hw->chip_rev == CHIP_REV_YU_EC_U_B0))
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sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
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}
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sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
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@ -680,6 +680,7 @@ enum {
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BMU_FIFO_ENA | BMU_OP_ON,
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BMU_WM_DEFAULT = 0x600,
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BMU_WM_PEX = 0x80,
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};
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/* Tx BMU Control / Status Registers (Yukon-2) */
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