Blackfin arch: cleanup and unify the ins functions
this also fixes some errors in the ipipe merge Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Mike Frysinger
Bryan Wu
parent
39ca44536d
commit
c250bfb93c
1 changed files with 84 additions and 345 deletions
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@ -1,31 +1,9 @@
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/*
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* File: arch/blackfin/lib/ins.S
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* Based on:
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* Author: Bas Vermeulen <bas@buyways.nl>
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* arch/blackfin/lib/ins.S - ins{bwl} using hardware loops
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*
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* Created: Tue Mar 22 15:27:24 CEST 2005
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* Description: Implementation of ins{bwl} for BlackFin processors using zero overhead loops.
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*
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* Modified:
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* Copyright 2004-2008 Analog Devices Inc.
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* Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* Copyright 2004-2008 Analog Devices Inc.
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* Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/linkage.h>
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@ -33,6 +11,46 @@
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.align 2
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#ifdef CONFIG_IPIPE
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# define DO_CLI \
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[--sp] = rets; \
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[--sp] = (P5:0); \
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sp += -12; \
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call ___ipipe_stall_root_raw; \
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sp += 12; \
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(P5:0) = [sp++];
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# define CLI_INNER_NOP
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#else
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# define DO_CLI cli R3;
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# define CLI_INNER_NOP nop; nop; nop;
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#endif
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#ifdef CONFIG_IPIPE
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# define DO_STI \
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sp += -12; \
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call ___ipipe_unstall_root_raw; \
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sp += 12; \
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2: rets = [sp++];
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#else
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# define DO_STI 2: sti R3;
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#endif
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#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
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# define CLI_OUTER DO_CLI;
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# define STI_OUTER DO_STI;
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# define CLI_INNER 1:
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# if ANOMALY_05000416
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# define STI_INNER nop; 2: nop;
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# else
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# define STI_INNER 2:
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# endif
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#else
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# define CLI_OUTER
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# define STI_OUTER
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# define CLI_INNER 1: DO_CLI; CLI_INNER_NOP;
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# define STI_INNER DO_STI;
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#endif
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/*
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* Reads on the Blackfin are speculative. In Blackfin terms, this means they
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* can be interrupted at any time (even after they have been issued on to the
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@ -53,327 +71,48 @@
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* buffers in/out of FIFOs.
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*/
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ENTRY(_insl)
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#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
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P0 = R0; /* P0 = port */
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#ifdef CONFIG_IPIPE
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[--sp] = rets
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[--sp] = (P5:0);
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sp += -12
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call ___ipipe_stall_root_raw
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sp += 12
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(P5:0) = [sp++];
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#else
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cli R3;
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#endif
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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SSYNC;
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LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
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.Llong_loop_s: R0 = [P0];
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[P1++] = R0;
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NOP;
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.Llong_loop_e: NOP;
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#ifdef CONFIG_IPIPE
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sp += -12
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call ___ipipe_unstall_root_raw
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sp += 12
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rets = [sp++]
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#else
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sti R3;
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#endif
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RTS;
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#else
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P0 = R0; /* P0 = port */
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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SSYNC;
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LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
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.Llong_loop_s:
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#ifdef CONFIG_IPIPE
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[--sp] = rets
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[--sp] = (P5:0);
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sp += -12
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call ___ipipe_stall_root_raw
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sp += 12
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(P5:0) = [sp++];
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#else
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CLI R3;
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#endif
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NOP; NOP; NOP;
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R0 = [P0];
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[P1++] = R0;
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.Llong_loop_e:
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#ifdef CONFIG_IPIPE
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sp += -12
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call ___ipipe_unstall_root_raw
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sp += 12
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rets = [sp++]
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#else
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STI R3;
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#endif
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RTS;
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#endif
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ENDPROC(_insl)
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#define COMMON_INS(func, ops) \
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ENTRY(_ins##func) \
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P0 = R0; /* P0 = port */ \
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CLI_OUTER; /* 3 instructions before first read access */ \
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P1 = R1; /* P1 = address */ \
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P2 = R2; /* P2 = count */ \
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SSYNC; \
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\
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LSETUP(1f, 2f) LC0 = P2; \
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CLI_INNER; \
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ops; \
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STI_INNER; \
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\
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STI_OUTER; \
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RTS; \
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ENDPROC(_ins##func)
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ENTRY(_insw)
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#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
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P0 = R0; /* P0 = port */
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#ifdef CONFIG_IPIPE
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[--sp] = rets
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[--sp] = (P5:0);
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sp += -12
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call ___ipipe_stall_root_raw
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sp += 12
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(P5:0) = [sp++];
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#else
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cli R3;
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#endif
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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SSYNC;
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LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
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.Lword_loop_s: R0 = W[P0];
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W[P1++] = R0;
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NOP;
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.Lword_loop_e: NOP;
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#ifdef CONFIG_IPIPE
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sp += -12
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call ___ipipe_unstall_root_raw
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sp += 12
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rets = [sp++]
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#else
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sti R3;
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#endif
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RTS;
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#else
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P0 = R0; /* P0 = port */
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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SSYNC;
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LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
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.Lword_loop_s:
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#ifdef CONFIG_IPIPE
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[--sp] = rets
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[--sp] = (P5:0);
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sp += -12
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call ___ipipe_stall_root_raw
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sp += 12
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(P5:0) = [sp++];
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#else
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CLI R3;
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#endif
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NOP; NOP; NOP;
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R0 = W[P0];
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W[P1++] = R0;
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.Lword_loop_e:
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#ifdef CONFIG_IPIPE
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sp += -12
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call ___ipipe_unstall_root_raw
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sp += 12
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rets = [sp++]
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#else
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STI R3;
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#endif
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RTS;
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COMMON_INS(l, \
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R0 = [P0]; \
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[P1++] = R0; \
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)
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#endif
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ENDPROC(_insw)
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COMMON_INS(w, \
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R0 = W[P0]; \
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W[P1++] = R0; \
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)
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ENTRY(_insw_8)
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#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
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P0 = R0; /* P0 = port */
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#ifdef CONFIG_IPIPE
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[--sp] = rets
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[--sp] = (P5:0);
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sp += -12
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call ___ipipe_stall_root_raw
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sp += 12
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(P5:0) = [sp++];
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#else
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cli R3;
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#endif
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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SSYNC;
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LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
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.Lword8_loop_s: R0 = W[P0];
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B[P1++] = R0;
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R0 = R0 >> 8;
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B[P1++] = R0;
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NOP;
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.Lword8_loop_e: NOP;
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#ifdef CONFIG_IPIPE
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sp += -12
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call ___ipipe_unstall_root_raw
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sp += 12
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rets = [sp++]
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#else
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sti R3;
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#endif
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RTS;
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#else
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P0 = R0; /* P0 = port */
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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SSYNC;
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LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
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.Lword8_loop_s:
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#ifdef CONFIG_IPIPE
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[--sp] = rets
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[--sp] = (P5:0);
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sp += -12
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call ___ipipe_stall_root_raw
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sp += 12
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(P5:0) = [sp++];
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#else
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CLI R3;
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#endif
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NOP; NOP; NOP;
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R0 = W[P0];
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B[P1++] = R0;
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R0 = R0 >> 8;
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B[P1++] = R0;
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NOP;
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.Lword8_loop_e:
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#ifdef CONFIG_IPIPE
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sp += -12
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call ___ipipe_unstall_root_raw
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sp += 12
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rets = [sp++]
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#else
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STI R3;
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#endif
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RTS;
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#endif
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ENDPROC(_insw_8)
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COMMON_INS(w_8, \
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R0 = W[P0]; \
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B[P1++] = R0; \
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R0 = R0 >> 8; \
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B[P1++] = R0; \
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)
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ENTRY(_insb)
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#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
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P0 = R0; /* P0 = port */
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#ifdef CONFIG_IPIPE
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[--sp] = rets
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[--sp] = (P5:0);
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sp += -12
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call ___ipipe_stall_root_raw
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sp += 12
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(P5:0) = [sp++];
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#else
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cli R3;
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#endif
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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SSYNC;
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LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
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.Lbyte_loop_s: R0 = B[P0];
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B[P1++] = R0;
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NOP;
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.Lbyte_loop_e: NOP;
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#ifdef CONFIG_IPIPE
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sp += -12
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call ___ipipe_unstall_root_raw
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sp += 12
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rets = [sp++]
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#else
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sti R3;
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#endif
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RTS;
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#else
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P0 = R0; /* P0 = port */
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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SSYNC;
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LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
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.Lbyte_loop_s:
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#ifdef CONFIG_IPIPE
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[--sp] = rets
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[--sp] = (P5:0);
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sp += -12
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call ___ipipe_stall_root_raw
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sp += 12
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(P5:0) = [sp++];
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#else
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CLI R3;
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#endif
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NOP; NOP; NOP;
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R0 = B[P0];
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B[P1++] = R0;
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.Lbyte_loop_e:
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#ifdef CONFIG_IPIPE
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sp += -12
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call ___ipipe_unstall_root_raw
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sp += 12
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rets = [sp++]
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#else
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STI R3;
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#endif
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RTS;
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#endif
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ENDPROC(_insb)
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COMMON_INS(b, \
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R0 = B[P0]; \
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B[P1++] = R0; \
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)
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ENTRY(_insl_16)
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#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
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P0 = R0; /* P0 = port */
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#ifdef CONFIG_IPIPE
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[--sp] = rets
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[--sp] = (P5:0);
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sp += -12
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call ___ipipe_stall_root_raw
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sp += 12
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(P5:0) = [sp++];
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#else
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cli R3;
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#endif
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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SSYNC;
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LSETUP( .Llong16_loop_s, .Llong16_loop_e) LC0 = P2;
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.Llong16_loop_s: R0 = [P0];
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W[P1++] = R0;
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R0 = R0 >> 16;
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W[P1++] = R0;
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NOP;
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.Llong16_loop_e: NOP;
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#ifdef CONFIG_IPIPE
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sp += -12
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call ___ipipe_unstall_root_raw
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sp += 12
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rets = [sp++]
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#else
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sti R3;
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#endif
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RTS;
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#else
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P0 = R0; /* P0 = port */
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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SSYNC;
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LSETUP( .Llong16_loop_s, .Llong16_loop_e) LC0 = P2;
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.Llong16_loop_s:
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#ifdef CONFIG_IPIPE
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[--sp] = rets
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[--sp] = (P5:0);
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sp += -12
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call ___ipipe_stall_root_raw
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sp += 12
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(P5:0) = [sp++];
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#else
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CLI R3;
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#endif
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NOP; NOP; NOP;
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R0 = [P0];
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W[P1++] = R0;
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R0 = R0 >> 16;
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W[P1++] = R0;
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.Llong16_loop_e:
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#ifdef CONFIG_IPIPE
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sp += -12
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call ___ipipe_unstall_root_raw
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sp += 12
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rets = [sp++]
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#else
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STI R3;
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#endif
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RTS;
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#endif
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ENDPROC(_insl_16)
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COMMON_INS(l_16, \
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R0 = [P0]; \
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W[P1++] = R0; \
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R0 = R0 >> 16; \
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W[P1++] = R0; \
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)
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