OMAP2: PRCM: fix some SHIFT macros that were actually bitmasks
After Charu's GPIO hwmod patches, GPIO initialization on N800 emits the following messages for all GPIO banks: omap_hwmod: gpio1: cannot be enabled (3) This is due to OMAP24XX_ST_GPIOS_SHIFT being defined as a bitmask. Fix this and also fix two other macros that had the same problem. Thanks to Tony Lindgren <tony@atomide.com> for originally reporting this bug. Signed-off-by: Paul Walmsley <paul@pwsan.com Cc: Charulatha Varadarajan <charu@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
parent
e83df17f17
commit
c2015dc88a
1 changed files with 6 additions and 5 deletions
|
@ -243,13 +243,14 @@
|
|||
#define OMAP24XX_EN_GPT1_MASK (1 << 0)
|
||||
|
||||
/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
|
||||
#define OMAP24XX_ST_GPIOS_SHIFT (1 << 2)
|
||||
#define OMAP24XX_ST_GPIOS_MASK 2
|
||||
#define OMAP24XX_ST_GPT1_SHIFT (1 << 0)
|
||||
#define OMAP24XX_ST_GPT1_MASK 0
|
||||
#define OMAP24XX_ST_GPIOS_SHIFT 2
|
||||
#define OMAP24XX_ST_GPIOS_MASK (1 << 2)
|
||||
#define OMAP24XX_ST_GPT1_SHIFT 0
|
||||
#define OMAP24XX_ST_GPT1_MASK (1 << 0)
|
||||
|
||||
/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
|
||||
#define OMAP2430_ST_MDM_SHIFT (1 << 0)
|
||||
#define OMAP2430_ST_MDM_SHIFT 0
|
||||
#define OMAP2430_ST_MDM_MASK (1 << 0)
|
||||
|
||||
|
||||
/* 3430 register bits shared between CM & PRM registers */
|
||||
|
|
Loading…
Reference in a new issue