ath9k_hw: use the devres API for allocations
Signed-off-by: Felix Fietkau <nbd@openwrt.org> Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
b81950b165
commit
c1b976d2fc
7 changed files with 37 additions and 80 deletions
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@ -470,16 +470,15 @@ static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
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static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
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static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
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{
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{
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#define ATH_ALLOC_BANK(bank, size) do { \
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#define ATH_ALLOC_BANK(bank, size) do { \
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bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
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bank = devm_kzalloc(ah->dev, sizeof(u32) * size, GFP_KERNEL); \
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if (!bank) { \
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if (!bank) \
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ath_err(common, "Cannot allocate RF banks\n"); \
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goto error; \
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return -ENOMEM; \
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} \
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} while (0);
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} while (0);
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath_common *common = ath9k_hw_common(ah);
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BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
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if (AR_SREV_9280_20_OR_LATER(ah))
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return 0;
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ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
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ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
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ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
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ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
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@ -492,35 +491,12 @@ static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
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return 0;
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return 0;
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#undef ATH_ALLOC_BANK
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#undef ATH_ALLOC_BANK
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error:
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ath_err(common, "Cannot allocate RF banks\n");
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return -ENOMEM;
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}
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}
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/**
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* ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
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* @ah: atheros hardware struture
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* For the external AR2133/AR5133 radios banks.
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*/
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static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
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{
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#define ATH_FREE_BANK(bank) do { \
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kfree(bank); \
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bank = NULL; \
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} while (0);
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BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
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ATH_FREE_BANK(ah->analogBank0Data);
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ATH_FREE_BANK(ah->analogBank1Data);
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ATH_FREE_BANK(ah->analogBank2Data);
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ATH_FREE_BANK(ah->analogBank3Data);
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ATH_FREE_BANK(ah->analogBank6Data);
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ATH_FREE_BANK(ah->analogBank6TPCData);
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ATH_FREE_BANK(ah->analogBank7Data);
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ATH_FREE_BANK(ah->bank6Temp);
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#undef ATH_FREE_BANK
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}
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/* *
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/* *
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* ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
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* ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
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* @ah: atheros hardware structure
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* @ah: atheros hardware structure
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@ -1380,7 +1356,7 @@ static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
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conf->radar_inband = 8;
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conf->radar_inband = 8;
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}
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}
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void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
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int ar5008_hw_attach_phy_ops(struct ath_hw *ah)
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{
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{
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struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
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struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
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static const u32 ar5416_cca_regs[6] = {
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static const u32 ar5416_cca_regs[6] = {
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@ -1391,12 +1367,15 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
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AR_PHY_CH1_EXT_CCA,
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AR_PHY_CH1_EXT_CCA,
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AR_PHY_CH2_EXT_CCA
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AR_PHY_CH2_EXT_CCA
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};
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};
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int ret;
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ret = ar5008_hw_rf_alloc_ext_banks(ah);
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if (ret)
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return ret;
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priv_ops->rf_set_freq = ar5008_hw_set_channel;
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priv_ops->rf_set_freq = ar5008_hw_set_channel;
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priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
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priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
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priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
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priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
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priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
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priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
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priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
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priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
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priv_ops->init_bb = ar5008_hw_init_bb;
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priv_ops->init_bb = ar5008_hw_init_bb;
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@ -1421,4 +1400,5 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
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ar5008_hw_set_nf_limits(ah);
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ar5008_hw_set_nf_limits(ah);
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ar5008_hw_set_radar_conf(ah);
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ar5008_hw_set_radar_conf(ah);
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memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
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memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
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return 0;
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}
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}
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@ -102,7 +102,7 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
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u32 size = sizeof(u32) * addac->ia_rows * addac->ia_columns;
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u32 size = sizeof(u32) * addac->ia_rows * addac->ia_columns;
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u32 *data;
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u32 *data;
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data = kmalloc(size, GFP_KERNEL);
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data = devm_kzalloc(ah->dev, size, GFP_KERNEL);
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if (!data)
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if (!data)
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return;
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return;
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@ -409,22 +409,27 @@ void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
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}
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}
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/* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
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/* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
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void ar9002_hw_attach_ops(struct ath_hw *ah)
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int ar9002_hw_attach_ops(struct ath_hw *ah)
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{
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{
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struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
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struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
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struct ath_hw_ops *ops = ath9k_hw_ops(ah);
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struct ath_hw_ops *ops = ath9k_hw_ops(ah);
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int ret;
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priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
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priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
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priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
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priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
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ops->config_pci_powersave = ar9002_hw_configpcipowersave;
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ops->config_pci_powersave = ar9002_hw_configpcipowersave;
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ar5008_hw_attach_phy_ops(ah);
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ret = ar5008_hw_attach_phy_ops(ah);
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if (ret)
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return ret;
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if (AR_SREV_9280_20_OR_LATER(ah))
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if (AR_SREV_9280_20_OR_LATER(ah))
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ar9002_hw_attach_phy_ops(ah);
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ar9002_hw_attach_phy_ops(ah);
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ar9002_hw_attach_calib_ops(ah);
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ar9002_hw_attach_calib_ops(ah);
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ar9002_hw_attach_mac_ops(ah);
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ar9002_hw_attach_mac_ops(ah);
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return 0;
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}
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}
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void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
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void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
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@ -561,8 +561,6 @@ void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
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struct ath_hw_ops *ops = ath9k_hw_ops(ah);
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struct ath_hw_ops *ops = ath9k_hw_ops(ah);
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priv_ops->set_rf_regs = NULL;
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priv_ops->set_rf_regs = NULL;
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priv_ops->rf_alloc_ext_banks = NULL;
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priv_ops->rf_free_ext_banks = NULL;
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priv_ops->rf_set_freq = ar9002_hw_set_channel;
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priv_ops->rf_set_freq = ar9002_hw_set_channel;
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priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
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priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
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priv_ops->olc_init = ar9002_olc_init;
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priv_ops->olc_init = ar9002_olc_init;
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@ -101,22 +101,6 @@ static inline void ath9k_hw_spur_mitigate_freq(struct ath_hw *ah,
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ath9k_hw_private_ops(ah)->spur_mitigate_freq(ah, chan);
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ath9k_hw_private_ops(ah)->spur_mitigate_freq(ah, chan);
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}
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}
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static inline int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
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{
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if (!ath9k_hw_private_ops(ah)->rf_alloc_ext_banks)
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return 0;
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return ath9k_hw_private_ops(ah)->rf_alloc_ext_banks(ah);
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}
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static inline void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
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{
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if (!ath9k_hw_private_ops(ah)->rf_free_ext_banks)
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return;
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ath9k_hw_private_ops(ah)->rf_free_ext_banks(ah);
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}
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static inline bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
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static inline bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
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struct ath9k_channel *chan,
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struct ath9k_channel *chan,
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u16 modesIndex)
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u16 modesIndex)
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@ -554,14 +554,6 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
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ah->eep_ops->get_eeprom_ver(ah),
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ah->eep_ops->get_eeprom_ver(ah),
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ah->eep_ops->get_eeprom_rev(ah));
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ah->eep_ops->get_eeprom_rev(ah));
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ecode = ath9k_hw_rf_alloc_ext_banks(ah);
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if (ecode) {
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ath_err(ath9k_hw_common(ah),
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"Failed allocating banks for external radio\n");
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ath9k_hw_rf_free_ext_banks(ah);
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return ecode;
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}
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if (ah->config.enable_ani) {
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if (ah->config.enable_ani) {
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ath9k_hw_ani_setup(ah);
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ath9k_hw_ani_setup(ah);
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ath9k_hw_ani_init(ah);
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ath9k_hw_ani_init(ah);
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@ -570,12 +562,13 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
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return 0;
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return 0;
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}
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}
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static void ath9k_hw_attach_ops(struct ath_hw *ah)
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static int ath9k_hw_attach_ops(struct ath_hw *ah)
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{
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{
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if (AR_SREV_9300_20_OR_LATER(ah))
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if (!AR_SREV_9300_20_OR_LATER(ah))
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ar9003_hw_attach_ops(ah);
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return ar9002_hw_attach_ops(ah);
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else
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ar9002_hw_attach_ops(ah);
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ar9003_hw_attach_ops(ah);
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return 0;
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}
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}
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/* Called for all hardware families */
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/* Called for all hardware families */
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@ -611,7 +604,9 @@ static int __ath9k_hw_init(struct ath_hw *ah)
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ath9k_hw_init_defaults(ah);
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ath9k_hw_init_defaults(ah);
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ath9k_hw_init_config(ah);
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ath9k_hw_init_config(ah);
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ath9k_hw_attach_ops(ah);
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r = ath9k_hw_attach_ops(ah);
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if (r)
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return r;
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if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
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if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
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ath_err(common, "Couldn't wakeup chip\n");
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ath_err(common, "Couldn't wakeup chip\n");
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@ -1153,12 +1148,9 @@ void ath9k_hw_deinit(struct ath_hw *ah)
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath_common *common = ath9k_hw_common(ah);
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if (common->state < ATH_HW_INITIALIZED)
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if (common->state < ATH_HW_INITIALIZED)
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goto free_hw;
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return;
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ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
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ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
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free_hw:
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ath9k_hw_rf_free_ext_banks(ah);
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}
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}
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EXPORT_SYMBOL(ath9k_hw_deinit);
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EXPORT_SYMBOL(ath9k_hw_deinit);
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@ -604,8 +604,6 @@ struct ath_hw_radar_conf {
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*
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*
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* @rf_set_freq: change frequency
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* @rf_set_freq: change frequency
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* @spur_mitigate_freq: spur mitigation
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* @spur_mitigate_freq: spur mitigation
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* @rf_alloc_ext_banks:
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* @rf_free_ext_banks:
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* @set_rf_regs:
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* @set_rf_regs:
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* @compute_pll_control: compute the PLL control value to use for
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* @compute_pll_control: compute the PLL control value to use for
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* AR_RTC_PLL_CONTROL for a given channel
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* AR_RTC_PLL_CONTROL for a given channel
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@ -630,8 +628,6 @@ struct ath_hw_private_ops {
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struct ath9k_channel *chan);
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struct ath9k_channel *chan);
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void (*spur_mitigate_freq)(struct ath_hw *ah,
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void (*spur_mitigate_freq)(struct ath_hw *ah,
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struct ath9k_channel *chan);
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struct ath9k_channel *chan);
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int (*rf_alloc_ext_banks)(struct ath_hw *ah);
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void (*rf_free_ext_banks)(struct ath_hw *ah);
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bool (*set_rf_regs)(struct ath_hw *ah,
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bool (*set_rf_regs)(struct ath_hw *ah,
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struct ath9k_channel *chan,
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struct ath9k_channel *chan,
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u16 modesIndex);
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u16 modesIndex);
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@ -710,6 +706,7 @@ enum ath_cal_list {
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struct ath_hw {
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struct ath_hw {
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struct ath_ops reg_ops;
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struct ath_ops reg_ops;
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struct device *dev;
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struct ieee80211_hw *hw;
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struct ieee80211_hw *hw;
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struct ath_common common;
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struct ath_common common;
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struct ath9k_hw_version hw_version;
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struct ath9k_hw_version hw_version;
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@ -1068,14 +1065,14 @@ bool ar9003_paprd_is_done(struct ath_hw *ah);
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bool ar9003_is_paprd_enabled(struct ath_hw *ah);
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bool ar9003_is_paprd_enabled(struct ath_hw *ah);
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/* Hardware family op attach helpers */
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/* Hardware family op attach helpers */
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void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
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int ar5008_hw_attach_phy_ops(struct ath_hw *ah);
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void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
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void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
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void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
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void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
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void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
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void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
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void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
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void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
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void ar9002_hw_attach_ops(struct ath_hw *ah);
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int ar9002_hw_attach_ops(struct ath_hw *ah);
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void ar9003_hw_attach_ops(struct ath_hw *ah);
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void ar9003_hw_attach_ops(struct ath_hw *ah);
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void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
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void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
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@ -559,6 +559,7 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
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if (!ah)
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if (!ah)
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return -ENOMEM;
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return -ENOMEM;
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ah->dev = sc->dev;
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ah->hw = sc->hw;
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ah->hw = sc->hw;
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ah->hw_version.devid = devid;
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ah->hw_version.devid = devid;
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ah->reg_ops.read = ath9k_ioread32;
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ah->reg_ops.read = ath9k_ioread32;
|
||||||
|
|
Loading…
Reference in a new issue