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clk: tegra: override bits for Tegra30 PLLM

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Define override bits for Tegra30 PLLM.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Peter De Schrijver 2013-06-06 13:47:30 +03:00 committed by Mike Turquette
parent d53442e94d
commit c09e32bb67
1 changed files with 18 additions and 0 deletions
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18
drivers/clk/tegra/clk-tegra30.c
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@ -252,6 +252,9 @@
#define CLK_RESET_CCLK_RUN_POLICY 2 #define CLK_RESET_CCLK_RUN_POLICY 2
#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8 #define CLK_RESET_CCLK_BURST_POLICY_PLLX 8
/* PLLM override registers */
#define PMC_PLLM_WB0_OVERRIDE 0x1dc
#ifdef CONFIG_PM_SLEEP #ifdef CONFIG_PM_SLEEP
static struct cpu_clk_suspend_context { static struct cpu_clk_suspend_context {
u32 pllx_misc; u32 pllx_misc;
@ -563,6 +566,18 @@ static struct tegra_clk_pll_params pll_c_params = {
.lock_delay = 300, .lock_delay = 300,
}; };
static struct div_nmp pllm_nmp = {
.divn_shift = 8,
.divn_width = 10,
.override_divn_shift = 5,
.divm_shift = 0,
.divm_width = 5,
.override_divm_shift = 0,
.divp_shift = 20,
.divp_width = 3,
.override_divp_shift = 15,
};
static struct tegra_clk_pll_params pll_m_params = { static struct tegra_clk_pll_params pll_m_params = {
.input_min = 2000000, .input_min = 2000000,
.input_max = 31000000, .input_max = 31000000,
@ -575,6 +590,9 @@ static struct tegra_clk_pll_params pll_m_params = {
.lock_mask = PLL_BASE_LOCK, .lock_mask = PLL_BASE_LOCK,
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
.lock_delay = 300, .lock_delay = 300,
.div_nmp = &pllm_nmp,
.pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
.pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE,
}; };
static struct tegra_clk_pll_params pll_p_params = { static struct tegra_clk_pll_params pll_p_params = {