edac updates for v3.18-rc1
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commit
bf65dea87e
2 changed files with 22 additions and 33 deletions
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@ -52,36 +52,6 @@ static int probed;
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#define GET_BITFIELD(v, lo, hi) \
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(((v) & GENMASK_ULL(hi, lo)) >> (lo))
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/*
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* sbridge Memory Controller Registers
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*/
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/*
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* FIXME: For now, let's order by device function, as it makes
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* easier for driver's development process. This table should be
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* moved to pci_id.h when submitted upstream
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*/
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */
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/*
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* Currently, unused, but will be needed in the future
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* implementations, as they hold the error counters
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*/
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */
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/* Devices 12 Function 6, Offsets 0x80 to 0xcc */
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static const u32 sbridge_dram_rule[] = {
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0x80, 0x88, 0x90, 0x98, 0xa0,
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@ -283,8 +253,9 @@ static const u32 correrrthrsld[] = {
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* sbridge structs
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*/
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#define NUM_CHANNELS 4
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#define MAX_DIMMS 3 /* Max DIMMS per channel */
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#define NUM_CHANNELS 4
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#define MAX_DIMMS 3 /* Max DIMMS per channel */
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#define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */
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enum type {
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SANDY_BRIDGE,
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@ -529,7 +500,7 @@ static const struct pci_id_table pci_dev_descr_haswell_table[] = {
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* pci_device_id table for which devices we are looking for
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*/
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static const struct pci_device_id sbridge_pci_tbl[] = {
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)},
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{0,} /* 0 terminated list. */
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@ -1991,6 +1962,9 @@ static void sbridge_mce_output_error(struct mem_ctl_info *mci,
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/* FIXME: need support for channel mask */
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if (channel == CHANNEL_UNSPECIFIED)
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channel = -1;
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/* Call the helper to output message */
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edac_mc_handle_error(tp_event, mci, core_err_cnt,
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m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
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@ -2820,7 +2820,22 @@
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#define PCI_DEVICE_ID_INTEL_UNC_R2PCIE 0x3c43
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#define PCI_DEVICE_ID_INTEL_UNC_R3QPI0 0x3c44
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#define PCI_DEVICE_ID_INTEL_UNC_R3QPI1 0x3c45
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */
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#define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX 0x3ce0
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */
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#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */
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#define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f
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#define PCI_DEVICE_ID_INTEL_5100_16 0x65f0
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#define PCI_DEVICE_ID_INTEL_5100_19 0x65f3
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