ixgbe: cleanup unclear references to reg_idx
There are a number of places where we use the variable j to contain the register index of the ring. Instead of using such a non-descriptive variable name it is better that we name it reg_idx so that it is clear what the variable contains. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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9d6b758f42
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1 changed files with 62 additions and 62 deletions
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@ -647,8 +647,8 @@ static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
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#ifdef CONFIG_IXGBE_DCB
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if (adapter->dcb_cfg.pfc_mode_enable) {
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int tc;
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int reg_idx = tx_ring->reg_idx;
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int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
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u8 reg_idx = tx_ring->reg_idx;
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switch (adapter->hw.mac.type) {
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case ixgbe_mac_82598EB:
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@ -1422,7 +1422,7 @@ static int ixgbe_clean_rxonly(struct napi_struct *, int);
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static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
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{
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struct ixgbe_q_vector *q_vector;
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int i, j, q_vectors, v_idx, r_idx;
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int i, q_vectors, v_idx, r_idx;
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u32 mask;
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q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
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@ -1438,8 +1438,8 @@ static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
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adapter->num_rx_queues);
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for (i = 0; i < q_vector->rxr_count; i++) {
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j = adapter->rx_ring[r_idx]->reg_idx;
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ixgbe_set_ivar(adapter, 0, j, v_idx);
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u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
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ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
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r_idx = find_next_bit(q_vector->rxr_idx,
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adapter->num_rx_queues,
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r_idx + 1);
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@ -1448,8 +1448,8 @@ static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
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adapter->num_tx_queues);
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for (i = 0; i < q_vector->txr_count; i++) {
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j = adapter->tx_ring[r_idx]->reg_idx;
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ixgbe_set_ivar(adapter, 1, j, v_idx);
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u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
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ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
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r_idx = find_next_bit(q_vector->txr_idx,
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adapter->num_tx_queues,
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r_idx + 1);
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@ -2555,7 +2555,7 @@ void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
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u64 tdba = ring->dma;
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int wait_loop = 10;
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u32 txdctl;
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u16 reg_idx = ring->reg_idx;
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u8 reg_idx = ring->reg_idx;
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/* disable queue to avoid issues while updating state */
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txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
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@ -2684,13 +2684,13 @@ static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
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struct ixgbe_ring *rx_ring)
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{
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u32 srrctl;
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int index = rx_ring->reg_idx;
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u8 reg_idx = rx_ring->reg_idx;
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switch (adapter->hw.mac.type) {
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case ixgbe_mac_82598EB: {
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struct ixgbe_ring_feature *feature = adapter->ring_feature;
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const int mask = feature[RING_F_RSS].mask;
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index = index & mask;
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reg_idx = reg_idx & mask;
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}
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break;
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case ixgbe_mac_82599EB:
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@ -2698,7 +2698,7 @@ static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
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break;
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}
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srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
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srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
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srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
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srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
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@ -2721,7 +2721,7 @@ static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
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srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
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}
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
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}
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static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
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@ -2801,7 +2801,7 @@ static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
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struct ixgbe_hw *hw = &adapter->hw;
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u32 rscctrl;
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int rx_buf_len;
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u16 reg_idx = ring->reg_idx;
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u8 reg_idx = ring->reg_idx;
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if (!ring_is_rsc_enabled(ring))
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return;
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@ -2867,9 +2867,9 @@ static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
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struct ixgbe_ring *ring)
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{
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struct ixgbe_hw *hw = &adapter->hw;
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int reg_idx = ring->reg_idx;
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int wait_loop = IXGBE_MAX_RX_DESC_POLL;
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u32 rxdctl;
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u8 reg_idx = ring->reg_idx;
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/* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
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if (hw->mac.type == ixgbe_mac_82598EB &&
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@ -2893,7 +2893,7 @@ void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
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struct ixgbe_hw *hw = &adapter->hw;
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u64 rdba = ring->dma;
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u32 rxdctl;
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u16 reg_idx = ring->reg_idx;
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u8 reg_idx = ring->reg_idx;
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/* disable queue to avoid issues while updating state */
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rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
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@ -3894,7 +3894,7 @@ void ixgbe_down(struct ixgbe_adapter *adapter)
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struct ixgbe_hw *hw = &adapter->hw;
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u32 rxctrl;
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u32 txdctl;
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int i, j;
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int i;
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int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
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/* signal that we are down to the interrupt handler */
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@ -3952,9 +3952,9 @@ void ixgbe_down(struct ixgbe_adapter *adapter)
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/* disable transmits in the hardware now that interrupts are off */
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for (i = 0; i < adapter->num_tx_queues; i++) {
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j = adapter->tx_ring[i]->reg_idx;
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txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
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IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
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u8 reg_idx = adapter->tx_ring[i]->reg_idx;
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txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
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IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
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(txdctl & ~IXGBE_TXDCTL_ENABLE));
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}
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/* Disable the Tx DMA engine on 82599 */
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@ -4420,55 +4420,55 @@ static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
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*/
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static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
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{
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int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
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bool ret = false;
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struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
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int i;
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u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
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if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
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return false;
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if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
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#ifdef CONFIG_IXGBE_DCB
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if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
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struct ixgbe_fcoe *fcoe = &adapter->fcoe;
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if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
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struct ixgbe_fcoe *fcoe = &adapter->fcoe;
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ixgbe_cache_ring_dcb(adapter);
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/* find out queues in TC for FCoE */
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fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
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fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
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/*
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* In 82599, the number of Tx queues for each traffic
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* class for both 8-TC and 4-TC modes are:
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* TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
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* 8 TCs: 32 32 16 16 8 8 8 8
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* 4 TCs: 64 64 32 32
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* We have max 8 queues for FCoE, where 8 the is
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* FCoE redirection table size. If TC for FCoE is
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* less than or equal to TC3, we have enough queues
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* to add max of 8 queues for FCoE, so we start FCoE
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* tx descriptor from the next one, i.e., reg_idx + 1.
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* If TC for FCoE is above TC3, implying 8 TC mode,
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* and we need 8 for FCoE, we have to take all queues
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* in that traffic class for FCoE.
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*/
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if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
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fcoe_tx_i--;
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}
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#endif /* CONFIG_IXGBE_DCB */
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if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
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if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
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(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
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ixgbe_cache_ring_fdir(adapter);
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else
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ixgbe_cache_ring_rss(adapter);
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fcoe_rx_i = f->mask;
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fcoe_tx_i = f->mask;
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}
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for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
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adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
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adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
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}
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ret = true;
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ixgbe_cache_ring_dcb(adapter);
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/* find out queues in TC for FCoE */
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fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
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fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
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/*
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* In 82599, the number of Tx queues for each traffic
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* class for both 8-TC and 4-TC modes are:
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* TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
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* 8 TCs: 32 32 16 16 8 8 8 8
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* 4 TCs: 64 64 32 32
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* We have max 8 queues for FCoE, where 8 the is
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* FCoE redirection table size. If TC for FCoE is
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* less than or equal to TC3, we have enough queues
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* to add max of 8 queues for FCoE, so we start FCoE
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* Tx queue from the next one, i.e., reg_idx + 1.
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* If TC for FCoE is above TC3, implying 8 TC mode,
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* and we need 8 for FCoE, we have to take all queues
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* in that traffic class for FCoE.
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*/
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if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
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fcoe_tx_i--;
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}
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return ret;
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#endif /* CONFIG_IXGBE_DCB */
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if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
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if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
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(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
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ixgbe_cache_ring_fdir(adapter);
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else
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ixgbe_cache_ring_rss(adapter);
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fcoe_rx_i = f->mask;
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fcoe_tx_i = f->mask;
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}
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for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
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adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
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adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
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}
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return true;
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}
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#endif /* IXGBE_FCOE */
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