Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: powerpc/perf_event: Fix oops due to perf_event_do_pending call powerpc/swiotlb: Fix off by one in determining boundary of which ops to use
This commit is contained in:
commit
be835674b5
6 changed files with 51 additions and 68 deletions
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@ -130,43 +130,5 @@ static inline int irqs_disabled_flags(unsigned long flags)
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*/
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struct irq_chip;
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#ifdef CONFIG_PERF_EVENTS
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#ifdef CONFIG_PPC64
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static inline unsigned long test_perf_event_pending(void)
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{
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unsigned long x;
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asm volatile("lbz %0,%1(13)"
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: "=r" (x)
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: "i" (offsetof(struct paca_struct, perf_event_pending)));
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return x;
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}
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static inline void set_perf_event_pending(void)
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{
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asm volatile("stb %0,%1(13)" : :
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"r" (1),
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"i" (offsetof(struct paca_struct, perf_event_pending)));
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}
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static inline void clear_perf_event_pending(void)
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{
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asm volatile("stb %0,%1(13)" : :
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"r" (0),
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"i" (offsetof(struct paca_struct, perf_event_pending)));
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}
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#endif /* CONFIG_PPC64 */
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#else /* CONFIG_PERF_EVENTS */
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static inline unsigned long test_perf_event_pending(void)
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{
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return 0;
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}
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static inline void clear_perf_event_pending(void) {}
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#endif /* CONFIG_PERF_EVENTS */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_HW_IRQ_H */
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@ -133,7 +133,6 @@ int main(void)
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DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr));
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DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled));
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DEFINE(PACAHARDIRQEN, offsetof(struct paca_struct, hard_enabled));
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DEFINE(PACAPERFPEND, offsetof(struct paca_struct, perf_event_pending));
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DEFINE(PACACONTEXTID, offsetof(struct paca_struct, context.id));
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#ifdef CONFIG_PPC_MM_SLICES
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DEFINE(PACALOWSLICESPSIZE, offsetof(struct paca_struct,
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@ -1,7 +1,8 @@
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/*
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* Contains routines needed to support swiotlb for ppc.
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*
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* Copyright (C) 2009 Becky Bruce, Freescale Semiconductor
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* Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
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* Author: Becky Bruce
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -70,7 +71,7 @@ static int ppc_swiotlb_bus_notify(struct notifier_block *nb,
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sd->max_direct_dma_addr = 0;
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/* May need to bounce if the device can't address all of DRAM */
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if (dma_get_mask(dev) < lmb_end_of_DRAM())
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if ((dma_get_mask(dev) + 1) < lmb_end_of_DRAM())
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set_dma_ops(dev, &swiotlb_dma_ops);
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return NOTIFY_DONE;
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@ -556,15 +556,6 @@ ALT_FW_FTR_SECTION_END_IFCLR(FW_FEATURE_ISERIES)
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2:
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TRACE_AND_RESTORE_IRQ(r5);
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#ifdef CONFIG_PERF_EVENTS
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/* check paca->perf_event_pending if we're enabling ints */
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lbz r3,PACAPERFPEND(r13)
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and. r3,r3,r5
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beq 27f
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bl .perf_event_do_pending
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27:
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#endif /* CONFIG_PERF_EVENTS */
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/* extract EE bit and use it to restore paca->hard_enabled */
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ld r3,_MSR(r1)
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rldicl r4,r3,49,63 /* r0 = (r3 >> 15) & 1 */
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@ -53,7 +53,6 @@
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#include <linux/bootmem.h>
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#include <linux/pci.h>
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#include <linux/debugfs.h>
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#include <linux/perf_event.h>
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#include <asm/uaccess.h>
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#include <asm/system.h>
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@ -145,11 +144,6 @@ notrace void raw_local_irq_restore(unsigned long en)
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}
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#endif /* CONFIG_PPC_STD_MMU_64 */
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if (test_perf_event_pending()) {
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clear_perf_event_pending();
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perf_event_do_pending();
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}
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/*
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* if (get_paca()->hard_enabled) return;
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* But again we need to take care that gcc gets hard_enabled directly
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@ -532,25 +532,60 @@ void __init iSeries_time_init_early(void)
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}
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#endif /* CONFIG_PPC_ISERIES */
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#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_PPC32)
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DEFINE_PER_CPU(u8, perf_event_pending);
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#ifdef CONFIG_PERF_EVENTS
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void set_perf_event_pending(void)
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/*
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* 64-bit uses a byte in the PACA, 32-bit uses a per-cpu variable...
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*/
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#ifdef CONFIG_PPC64
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static inline unsigned long test_perf_event_pending(void)
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{
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get_cpu_var(perf_event_pending) = 1;
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set_dec(1);
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put_cpu_var(perf_event_pending);
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unsigned long x;
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asm volatile("lbz %0,%1(13)"
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: "=r" (x)
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: "i" (offsetof(struct paca_struct, perf_event_pending)));
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return x;
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}
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static inline void set_perf_event_pending_flag(void)
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{
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asm volatile("stb %0,%1(13)" : :
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"r" (1),
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"i" (offsetof(struct paca_struct, perf_event_pending)));
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}
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static inline void clear_perf_event_pending(void)
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{
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asm volatile("stb %0,%1(13)" : :
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"r" (0),
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"i" (offsetof(struct paca_struct, perf_event_pending)));
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}
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#else /* 32-bit */
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DEFINE_PER_CPU(u8, perf_event_pending);
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#define set_perf_event_pending_flag() __get_cpu_var(perf_event_pending) = 1
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#define test_perf_event_pending() __get_cpu_var(perf_event_pending)
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#define clear_perf_event_pending() __get_cpu_var(perf_event_pending) = 0
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#else /* CONFIG_PERF_EVENTS && CONFIG_PPC32 */
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#endif /* 32 vs 64 bit */
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void set_perf_event_pending(void)
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{
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preempt_disable();
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set_perf_event_pending_flag();
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set_dec(1);
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preempt_enable();
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}
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#else /* CONFIG_PERF_EVENTS */
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#define test_perf_event_pending() 0
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#define clear_perf_event_pending()
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#endif /* CONFIG_PERF_EVENTS && CONFIG_PPC32 */
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#endif /* CONFIG_PERF_EVENTS */
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/*
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* For iSeries shared processors, we have to let the hypervisor
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@ -582,10 +617,6 @@ void timer_interrupt(struct pt_regs * regs)
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set_dec(DECREMENTER_MAX);
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#ifdef CONFIG_PPC32
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if (test_perf_event_pending()) {
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clear_perf_event_pending();
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perf_event_do_pending();
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}
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if (atomic_read(&ppc_n_lost_interrupts) != 0)
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do_IRQ(regs);
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#endif
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@ -604,6 +635,11 @@ void timer_interrupt(struct pt_regs * regs)
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calculate_steal_time();
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if (test_perf_event_pending()) {
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clear_perf_event_pending();
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perf_event_do_pending();
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}
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#ifdef CONFIG_PPC_ISERIES
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if (firmware_has_feature(FW_FEATURE_ISERIES))
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get_lppaca()->int_dword.fields.decr_int = 0;
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