x86: merge msr_32/64.h
Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Thomas Gleixner
parent
297a99e1a3
commit
be7baf80a6
4 changed files with 347 additions and 360 deletions
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@ -14,8 +14,6 @@ header-y += vsyscall32.h
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unifdef-y += e820.h
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unifdef-y += ist.h
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unifdef-y += mce.h
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unifdef-y += msr_32.h
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unifdef-y += msr_64.h
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unifdef-y += msr.h
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unifdef-y += mtrr.h
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unifdef-y += page_32.h
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@ -1,13 +1,350 @@
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#ifndef __ASM_X86_MSR_H_
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#define __ASM_X86_MSR_H_
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#include <asm/msr-index.h>
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#ifdef __i386__
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#ifdef __KERNEL__
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# ifdef CONFIG_X86_32
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# include "msr_32.h"
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# else
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# include "msr_64.h"
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# endif
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#ifndef __ASSEMBLY__
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#include <asm/errno.h>
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static inline unsigned long long native_read_msr(unsigned int msr)
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{
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unsigned long long val;
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asm volatile("rdmsr" : "=A" (val) : "c" (msr));
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return val;
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}
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static inline unsigned long long native_read_msr_safe(unsigned int msr,
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int *err)
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{
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unsigned long long val;
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asm volatile("2: rdmsr ; xorl %0,%0\n"
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"1:\n\t"
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".section .fixup,\"ax\"\n\t"
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"3: movl %3,%0 ; jmp 1b\n\t"
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".previous\n\t"
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".section __ex_table,\"a\"\n"
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" .align 4\n\t"
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" .long 2b,3b\n\t"
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".previous"
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: "=r" (*err), "=A" (val)
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: "c" (msr), "i" (-EFAULT));
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return val;
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}
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static inline void native_write_msr(unsigned int msr, unsigned long long val)
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{
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asm volatile("wrmsr" : : "c" (msr), "A"(val));
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}
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static inline int native_write_msr_safe(unsigned int msr,
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unsigned long long val)
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{
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int err;
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asm volatile("2: wrmsr ; xorl %0,%0\n"
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"1:\n\t"
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".section .fixup,\"ax\"\n\t"
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"3: movl %4,%0 ; jmp 1b\n\t"
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".previous\n\t"
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".section __ex_table,\"a\"\n"
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" .align 4\n\t"
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" .long 2b,3b\n\t"
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".previous"
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: "=a" (err)
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: "c" (msr), "0" ((u32)val), "d" ((u32)(val>>32)),
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"i" (-EFAULT));
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return err;
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}
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static inline unsigned long long native_read_tsc(void)
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{
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unsigned long long val;
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asm volatile("rdtsc" : "=A" (val));
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return val;
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}
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static inline unsigned long long native_read_pmc(void)
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{
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unsigned long long val;
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asm volatile("rdpmc" : "=A" (val));
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return val;
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}
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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# ifdef __i386__
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# include "msr_32.h"
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# else
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# include "msr_64.h"
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# endif
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#include <linux/errno.h>
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/*
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* Access to machine-specific registers (available on 586 and better only)
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* Note: the rd* operations modify the parameters directly (without using
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* pointer indirection), this allows gcc to optimize better
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*/
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#define rdmsr(msr,val1,val2) \
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do { \
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u64 __val = native_read_msr(msr); \
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(val1) = (u32)__val; \
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(val2) = (u32)(__val >> 32); \
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} while(0)
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static inline void wrmsr(u32 __msr, u32 __low, u32 __high)
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{
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native_write_msr(__msr, ((u64)__high << 32) | __low);
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}
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#define rdmsrl(msr,val) \
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((val) = native_read_msr(msr))
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#define wrmsrl(msr,val) native_write_msr(msr, val)
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/* wrmsr with exception handling */
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static inline int wrmsr_safe(u32 __msr, u32 __low, u32 __high)
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{
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return native_write_msr_safe(__msr, ((u64)__high << 32) | __low);
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}
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/* rdmsr with exception handling */
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#define rdmsr_safe(msr,p1,p2) \
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({ \
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int __err; \
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u64 __val = native_read_msr_safe(msr, &__err); \
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(*p1) = (u32)__val; \
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(*p2) = (u32)(__val >> 32); \
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__err; \
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})
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#define rdtscl(low) \
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((low) = (u32)native_read_tsc())
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#define rdtscll(val) \
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((val) = native_read_tsc())
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#define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
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#define rdpmc(counter,low,high) \
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do { \
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u64 _l = native_read_pmc(); \
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(low) = (u32)_l; \
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(high) = (u32)(_l >> 32); \
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} while(0)
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#endif /* !CONFIG_PARAVIRT */
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#ifdef CONFIG_SMP
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void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
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void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
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int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
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int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
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#else /* CONFIG_SMP */
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static inline void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
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{
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rdmsr(msr_no, *l, *h);
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}
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static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
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{
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wrmsr(msr_no, l, h);
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}
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static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
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{
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return rdmsr_safe(msr_no, l, h);
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}
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static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
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{
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return wrmsr_safe(msr_no, l, h);
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}
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#endif /* CONFIG_SMP */
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#endif /* ! __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#else /* __i386__ */
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#ifndef __ASSEMBLY__
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#include <linux/errno.h>
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/*
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* Access to machine-specific registers (available on 586 and better only)
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* Note: the rd* operations modify the parameters directly (without using
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* pointer indirection), this allows gcc to optimize better
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*/
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#define rdmsr(msr,val1,val2) \
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__asm__ __volatile__("rdmsr" \
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: "=a" (val1), "=d" (val2) \
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: "c" (msr))
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#define rdmsrl(msr,val) do { unsigned long a__,b__; \
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__asm__ __volatile__("rdmsr" \
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: "=a" (a__), "=d" (b__) \
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: "c" (msr)); \
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val = a__ | (b__<<32); \
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} while(0)
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#define wrmsr(msr,val1,val2) \
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__asm__ __volatile__("wrmsr" \
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: /* no outputs */ \
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: "c" (msr), "a" (val1), "d" (val2))
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#define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
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/* wrmsr with exception handling */
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#define wrmsr_safe(msr,a,b) ({ int ret__; \
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asm volatile("2: wrmsr ; xorl %0,%0\n" \
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"1:\n\t" \
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".section .fixup,\"ax\"\n\t" \
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"3: movl %4,%0 ; jmp 1b\n\t" \
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".previous\n\t" \
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".section __ex_table,\"a\"\n" \
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" .align 8\n\t" \
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" .quad 2b,3b\n\t" \
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".previous" \
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: "=a" (ret__) \
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: "c" (msr), "0" (a), "d" (b), "i" (-EFAULT)); \
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ret__; })
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#define checking_wrmsrl(msr,val) wrmsr_safe(msr,(u32)(val),(u32)((val)>>32))
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#define rdmsr_safe(msr,a,b) \
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({ int ret__; \
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asm volatile ("1: rdmsr\n" \
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"2:\n" \
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".section .fixup,\"ax\"\n" \
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"3: movl %4,%0\n" \
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" jmp 2b\n" \
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".previous\n" \
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".section __ex_table,\"a\"\n" \
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" .align 8\n" \
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" .quad 1b,3b\n" \
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".previous":"=&bDS" (ret__), "=a"(*(a)), "=d"(*(b)) \
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:"c"(msr), "i"(-EIO), "0"(0)); \
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ret__; })
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#define rdtsc(low,high) \
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__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
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#define rdtscl(low) \
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__asm__ __volatile__ ("rdtsc" : "=a" (low) : : "edx")
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#define rdtscp(low,high,aux) \
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asm volatile (".byte 0x0f,0x01,0xf9" : "=a" (low), "=d" (high), "=c" (aux))
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#define rdtscll(val) do { \
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unsigned int __a,__d; \
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asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \
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(val) = ((unsigned long)__a) | (((unsigned long)__d)<<32); \
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} while(0)
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#define rdtscpll(val, aux) do { \
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unsigned long __a, __d; \
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asm volatile (".byte 0x0f,0x01,0xf9" : "=a" (__a), "=d" (__d), "=c" (aux)); \
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(val) = (__d << 32) | __a; \
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} while (0)
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#define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
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#define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0)
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#define rdpmc(counter,low,high) \
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__asm__ __volatile__("rdpmc" \
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: "=a" (low), "=d" (high) \
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: "c" (counter))
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static inline void cpuid(int op, unsigned int *eax, unsigned int *ebx,
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unsigned int *ecx, unsigned int *edx)
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{
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__asm__("cpuid"
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: "=a" (*eax),
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"=b" (*ebx),
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"=c" (*ecx),
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"=d" (*edx)
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: "0" (op));
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}
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/* Some CPUID calls want 'count' to be placed in ecx */
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static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
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int *edx)
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{
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__asm__("cpuid"
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: "=a" (*eax),
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"=b" (*ebx),
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"=c" (*ecx),
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"=d" (*edx)
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: "0" (op), "c" (count));
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}
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/*
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* CPUID functions returning a single datum
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*/
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static inline unsigned int cpuid_eax(unsigned int op)
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{
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unsigned int eax;
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__asm__("cpuid"
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: "=a" (eax)
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: "0" (op)
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: "bx", "cx", "dx");
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return eax;
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}
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static inline unsigned int cpuid_ebx(unsigned int op)
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{
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unsigned int eax, ebx;
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__asm__("cpuid"
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: "=a" (eax), "=b" (ebx)
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: "0" (op)
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: "cx", "dx" );
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return ebx;
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}
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static inline unsigned int cpuid_ecx(unsigned int op)
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{
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unsigned int eax, ecx;
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__asm__("cpuid"
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: "=a" (eax), "=c" (ecx)
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: "0" (op)
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: "bx", "dx" );
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return ecx;
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}
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static inline unsigned int cpuid_edx(unsigned int op)
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{
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unsigned int eax, edx;
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__asm__("cpuid"
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: "=a" (eax), "=d" (edx)
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: "0" (op)
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: "bx", "cx");
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return edx;
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}
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#ifdef CONFIG_SMP
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void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
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void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
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int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
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int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
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#else /* CONFIG_SMP */
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static inline void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
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{
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rdmsr(msr_no, *l, *h);
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}
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static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
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{
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wrmsr(msr_no, l, h);
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}
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static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
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{
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return rdmsr_safe(msr_no, l, h);
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}
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static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
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{
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return wrmsr_safe(msr_no, l, h);
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}
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#endif /* CONFIG_SMP */
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#endif /* __ASSEMBLY__ */
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#endif /* !__i386__ */
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#endif
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@ -1,161 +0,0 @@
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#ifndef __ASM_MSR_H
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#define __ASM_MSR_H
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#include <asm/msr-index.h>
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#include <asm/errno.h>
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static inline unsigned long long native_read_msr(unsigned int msr)
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{
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unsigned long long val;
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asm volatile("rdmsr" : "=A" (val) : "c" (msr));
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return val;
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}
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static inline unsigned long long native_read_msr_safe(unsigned int msr,
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int *err)
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{
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unsigned long long val;
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asm volatile("2: rdmsr ; xorl %0,%0\n"
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"1:\n\t"
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".section .fixup,\"ax\"\n\t"
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"3: movl %3,%0 ; jmp 1b\n\t"
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".previous\n\t"
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".section __ex_table,\"a\"\n"
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" .align 4\n\t"
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" .long 2b,3b\n\t"
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".previous"
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: "=r" (*err), "=A" (val)
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: "c" (msr), "i" (-EFAULT));
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return val;
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}
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static inline void native_write_msr(unsigned int msr, unsigned long long val)
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{
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asm volatile("wrmsr" : : "c" (msr), "A"(val));
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}
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static inline int native_write_msr_safe(unsigned int msr,
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unsigned long long val)
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{
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int err;
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asm volatile("2: wrmsr ; xorl %0,%0\n"
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"1:\n\t"
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".section .fixup,\"ax\"\n\t"
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"3: movl %4,%0 ; jmp 1b\n\t"
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".previous\n\t"
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".section __ex_table,\"a\"\n"
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" .align 4\n\t"
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" .long 2b,3b\n\t"
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".previous"
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: "=a" (err)
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: "c" (msr), "0" ((u32)val), "d" ((u32)(val>>32)),
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"i" (-EFAULT));
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return err;
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}
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static inline unsigned long long native_read_tsc(void)
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{
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unsigned long long val;
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asm volatile("rdtsc" : "=A" (val));
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return val;
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}
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static inline unsigned long long native_read_pmc(void)
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{
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unsigned long long val;
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asm volatile("rdpmc" : "=A" (val));
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return val;
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}
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#include <linux/errno.h>
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/*
|
||||
* Access to machine-specific registers (available on 586 and better only)
|
||||
* Note: the rd* operations modify the parameters directly (without using
|
||||
* pointer indirection), this allows gcc to optimize better
|
||||
*/
|
||||
|
||||
#define rdmsr(msr,val1,val2) \
|
||||
do { \
|
||||
u64 __val = native_read_msr(msr); \
|
||||
(val1) = (u32)__val; \
|
||||
(val2) = (u32)(__val >> 32); \
|
||||
} while(0)
|
||||
|
||||
static inline void wrmsr(u32 __msr, u32 __low, u32 __high)
|
||||
{
|
||||
native_write_msr(__msr, ((u64)__high << 32) | __low);
|
||||
}
|
||||
|
||||
#define rdmsrl(msr,val) \
|
||||
((val) = native_read_msr(msr))
|
||||
|
||||
#define wrmsrl(msr,val) native_write_msr(msr, val)
|
||||
|
||||
/* wrmsr with exception handling */
|
||||
static inline int wrmsr_safe(u32 __msr, u32 __low, u32 __high)
|
||||
{
|
||||
return native_write_msr_safe(__msr, ((u64)__high << 32) | __low);
|
||||
}
|
||||
|
||||
/* rdmsr with exception handling */
|
||||
#define rdmsr_safe(msr,p1,p2) \
|
||||
({ \
|
||||
int __err; \
|
||||
u64 __val = native_read_msr_safe(msr, &__err); \
|
||||
(*p1) = (u32)__val; \
|
||||
(*p2) = (u32)(__val >> 32); \
|
||||
__err; \
|
||||
})
|
||||
|
||||
#define rdtscl(low) \
|
||||
((low) = (u32)native_read_tsc())
|
||||
|
||||
#define rdtscll(val) \
|
||||
((val) = native_read_tsc())
|
||||
|
||||
#define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
|
||||
|
||||
#define rdpmc(counter,low,high) \
|
||||
do { \
|
||||
u64 _l = native_read_pmc(); \
|
||||
(low) = (u32)_l; \
|
||||
(high) = (u32)(_l >> 32); \
|
||||
} while(0)
|
||||
#endif /* !CONFIG_PARAVIRT */
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
|
||||
void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
|
||||
int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
|
||||
int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
|
||||
#else /* CONFIG_SMP */
|
||||
static inline void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
|
||||
{
|
||||
rdmsr(msr_no, *l, *h);
|
||||
}
|
||||
static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
|
||||
{
|
||||
wrmsr(msr_no, l, h);
|
||||
}
|
||||
static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
|
||||
{
|
||||
return rdmsr_safe(msr_no, l, h);
|
||||
}
|
||||
static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
|
||||
{
|
||||
return wrmsr_safe(msr_no, l, h);
|
||||
}
|
||||
#endif /* CONFIG_SMP */
|
||||
#endif
|
||||
#endif
|
||||
#endif /* __ASM_MSR_H */
|
||||
|
|
@ -1,187 +0,0 @@
|
|||
#ifndef X86_64_MSR_H
|
||||
#define X86_64_MSR_H 1
|
||||
|
||||
#include <asm/msr-index.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/errno.h>
|
||||
/*
|
||||
* Access to machine-specific registers (available on 586 and better only)
|
||||
* Note: the rd* operations modify the parameters directly (without using
|
||||
* pointer indirection), this allows gcc to optimize better
|
||||
*/
|
||||
|
||||
#define rdmsr(msr,val1,val2) \
|
||||
__asm__ __volatile__("rdmsr" \
|
||||
: "=a" (val1), "=d" (val2) \
|
||||
: "c" (msr))
|
||||
|
||||
|
||||
#define rdmsrl(msr,val) do { unsigned long a__,b__; \
|
||||
__asm__ __volatile__("rdmsr" \
|
||||
: "=a" (a__), "=d" (b__) \
|
||||
: "c" (msr)); \
|
||||
val = a__ | (b__<<32); \
|
||||
} while(0)
|
||||
|
||||
#define wrmsr(msr,val1,val2) \
|
||||
__asm__ __volatile__("wrmsr" \
|
||||
: /* no outputs */ \
|
||||
: "c" (msr), "a" (val1), "d" (val2))
|
||||
|
||||
#define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
|
||||
|
||||
/* wrmsr with exception handling */
|
||||
#define wrmsr_safe(msr,a,b) ({ int ret__; \
|
||||
asm volatile("2: wrmsr ; xorl %0,%0\n" \
|
||||
"1:\n\t" \
|
||||
".section .fixup,\"ax\"\n\t" \
|
||||
"3: movl %4,%0 ; jmp 1b\n\t" \
|
||||
".previous\n\t" \
|
||||
".section __ex_table,\"a\"\n" \
|
||||
" .align 8\n\t" \
|
||||
" .quad 2b,3b\n\t" \
|
||||
".previous" \
|
||||
: "=a" (ret__) \
|
||||
: "c" (msr), "0" (a), "d" (b), "i" (-EFAULT)); \
|
||||
ret__; })
|
||||
|
||||
#define checking_wrmsrl(msr,val) wrmsr_safe(msr,(u32)(val),(u32)((val)>>32))
|
||||
|
||||
#define rdmsr_safe(msr,a,b) \
|
||||
({ int ret__; \
|
||||
asm volatile ("1: rdmsr\n" \
|
||||
"2:\n" \
|
||||
".section .fixup,\"ax\"\n" \
|
||||
"3: movl %4,%0\n" \
|
||||
" jmp 2b\n" \
|
||||
".previous\n" \
|
||||
".section __ex_table,\"a\"\n" \
|
||||
" .align 8\n" \
|
||||
" .quad 1b,3b\n" \
|
||||
".previous":"=&bDS" (ret__), "=a"(*(a)), "=d"(*(b))\
|
||||
:"c"(msr), "i"(-EIO), "0"(0)); \
|
||||
ret__; })
|
||||
|
||||
#define rdtsc(low,high) \
|
||||
__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
|
||||
|
||||
#define rdtscl(low) \
|
||||
__asm__ __volatile__ ("rdtsc" : "=a" (low) : : "edx")
|
||||
|
||||
#define rdtscp(low,high,aux) \
|
||||
asm volatile (".byte 0x0f,0x01,0xf9" : "=a" (low), "=d" (high), "=c" (aux))
|
||||
|
||||
#define rdtscll(val) do { \
|
||||
unsigned int __a,__d; \
|
||||
asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \
|
||||
(val) = ((unsigned long)__a) | (((unsigned long)__d)<<32); \
|
||||
} while(0)
|
||||
|
||||
#define rdtscpll(val, aux) do { \
|
||||
unsigned long __a, __d; \
|
||||
asm volatile (".byte 0x0f,0x01,0xf9" : "=a" (__a), "=d" (__d), "=c" (aux)); \
|
||||
(val) = (__d << 32) | __a; \
|
||||
} while (0)
|
||||
|
||||
#define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
|
||||
|
||||
#define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0)
|
||||
|
||||
#define rdpmc(counter,low,high) \
|
||||
__asm__ __volatile__("rdpmc" \
|
||||
: "=a" (low), "=d" (high) \
|
||||
: "c" (counter))
|
||||
|
||||
static inline void cpuid(int op, unsigned int *eax, unsigned int *ebx,
|
||||
unsigned int *ecx, unsigned int *edx)
|
||||
{
|
||||
__asm__("cpuid"
|
||||
: "=a" (*eax),
|
||||
"=b" (*ebx),
|
||||
"=c" (*ecx),
|
||||
"=d" (*edx)
|
||||
: "0" (op));
|
||||
}
|
||||
|
||||
/* Some CPUID calls want 'count' to be placed in ecx */
|
||||
static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
|
||||
int *edx)
|
||||
{
|
||||
__asm__("cpuid"
|
||||
: "=a" (*eax),
|
||||
"=b" (*ebx),
|
||||
"=c" (*ecx),
|
||||
"=d" (*edx)
|
||||
: "0" (op), "c" (count));
|
||||
}
|
||||
|
||||
/*
|
||||
* CPUID functions returning a single datum
|
||||
*/
|
||||
static inline unsigned int cpuid_eax(unsigned int op)
|
||||
{
|
||||
unsigned int eax;
|
||||
|
||||
__asm__("cpuid"
|
||||
: "=a" (eax)
|
||||
: "0" (op)
|
||||
: "bx", "cx", "dx");
|
||||
return eax;
|
||||
}
|
||||
static inline unsigned int cpuid_ebx(unsigned int op)
|
||||
{
|
||||
unsigned int eax, ebx;
|
||||
|
||||
__asm__("cpuid"
|
||||
: "=a" (eax), "=b" (ebx)
|
||||
: "0" (op)
|
||||
: "cx", "dx" );
|
||||
return ebx;
|
||||
}
|
||||
static inline unsigned int cpuid_ecx(unsigned int op)
|
||||
{
|
||||
unsigned int eax, ecx;
|
||||
|
||||
__asm__("cpuid"
|
||||
: "=a" (eax), "=c" (ecx)
|
||||
: "0" (op)
|
||||
: "bx", "dx" );
|
||||
return ecx;
|
||||
}
|
||||
static inline unsigned int cpuid_edx(unsigned int op)
|
||||
{
|
||||
unsigned int eax, edx;
|
||||
|
||||
__asm__("cpuid"
|
||||
: "=a" (eax), "=d" (edx)
|
||||
: "0" (op)
|
||||
: "bx", "cx");
|
||||
return edx;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
|
||||
void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
|
||||
int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
|
||||
int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
|
||||
#else /* CONFIG_SMP */
|
||||
static inline void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
|
||||
{
|
||||
rdmsr(msr_no, *l, *h);
|
||||
}
|
||||
static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
|
||||
{
|
||||
wrmsr(msr_no, l, h);
|
||||
}
|
||||
static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
|
||||
{
|
||||
return rdmsr_safe(msr_no, l, h);
|
||||
}
|
||||
static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
|
||||
{
|
||||
return wrmsr_safe(msr_no, l, h);
|
||||
}
|
||||
#endif /* CONFIG_SMP */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* X86_64_MSR_H */
|
||||
Loading…
Reference in a new issue