[PARISC] Beautify parisc vmlinux.lds.S
Introduce a consistent layout of vmlinux. The same layout has been introduced for most architectures. And the same time move a few label definitions inside the curly brackets so they are assigned the correct starting address. Before a ld inserted alignment would have casued the label to pint before the actual start of the section. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Kyle McMartin <kyle@mcmartin.ca>
This commit is contained in:
Sam Ravnborg
Kyle McMartin
parent
e9a03990d9
commit
be1b3d8cb1
1 changed files with 192 additions and 141 deletions
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@ -46,168 +46,219 @@ jiffies = jiffies_64;
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#endif
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SECTIONS
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{
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. = KERNEL_BINARY_TEXT_START;
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. = KERNEL_BINARY_TEXT_START;
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_text = .; /* Text and read-only data */
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.text ALIGN(16) : {
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TEXT_TEXT
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SCHED_TEXT
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LOCK_TEXT
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*(.text.do_softirq)
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*(.text.sys_exit)
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*(.text.do_sigaltstack)
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*(.text.do_fork)
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*(.text.*)
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*(.fixup)
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*(.lock.text) /* out-of-line lock text */
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*(.gnu.warning)
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_text = .; /* Text and read-only data */
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.text ALIGN(16) : {
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TEXT_TEXT
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SCHED_TEXT
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LOCK_TEXT
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*(.text.do_softirq)
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*(.text.sys_exit)
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*(.text.do_sigaltstack)
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*(.text.do_fork)
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*(.text.*)
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*(.fixup)
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*(.lock.text) /* out-of-line lock text */
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*(.gnu.warning)
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} = 0
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/* End of text section */
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_etext = .;
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_etext = .; /* End of text section */
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RODATA
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BUG_TABLE
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RODATA
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BUG_TABLE
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/* writeable */
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. = ALIGN(ASM_PAGE_SIZE); /* Make sure this is page aligned so
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that we can properly leave these
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as writable */
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data_start = .;
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. = ALIGN(16); /* Exception table */
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__start___ex_table = .;
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__ex_table : { *(__ex_table) }
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__stop___ex_table = .;
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NOTES
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__start___unwind = .; /* unwind info */
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.PARISC.unwind : { *(.PARISC.unwind) }
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__stop___unwind = .;
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/* rarely changed data like cpu maps */
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. = ALIGN(16);
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.data.read_mostly : { *(.data.read_mostly) }
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. = ALIGN(L1_CACHE_BYTES);
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.data : { /* Data */
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DATA_DATA
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CONSTRUCTORS
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/* writeable */
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/* Make sure this is page aligned so
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* that we can properly leave these
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* as writable
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*/
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. = ALIGN(ASM_PAGE_SIZE);
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data_start = .;
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. = ALIGN(16);
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/* Exception table */
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__ex_table : {
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__start___ex_table = .;
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*(__ex_table)
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__stop___ex_table = .;
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}
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. = ALIGN(L1_CACHE_BYTES);
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.data.cacheline_aligned : { *(.data.cacheline_aligned) }
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NOTES
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/* PA-RISC locks requires 16-byte alignment */
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. = ALIGN(16);
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.data.lock_aligned : { *(.data.lock_aligned) }
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. = ALIGN(ASM_PAGE_SIZE);
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/* nosave data is really only used for software suspend...it's here
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* just in case we ever implement it */
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__nosave_begin = .;
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.data_nosave : { *(.data.nosave) }
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. = ALIGN(ASM_PAGE_SIZE);
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__nosave_end = .;
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_edata = .; /* End of data section */
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__bss_start = .; /* BSS */
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/* page table entries need to be PAGE_SIZE aligned */
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. = ALIGN(ASM_PAGE_SIZE);
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.data.vmpages : {
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*(.data.vm0.pmd)
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*(.data.vm0.pgd)
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*(.data.vm0.pte)
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/* unwind info */
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.PARISC.unwind : {
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__start___unwind = .;
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*(.PARISC.unwind)
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__stop___unwind = .;
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}
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.bss : { *(.bss) *(COMMON) }
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__bss_stop = .;
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/* rarely changed data like cpu maps */
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. = ALIGN(16);
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.data.read_mostly : {
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*(.data.read_mostly)
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}
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. = ALIGN(L1_CACHE_BYTES);
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/* Data */
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.data : {
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DATA_DATA
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CONSTRUCTORS
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}
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. = ALIGN(L1_CACHE_BYTES);
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.data.cacheline_aligned : {
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*(.data.cacheline_aligned)
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}
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/* PA-RISC locks requires 16-byte alignment */
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. = ALIGN(16);
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.data.lock_aligned : {
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*(.data.lock_aligned)
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}
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/* nosave data is really only used for software suspend...it's here
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* just in case we ever implement it
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*/
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. = ALIGN(ASM_PAGE_SIZE);
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__nosave_begin = .;
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.data_nosave : {
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*(.data.nosave)
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}
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. = ALIGN(ASM_PAGE_SIZE);
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__nosave_end = .;
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/* End of data section */
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_edata = .;
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/* BSS */
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__bss_start = .;
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/* page table entries need to be PAGE_SIZE aligned */
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. = ALIGN(ASM_PAGE_SIZE);
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.data.vmpages : {
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*(.data.vm0.pmd)
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*(.data.vm0.pgd)
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*(.data.vm0.pte)
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}
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.bss : {
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*(.bss)
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*(COMMON)
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}
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__bss_stop = .;
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/* assembler code expects init_task to be 16k aligned */
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. = ALIGN(16384); /* init_task */
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.data.init_task : { *(.data.init_task) }
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/* assembler code expects init_task to be 16k aligned */
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. = ALIGN(16384);
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/* init_task */
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.data.init_task : {
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*(.data.init_task)
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}
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/* The interrupt stack is currently partially coded, but not yet
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* implemented */
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. = ALIGN(16384);
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init_istack : { *(init_istack) }
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/* The interrupt stack is currently partially coded, but not yet
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* implemented
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*/
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. = ALIGN(16384);
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init_istack : {
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*(init_istack)
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}
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#ifdef CONFIG_64BIT
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. = ALIGN(16); /* Linkage tables */
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.opd : { *(.opd) } PROVIDE (__gp = .);
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.plt : { *(.plt) }
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.dlt : { *(.dlt) }
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. = ALIGN(16);
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/* Linkage tables */
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.opd : {
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*(.opd)
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} PROVIDE (__gp = .);
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.plt : {
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*(.plt)
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}
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.dlt : {
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*(.dlt)
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}
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#endif
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/* reserve space for interrupt stack by aligning __init* to 16k */
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. = ALIGN(16384);
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__init_begin = .;
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.init.text : {
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_sinittext = .;
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*(.init.text)
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_einittext = .;
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}
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.init.data : { *(.init.data) }
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. = ALIGN(16);
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__setup_start = .;
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.init.setup : { *(.init.setup) }
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__setup_end = .;
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__initcall_start = .;
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.initcall.init : {
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INITCALLS
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}
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__initcall_end = .;
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__con_initcall_start = .;
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.con_initcall.init : { *(.con_initcall.init) }
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__con_initcall_end = .;
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SECURITY_INIT
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/* alternate instruction replacement. This is a mechanism x86 uses
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* to detect the CPU type and replace generic instruction sequences
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* with CPU specific ones. We don't currently do this in PA, but
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* it seems like a good idea... */
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. = ALIGN(4);
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__alt_instructions = .;
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.altinstructions : { *(.altinstructions) }
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__alt_instructions_end = .;
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.altinstr_replacement : { *(.altinstr_replacement) }
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/* .exit.text is discard at runtime, not link time, to deal with references
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from .altinstructions and .eh_frame */
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.exit.text : { *(.exit.text) }
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.exit.data : { *(.exit.data) }
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/* reserve space for interrupt stack by aligning __init* to 16k */
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. = ALIGN(16384);
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__init_begin = .;
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.init.text : {
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_sinittext = .;
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*(.init.text)
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_einittext = .;
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}
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.init.data : {
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*(.init.data)
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}
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. = ALIGN(16);
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.init.setup : {
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__setup_start = .;
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*(.init.setup)
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__setup_end = .;
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}
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.initcall.init : {
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__initcall_start = .;
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INITCALLS
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__initcall_end = .;
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}
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.con_initcall.init : {
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__con_initcall_start = .;
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*(.con_initcall.init)
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__con_initcall_end = .;
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}
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SECURITY_INIT
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/* alternate instruction replacement. This is a mechanism x86 uses
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* to detect the CPU type and replace generic instruction sequences
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* with CPU specific ones. We don't currently do this in PA, but
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* it seems like a good idea...
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*/
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. = ALIGN(4);
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.altinstructions : {
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__alt_instructions = .;
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*(.altinstructions)
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__alt_instructions_end = .;
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}
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.altinstr_replacement : {
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*(.altinstr_replacement)
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}
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/* .exit.text is discard at runtime, not link time, to deal with references
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* from .altinstructions and .eh_frame
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*/
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.exit.text : {
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*(.exit.text)
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}
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.exit.data : {
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*(.exit.data)
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}
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#ifdef CONFIG_BLK_DEV_INITRD
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. = ALIGN(ASM_PAGE_SIZE);
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__initramfs_start = .;
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.init.ramfs : { *(.init.ramfs) }
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__initramfs_end = .;
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. = ALIGN(ASM_PAGE_SIZE);
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.init.ramfs : {
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__initramfs_start = .;
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*(.init.ramfs)
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__initramfs_end = .;
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}
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#endif
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PERCPU(ASM_PAGE_SIZE)
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PERCPU(ASM_PAGE_SIZE)
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. = ALIGN(ASM_PAGE_SIZE);
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__init_end = .;
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/* freed after init ends here */
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_end = . ;
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. = ALIGN(ASM_PAGE_SIZE);
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__init_end = .;
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/* freed after init ends here */
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_end = . ;
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/* Sections to be discarded */
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/DISCARD/ : {
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*(.exitcall.exit)
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/* Sections to be discarded */
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/DISCARD/ : {
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*(.exitcall.exit)
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#ifdef CONFIG_64BIT
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/* temporary hack until binutils is fixed to not emit these
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for static binaries */
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*(.interp)
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*(.dynsym)
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*(.dynstr)
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*(.dynamic)
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*(.hash)
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*(.gnu.hash)
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/* temporary hack until binutils is fixed to not emit these
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* for static binaries
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*/
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*(.interp)
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*(.dynsym)
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*(.dynstr)
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*(.dynamic)
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*(.hash)
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*(.gnu.hash)
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#endif
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}
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STABS_DEBUG
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.note 0 : { *(.note) }
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STABS_DEBUG
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.note 0 : { *(.note) }
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}
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