[ARM] 4778/1: S3C2412: Add armclk and init from DVS state
Add armclk to the S3C2412 to indicate the current clock connected to the ARM core. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -234,6 +234,45 @@ static struct clk clk_msysclk = {
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.set_parent = s3c2412_setparent_msysclk,
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};
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static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
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{
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unsigned long flags;
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unsigned long clkdiv;
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unsigned long dvs;
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/* Note, we current equate fclk andf msysclk for S3C2412 */
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if (parent == &clk_msysclk || parent == &clk_f)
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dvs = 0;
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else if (parent == &clk_h)
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dvs = S3C2412_CLKDIVN_DVSEN;
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else
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return -EINVAL;
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clk->parent = parent;
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/* update this under irq lockdown, clkdivn is not protected
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* by the clock system. */
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local_irq_save(flags);
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clkdiv = __raw_readl(S3C2410_CLKDIVN);
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clkdiv &= ~S3C2412_CLKDIVN_DVSEN;
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clkdiv |= dvs;
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__raw_writel(clkdiv, S3C2410_CLKDIVN);
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local_irq_restore(flags);
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return 0;
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}
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static struct clk clk_armclk = {
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.name = "armclk",
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.id = -1,
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.parent = &clk_msysclk,
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.set_parent = s3c2412_setparent_armclk,
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};
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/* these next clocks have an divider immediately after them,
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* so we can register them with their divider and leave out the
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* intermediate clock stage
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@ -630,11 +669,13 @@ static struct clk *clks[] __initdata = {
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&clk_erefclk,
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&clk_urefclk,
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&clk_mrefclk,
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&clk_armclk,
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};
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int __init s3c2412_baseclk_add(void)
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{
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unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
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unsigned int dvs;
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struct clk *clkp;
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int ret;
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int ptr;
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@ -655,6 +696,15 @@ int __init s3c2412_baseclk_add(void)
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}
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}
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/* set the dvs state according to what we got at boot time */
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dvs = __raw_readl(S3C2410_CLKDIVN) & S3C2412_CLKDIVN_DVSEN;
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if (dvs)
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clk_armclk.parent = &clk_h;
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printk(KERN_INFO "S3C2412: DVS is %s\n", dvs ? "on" : "off");
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/* ensure usb bus clock is within correct rate of 48MHz */
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if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
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