Blackfin: update anomaly lists
Signed-off-by: Yi Li <yi.li@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Yi Li
Mike Frysinger
parent
f1cb64625c
commit
bd411b15cc
6 changed files with 35 additions and 6 deletions
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@ -124,6 +124,7 @@
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#define ANOMALY_05000386 (0)
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#define ANOMALY_05000389 (0)
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#define ANOMALY_05000400 (0)
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#define ANOMALY_05000402 (0)
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#define ANOMALY_05000412 (0)
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#define ANOMALY_05000432 (0)
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#define ANOMALY_05000447 (0)
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@ -7,7 +7,7 @@
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*/
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/* This file should be up to date with:
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* - Revision C, 03/13/2009; ADSP-BF526 Blackfin Processor Anomaly List
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* - Revision D, 08/14/2009; ADSP-BF526 Blackfin Processor Anomaly List
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* - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List
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*/
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@ -176,7 +176,7 @@
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#define ANOMALY_05000443 (1)
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/* The WURESET Bit in the SYSCR Register is not Functional */
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#define ANOMALY_05000445 (1)
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/* USB DMA Short Packet Data Corruption */
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/* USB DMA Mode 1 Short Packet Data Corruption */
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#define ANOMALY_05000450 (1)
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/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
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#define ANOMALY_05000451 (1)
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@ -186,12 +186,20 @@
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#define ANOMALY_05000456 (1)
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/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
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#define ANOMALY_05000457 (1)
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/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
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#define ANOMALY_05000460 (1)
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/* False Hardware Error when RETI Points to Invalid Memory */
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#define ANOMALY_05000461 (1)
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/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
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#define ANOMALY_05000462 (1)
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/* USB Rx DMA hang */
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#define ANOMALY_05000465 (1)
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/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
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#define ANOMALY_05000466 (1)
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/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
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#define ANOMALY_05000467 (1)
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/* PLL Latches Incorrect Settings During Reset */
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#define ANOMALY_05000469 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000099 (0)
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@ -238,6 +246,7 @@
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#define ANOMALY_05000362 (1)
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#define ANOMALY_05000363 (0)
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#define ANOMALY_05000400 (0)
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#define ANOMALY_05000402 (0)
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#define ANOMALY_05000412 (0)
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#define ANOMALY_05000447 (0)
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#define ANOMALY_05000448 (0)
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@ -143,7 +143,7 @@
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (1)
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/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
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#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
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#define ANOMALY_05000402 (__SILICON_REVISION__ == 2)
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/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
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#define ANOMALY_05000403 (1)
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/* Speculative Fetches Can Cause Undesired External FIFO Operations */
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@ -113,7 +113,7 @@
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/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
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#define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
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/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
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#define ANOMALY_05000402 (__SILICON_REVISION__ < 4)
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#define ANOMALY_05000402 (__SILICON_REVISION__ == 3)
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/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
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#define ANOMALY_05000403 (1)
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/* Speculative Fetches Can Cause Undesired External FIFO Operations */
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@ -7,7 +7,7 @@
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*/
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/* This file should be up to date with:
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* - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
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* - Revision I, 07/23/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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@ -162,6 +162,8 @@
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#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
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/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
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#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
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/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
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#define ANOMALY_05000434 (1)
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/* OTP Write Accesses Not Supported */
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#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
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/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
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@ -176,12 +178,26 @@
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#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
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/* USB DMA Mode 1 Short Packet Data Corruption */
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#define ANOMALY_05000450 (1)
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/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
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#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
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/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
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#define ANOMALY_05000456 (__SILICON_REVISION__ < 3)
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#define ANOMALY_05000456 (1)
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/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
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#define ANOMALY_05000457 (1)
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/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
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#define ANOMALY_05000460 (1)
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/* False Hardware Error when RETI Points to Invalid Memory */
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#define ANOMALY_05000461 (1)
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/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
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#define ANOMALY_05000462 (1)
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/* USB DMA RX Data Corruption */
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#define ANOMALY_05000463 (1)
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/* USB TX DMA Hang */
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#define ANOMALY_05000464 (1)
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/* USB Rx DMA hang */
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#define ANOMALY_05000465 (1)
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/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
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#define ANOMALY_05000466 (1)
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/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
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#define ANOMALY_05000467 (1)
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@ -230,6 +246,7 @@
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#define ANOMALY_05000364 (0)
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#define ANOMALY_05000380 (0)
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#define ANOMALY_05000400 (0)
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#define ANOMALY_05000402 (0)
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#define ANOMALY_05000412 (0)
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#define ANOMALY_05000432 (0)
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#define ANOMALY_05000435 (0)
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@ -262,6 +262,8 @@
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#define ANOMALY_05000366 (1)
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (1)
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/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
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#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
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/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
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#define ANOMALY_05000403 (1)
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/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
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