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Blackfin: update anomaly lists

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Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Yi Li 2009-08-05 10:02:14 +00:00 committed by Mike Frysinger
parent f1cb64625c
commit bd411b15cc
6 changed files with 35 additions and 6 deletions
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1
arch/blackfin/mach-bf518/include/mach/anomaly.h
View file

@ -124,6 +124,7 @@
#define ANOMALY_05000386 (0) #define ANOMALY_05000386 (0)
#define ANOMALY_05000389 (0) #define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0) #define ANOMALY_05000400 (0)
#define ANOMALY_05000402 (0)
#define ANOMALY_05000412 (0) #define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0) #define ANOMALY_05000432 (0)
#define ANOMALY_05000447 (0) #define ANOMALY_05000447 (0)

13
arch/blackfin/mach-bf527/include/mach/anomaly.h
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@ -7,7 +7,7 @@
*/ */
/* This file should be up to date with: /* This file should be up to date with:
* - Revision C, 03/13/2009; ADSP-BF526 Blackfin Processor Anomaly List * - Revision D, 08/14/2009; ADSP-BF526 Blackfin Processor Anomaly List
* - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List * - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List
*/ */
@ -176,7 +176,7 @@
#define ANOMALY_05000443 (1) #define ANOMALY_05000443 (1)
/* The WURESET Bit in the SYSCR Register is not Functional */ /* The WURESET Bit in the SYSCR Register is not Functional */
#define ANOMALY_05000445 (1) #define ANOMALY_05000445 (1)
/* USB DMA Short Packet Data Corruption */ /* USB DMA Mode 1 Short Packet Data Corruption */
#define ANOMALY_05000450 (1) #define ANOMALY_05000450 (1)
/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
#define ANOMALY_05000451 (1) #define ANOMALY_05000451 (1)
@ -186,12 +186,20 @@
#define ANOMALY_05000456 (1) #define ANOMALY_05000456 (1)
/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
#define ANOMALY_05000457 (1) #define ANOMALY_05000457 (1)
/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
#define ANOMALY_05000460 (1)
/* False Hardware Error when RETI Points to Invalid Memory */ /* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1) #define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
#define ANOMALY_05000462 (1)
/* USB Rx DMA hang */ /* USB Rx DMA hang */
#define ANOMALY_05000465 (1) #define ANOMALY_05000465 (1)
/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
#define ANOMALY_05000466 (1)
/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ /* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
#define ANOMALY_05000467 (1) #define ANOMALY_05000467 (1)
/* PLL Latches Incorrect Settings During Reset */
#define ANOMALY_05000469 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0) #define ANOMALY_05000099 (0)
@ -238,6 +246,7 @@
#define ANOMALY_05000362 (1) #define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0) #define ANOMALY_05000363 (0)
#define ANOMALY_05000400 (0) #define ANOMALY_05000400 (0)
#define ANOMALY_05000402 (0)
#define ANOMALY_05000412 (0) #define ANOMALY_05000412 (0)
#define ANOMALY_05000447 (0) #define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0) #define ANOMALY_05000448 (0)

2
arch/blackfin/mach-bf537/include/mach/anomaly.h
View file

@ -143,7 +143,7 @@
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1) #define ANOMALY_05000371 (1)
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) #define ANOMALY_05000402 (__SILICON_REVISION__ == 2)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1) #define ANOMALY_05000403 (1)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */ /* Speculative Fetches Can Cause Undesired External FIFO Operations */

2
arch/blackfin/mach-bf538/include/mach/anomaly.h
View file

@ -113,7 +113,7 @@
/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */ /* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
#define ANOMALY_05000375 (__SILICON_REVISION__ < 4) #define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
#define ANOMALY_05000402 (__SILICON_REVISION__ < 4) #define ANOMALY_05000402 (__SILICON_REVISION__ == 3)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1) #define ANOMALY_05000403 (1)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */ /* Speculative Fetches Can Cause Undesired External FIFO Operations */

21
arch/blackfin/mach-bf548/include/mach/anomaly.h
View file

@ -7,7 +7,7 @@
*/ */
/* This file should be up to date with: /* This file should be up to date with:
* - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List * - Revision I, 07/23/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
*/ */
#ifndef _MACH_ANOMALY_H_ #ifndef _MACH_ANOMALY_H_
@ -162,6 +162,8 @@
#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
/* Incorrect Use of Stack in Lockbox Firmware During Authentication */ /* Incorrect Use of Stack in Lockbox Firmware During Authentication */
#define ANOMALY_05000431 (__SILICON_REVISION__ < 3) #define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
#define ANOMALY_05000434 (1)
/* OTP Write Accesses Not Supported */ /* OTP Write Accesses Not Supported */
#define ANOMALY_05000442 (__SILICON_REVISION__ < 1) #define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
@ -176,12 +178,26 @@
#define ANOMALY_05000449 (__SILICON_REVISION__ == 1) #define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
/* USB DMA Mode 1 Short Packet Data Corruption */ /* USB DMA Mode 1 Short Packet Data Corruption */
#define ANOMALY_05000450 (1) #define ANOMALY_05000450 (1)
/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
#define ANOMALY_05000456 (__SILICON_REVISION__ < 3) #define ANOMALY_05000456 (1)
/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
#define ANOMALY_05000457 (1)
/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
#define ANOMALY_05000460 (1)
/* False Hardware Error when RETI Points to Invalid Memory */ /* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1) #define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
#define ANOMALY_05000462 (1)
/* USB DMA RX Data Corruption */
#define ANOMALY_05000463 (1)
/* USB TX DMA Hang */
#define ANOMALY_05000464 (1)
/* USB Rx DMA hang */ /* USB Rx DMA hang */
#define ANOMALY_05000465 (1) #define ANOMALY_05000465 (1)
/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
#define ANOMALY_05000466 (1)
/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ /* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
#define ANOMALY_05000467 (1) #define ANOMALY_05000467 (1)
@ -230,6 +246,7 @@
#define ANOMALY_05000364 (0) #define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0) #define ANOMALY_05000380 (0)
#define ANOMALY_05000400 (0) #define ANOMALY_05000400 (0)
#define ANOMALY_05000402 (0)
#define ANOMALY_05000412 (0) #define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0) #define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0) #define ANOMALY_05000435 (0)

2
arch/blackfin/mach-bf561/include/mach/anomaly.h
View file

@ -262,6 +262,8 @@
#define ANOMALY_05000366 (1) #define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1) #define ANOMALY_05000371 (1)
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1) #define ANOMALY_05000403 (1)
/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ /* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */