drm/radeon: add support mc ucode loading on CIK (v2)
Load the GDDR5 ucode and train the links. v2: update ucode Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher
parent
02c8132741
commit
bc8273fe97
2 changed files with 132 additions and 0 deletions
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@ -65,6 +65,122 @@ extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_sa
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extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
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extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
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#define BONAIRE_IO_MC_REGS_SIZE 36
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static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =
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{
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{0x00000070, 0x04400000},
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{0x00000071, 0x80c01803},
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{0x00000072, 0x00004004},
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{0x00000073, 0x00000100},
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{0x00000074, 0x00ff0000},
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{0x00000075, 0x34000000},
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{0x00000076, 0x08000014},
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{0x00000077, 0x00cc08ec},
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{0x00000078, 0x00000400},
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{0x00000079, 0x00000000},
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{0x0000007a, 0x04090000},
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{0x0000007c, 0x00000000},
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{0x0000007e, 0x4408a8e8},
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{0x0000007f, 0x00000304},
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{0x00000080, 0x00000000},
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{0x00000082, 0x00000001},
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{0x00000083, 0x00000002},
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{0x00000084, 0xf3e4f400},
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{0x00000085, 0x052024e3},
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{0x00000087, 0x00000000},
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{0x00000088, 0x01000000},
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{0x0000008a, 0x1c0a0000},
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{0x0000008b, 0xff010000},
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{0x0000008d, 0xffffefff},
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{0x0000008e, 0xfff3efff},
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{0x0000008f, 0xfff3efbf},
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{0x00000092, 0xf7ffffff},
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{0x00000093, 0xffffff7f},
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{0x00000095, 0x00101101},
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{0x00000096, 0x00000fff},
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{0x00000097, 0x00116fff},
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{0x00000098, 0x60010000},
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{0x00000099, 0x10010000},
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{0x0000009a, 0x00006000},
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{0x0000009b, 0x00001000},
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{0x0000009f, 0x00b48000}
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};
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/* ucode loading */
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/**
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* ci_mc_load_microcode - load MC ucode into the hw
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*
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* @rdev: radeon_device pointer
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*
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* Load the GDDR MC ucode into the hw (CIK).
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* Returns 0 on success, error on failure.
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*/
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static int ci_mc_load_microcode(struct radeon_device *rdev)
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{
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const __be32 *fw_data;
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u32 running, blackout = 0;
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u32 *io_mc_regs;
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int i, ucode_size, regs_size;
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if (!rdev->mc_fw)
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return -EINVAL;
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switch (rdev->family) {
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case CHIP_BONAIRE:
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default:
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io_mc_regs = (u32 *)&bonaire_io_mc_regs;
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ucode_size = CIK_MC_UCODE_SIZE;
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regs_size = BONAIRE_IO_MC_REGS_SIZE;
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break;
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}
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running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
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if (running == 0) {
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if (running) {
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blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
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WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
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}
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/* reset the engine and set to writable */
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WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
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WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
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/* load mc io regs */
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for (i = 0; i < regs_size; i++) {
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WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
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WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
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}
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/* load the MC ucode */
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fw_data = (const __be32 *)rdev->mc_fw->data;
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for (i = 0; i < ucode_size; i++)
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WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
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/* put the engine back into the active state */
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WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
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WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
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WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
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/* wait for training to complete */
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for (i = 0; i < rdev->usec_timeout; i++) {
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if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
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break;
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udelay(1);
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}
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for (i = 0; i < rdev->usec_timeout; i++) {
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if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
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break;
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udelay(1);
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}
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if (running)
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WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
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}
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return 0;
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}
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/**
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* cik_init_microcode - load ucode images from disk
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*
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@ -139,6 +139,8 @@
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#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
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#define MC_VM_FB_OFFSET 0x2068
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#define MC_SHARED_BLACKOUT_CNTL 0x20ac
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#define MC_ARB_RAMCFG 0x2760
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#define NOOFBANK_SHIFT 0
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#define NOOFBANK_MASK 0x00000003
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@ -153,6 +155,20 @@
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#define NOOFGROUPS_SHIFT 12
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#define NOOFGROUPS_MASK 0x00001000
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#define MC_SEQ_SUP_CNTL 0x28c8
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#define RUN_MASK (1 << 0)
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#define MC_SEQ_SUP_PGM 0x28cc
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#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8
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#define TRAIN_DONE_D0 (1 << 30)
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#define TRAIN_DONE_D1 (1 << 31)
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#define MC_IO_PAD_CNTL_D0 0x29d0
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#define MEM_FALL_OUT_CMD (1 << 8)
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#define MC_SEQ_IO_DEBUG_INDEX 0x2a44
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#define MC_SEQ_IO_DEBUG_DATA 0x2a48
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#define HDP_HOST_PATH_CNTL 0x2C00
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#define HDP_NONSURFACE_BASE 0x2C04
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#define HDP_NONSURFACE_INFO 0x2C08
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