ASoC: RT286: Fix silent at the beginning of stream
This patch fix the issue that the output is almost silent at the beginning of starting a playback. Signed-off-by: Bard Liao <bardliao@realtek.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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61a414c412
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2 changed files with 24 additions and 1 deletions
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@ -54,6 +54,7 @@ static struct reg_default rt286_index_def[] = {
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{ 0x09, 0xd810 },
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{ 0x0a, 0x0060 },
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{ 0x0b, 0x0000 },
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{ 0x0d, 0x2800 },
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{ 0x0f, 0x0000 },
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{ 0x19, 0x0a17 },
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{ 0x20, 0x0020 },
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@ -62,6 +63,9 @@ static struct reg_default rt286_index_def[] = {
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{ 0x4f, 0x50e9 },
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{ 0x50, 0x2c00 },
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{ 0x63, 0x2902 },
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{ 0x67, 0x1111 },
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{ 0x68, 0x1016 },
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{ 0x69, 0x273f },
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};
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#define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
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@ -902,14 +906,23 @@ static int rt286_set_bias_level(struct snd_soc_codec *codec,
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{
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switch (level) {
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case SND_SOC_BIAS_PREPARE:
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if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level)
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if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
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snd_soc_write(codec,
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RT286_SET_AUDIO_POWER, AC_PWRST_D0);
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snd_soc_update_bits(codec,
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RT286_DC_GAIN, 0x200, 0x200);
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}
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break;
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case SND_SOC_BIAS_ON:
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mdelay(10);
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break;
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case SND_SOC_BIAS_STANDBY:
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snd_soc_write(codec,
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RT286_SET_AUDIO_POWER, AC_PWRST_D3);
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snd_soc_update_bits(codec,
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RT286_DC_GAIN, 0x200, 0x0);
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break;
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default:
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@ -1152,6 +1165,11 @@ static int rt286_i2c_probe(struct i2c_client *i2c,
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/*Power down LDO2*/
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regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0x8, 0x0);
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/*Set depop parameter*/
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regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
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regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
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regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
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if (rt286->i2c->irq) {
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regmap_update_bits(rt286->regmap,
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RT286_IRQ_CTRL, 0x2, 0x2);
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@ -127,6 +127,7 @@
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#define RT286_I2S_CTRL1 0x09
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#define RT286_I2S_CTRL2 0x0a
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#define RT286_CLK_DIV 0x0b
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#define RT286_DC_GAIN 0x0d
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#define RT286_POWER_CTRL3 0x0f
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#define RT286_MIC1_DET_CTRL 0x19
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#define RT286_MISC_CTRL1 0x20
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@ -135,6 +136,10 @@
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#define RT286_CBJ_CTRL1 0x4f
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#define RT286_CBJ_CTRL2 0x50
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#define RT286_PLL_CTRL 0x63
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#define RT286_DEPOP_CTRL1 0x66
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#define RT286_DEPOP_CTRL2 0x67
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#define RT286_DEPOP_CTRL3 0x68
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#define RT286_DEPOP_CTRL4 0x69
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/* SPDIF (0x06) */
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#define RT286_SPDIF_SEL_SFT 0
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