x86: integrate start_secondary
It now looks the same between architectures, so we merge it in smpboot.c. Minor differences goes inside an ifdef Signed-off-by: Glauber Costa <gcosta@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Glauber de Oliveira Costa
Ingo Molnar
parent
cb3c8b9003
commit
bbc2ff6a91
3 changed files with 85 additions and 139 deletions
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@ -17,6 +17,7 @@
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#include <asm/tlbflush.h>
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#include <asm/mtrr.h>
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#include <asm/nmi.h>
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#include <asm/vmi.h>
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#include <linux/mc146818rtc.h>
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#include <mach_apic.h>
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@ -229,6 +230,90 @@ void __cpuinit smp_callin(void)
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cpu_set(cpuid, cpu_callin_map);
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}
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/*
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* Activate a secondary processor.
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*/
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void __cpuinit start_secondary(void *unused)
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{
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/*
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* Don't put *anything* before cpu_init(), SMP booting is too
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* fragile that we want to limit the things done here to the
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* most necessary things.
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*/
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#ifdef CONFIG_VMI
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vmi_bringup();
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#endif
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cpu_init();
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preempt_disable();
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smp_callin();
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/* otherwise gcc will move up smp_processor_id before the cpu_init */
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barrier();
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/*
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* Check TSC synchronization with the BP:
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*/
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check_tsc_sync_target();
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if (nmi_watchdog == NMI_IO_APIC) {
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disable_8259A_irq(0);
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enable_NMI_through_LVT0();
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enable_8259A_irq(0);
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}
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/* This must be done before setting cpu_online_map */
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set_cpu_sibling_map(raw_smp_processor_id());
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wmb();
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/*
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* We need to hold call_lock, so there is no inconsistency
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* between the time smp_call_function() determines number of
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* IPI recipients, and the time when the determination is made
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* for which cpus receive the IPI. Holding this
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* lock helps us to not include this cpu in a currently in progress
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* smp_call_function().
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*/
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lock_ipi_call_lock();
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#ifdef CONFIG_X86_64
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spin_lock(&vector_lock);
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/* Setup the per cpu irq handling data structures */
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__setup_vector_irq(smp_processor_id());
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/*
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* Allow the master to continue.
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*/
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spin_unlock(&vector_lock);
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#endif
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cpu_set(smp_processor_id(), cpu_online_map);
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unlock_ipi_call_lock();
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per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
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setup_secondary_clock();
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wmb();
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cpu_idle();
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}
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#ifdef CONFIG_X86_32
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/*
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* Everything has been set up for the secondary
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* CPUs - they just need to reload everything
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* from the task structure
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* This function must not return.
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*/
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void __devinit initialize_secondary(void)
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{
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/*
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* We don't actually need to load the full TSS,
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* basically just the stack pointer and the ip.
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*/
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asm volatile(
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"movl %0,%%esp\n\t"
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"jmp *%1"
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:
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:"m" (current->thread.sp), "m" (current->thread.ip));
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}
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#endif
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static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c)
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{
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@ -533,7 +618,6 @@ wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
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}
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#endif /* WAKE_SECONDARY_VIA_NMI */
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extern void start_secondary(void *unused);
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#ifdef WAKE_SECONDARY_VIA_INIT
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static int __devinit
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wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
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@ -80,81 +80,6 @@ extern void unmap_cpu_to_logical_apicid(int cpu);
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/* State of each CPU. */
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DEFINE_PER_CPU(int, cpu_state) = { 0 };
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extern void smp_callin(void);
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/*
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* Activate a secondary processor.
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*/
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void __cpuinit start_secondary(void *unused)
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{
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/*
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* Don't put *anything* before cpu_init(), SMP booting is too
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* fragile that we want to limit the things done here to the
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* most necessary things.
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*/
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#ifdef CONFIG_VMI
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vmi_bringup();
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#endif
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cpu_init();
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preempt_disable();
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smp_callin();
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/* otherwise gcc will move up smp_processor_id before the cpu_init */
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barrier();
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/*
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* Check TSC synchronization with the BP:
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*/
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check_tsc_sync_target();
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if (nmi_watchdog == NMI_IO_APIC) {
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disable_8259A_irq(0);
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enable_NMI_through_LVT0();
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enable_8259A_irq(0);
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}
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/* This must be done before setting cpu_online_map */
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set_cpu_sibling_map(raw_smp_processor_id());
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wmb();
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/*
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* We need to hold call_lock, so there is no inconsistency
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* between the time smp_call_function() determines number of
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* IPI recipients, and the time when the determination is made
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* for which cpus receive the IPI. Holding this
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* lock helps us to not include this cpu in a currently in progress
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* smp_call_function().
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*/
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lock_ipi_call_lock();
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cpu_set(smp_processor_id(), cpu_online_map);
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unlock_ipi_call_lock();
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per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
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setup_secondary_clock();
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wmb();
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cpu_idle();
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}
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/*
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* Everything has been set up for the secondary
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* CPUs - they just need to reload everything
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* from the task structure
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* This function must not return.
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*/
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void __devinit initialize_secondary(void)
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{
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/*
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* We don't actually need to load the full TSS,
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* basically just the stack pointer and the ip.
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*/
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asm volatile(
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"movl %0,%%esp\n\t"
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"jmp *%1"
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:
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:"m" (current->thread.sp),"m" (current->thread.ip));
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}
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#ifdef CONFIG_HOTPLUG_CPU
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void cpu_exit_clear(void)
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{
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@ -71,69 +71,6 @@ int smp_threads_ready;
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/* State of each CPU */
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DEFINE_PER_CPU(int, cpu_state) = { 0 };
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extern void smp_callin(void);
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/*
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* Setup code on secondary processor (after comming out of the trampoline)
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*/
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void __cpuinit start_secondary(void)
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{
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/*
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* Dont put anything before smp_callin(), SMP
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* booting is too fragile that we want to limit the
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* things done here to the most necessary things.
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*/
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cpu_init();
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preempt_disable();
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smp_callin();
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/* otherwise gcc will move up the smp_processor_id before the cpu_init */
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barrier();
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/*
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* Check TSC sync first:
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*/
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check_tsc_sync_target();
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if (nmi_watchdog == NMI_IO_APIC) {
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disable_8259A_irq(0);
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enable_NMI_through_LVT0();
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enable_8259A_irq(0);
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}
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/*
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* The sibling maps must be set before turing the online map on for
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* this cpu
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*/
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set_cpu_sibling_map(smp_processor_id());
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/*
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* We need to hold call_lock, so there is no inconsistency
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* between the time smp_call_function() determines number of
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* IPI recipients, and the time when the determination is made
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* for which cpus receive the IPI in genapic_flat.c. Holding this
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* lock helps us to not include this cpu in a currently in progress
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* smp_call_function().
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*/
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lock_ipi_call_lock();
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spin_lock(&vector_lock);
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/* Setup the per cpu irq handling data structures */
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__setup_vector_irq(smp_processor_id());
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/*
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* Allow the master to continue.
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*/
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spin_unlock(&vector_lock);
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cpu_set(smp_processor_id(), cpu_online_map);
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unlock_ipi_call_lock();
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per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
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setup_secondary_clock();
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wmb();
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cpu_idle();
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}
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cycles_t cacheflush_time;
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unsigned long cache_decay_ticks;
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