ARM: u300: move the gated system controller clocks to DT
This moves the slow, fast, AHB bridge and "rest" clocks on the U300 system controller over to registration from the device tree. Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
2165f836c8
commit
bba5f2cc2f
4 changed files with 418 additions and 110 deletions
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@ -0,0 +1,57 @@
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Clock bindings for ST-Ericsson U300 System Controller Clocks
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Bindings for the gated system controller clocks:
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Required properties:
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- compatible: must be "stericsson,u300-syscon-clk"
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- #clock-cells: must be <0>
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- clock-type: specifies the type of clock:
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0 = slow clock
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1 = fast clock
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2 = rest/remaining clock
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- clock-id: specifies the clock in the type range
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Optional properties:
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- clocks: parent clock(s)
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The available clocks per type are as follows:
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Type: ID: Clock:
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-------------------
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0 0 Slow peripheral bridge clock
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0 1 UART0 clock
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0 4 GPIO clock
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0 6 RTC clock
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0 7 Application timer clock
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0 8 Access timer clock
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1 0 Fast peripheral bridge clock
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1 1 I2C bus 0 clock
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1 2 I2C bus 1 clock
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1 5 MMC interface peripheral (silicon) clock
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1 6 SPI clock
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2 3 CPU clock
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2 4 DMA controller clock
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2 5 External Memory Interface (EMIF) clock
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2 6 NAND flask interface clock
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2 8 XGAM graphics engine clock
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2 9 Shared External Memory Interface (SEMI) clock
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2 10 AHB Subsystem Bridge clock
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2 12 Interrupt controller clock
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Example:
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gpio_clk: gpio_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <4>;
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clocks = <&slow_clk>;
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};
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gpio: gpio@c0016000 {
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compatible = "stericsson,gpio-coh901";
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(...)
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clocks = <&gpio_clk>;
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};
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@ -43,6 +43,49 @@
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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};
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/* Slow bridge clocks under PLL13 */
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slow_clk: slow_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <0>;
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clocks = <&pll13>;
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};
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uart0_clk: uart0_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <1>;
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clocks = <&slow_clk>;
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};
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gpio_clk: gpio_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <4>;
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clocks = <&slow_clk>;
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};
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rtc_clk: rtc_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <6>;
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clocks = <&slow_clk>;
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};
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apptimer_clk: app_tmr_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <7>;
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clocks = <&slow_clk>;
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};
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acc_tmr_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <8>;
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clocks = <&slow_clk>;
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};
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pll208: pll208@208M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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@ -55,6 +98,13 @@
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clock-mult = <1>;
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clocks = <&pll208>;
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};
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cpu_clk@208M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <3>;
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clocks = <&app208>;
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};
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app104: app_104_clk@104M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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@ -62,6 +112,13 @@
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clock-mult = <1>;
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clocks = <&pll208>;
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};
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semi_clk@104M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <9>;
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clocks = <&app104>;
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};
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app52: app_52_clk@52M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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@ -69,6 +126,49 @@
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clock-mult = <1>;
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clocks = <&pll208>;
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};
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/* AHB subsystem clocks */
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ahb_clk: ahb_subsys_clk@52M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <10>;
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clocks = <&app52>;
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};
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intcon_clk@52M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <12>;
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clocks = <&ahb_clk>;
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};
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emif_clk@52M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <5>;
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clocks = <&ahb_clk>;
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};
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dmac_clk: dmac_clk@52M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <4>;
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clocks = <&app52>;
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};
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fsmc_clk: fsmc_clk@52M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <6>;
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clocks = <&app52>;
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};
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xgam_clk: xgam_clk@52M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <8>;
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clocks = <&app52>;
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};
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app26: app_26_clk@26M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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@ -76,6 +176,42 @@
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clock-mult = <1>;
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clocks = <&app52>;
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};
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/* Fast bridge clocks */
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fast_clk: fast_clk@26M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <1>; /* Fast */
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clock-id = <0>;
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clocks = <&app26>;
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};
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i2c0_clk: i2c0_clk@26M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <1>; /* Fast */
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clock-id = <1>;
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clocks = <&fast_clk>;
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};
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i2c1_clk: i2c1_clk@26M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <1>; /* Fast */
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clock-id = <2>;
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clocks = <&fast_clk>;
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};
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mmc_pclk: mmc_p_clk@26M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <1>; /* Fast */
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clock-id = <5>;
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clocks = <&fast_clk>;
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};
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spi_clk: spi_p_clk@26M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <1>; /* Fast */
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clock-id = <6>;
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clocks = <&fast_clk>;
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};
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};
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timer: timer@c0014000 {
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@ -83,6 +219,7 @@
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reg = <0xc0014000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <24 25 26 27>;
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clocks = <&apptimer_clk>;
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};
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gpio: gpio@c0016000 {
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@ -90,6 +227,7 @@
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reg = <0xc0016000 0x1000>;
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interrupt-parent = <&vicb>;
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interrupts = <0 1 2 18 21 22 23>;
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clocks = <&gpio_clk>;
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interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
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"gpio4", "gpio5", "gpio6";
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interrupt-controller;
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@ -116,6 +254,7 @@
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reg = <0xc0017000 0x1000>;
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interrupt-parent = <&vicb>;
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interrupts = <10>;
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clocks = <&rtc_clk>;
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};
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dmac: dma-controller@c00020000 {
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@ -125,6 +264,7 @@
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interrupts = <2>;
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#dma-cells = <1>;
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dma-channels = <40>;
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clocks = <&dmac_clk>;
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};
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/* A NAND flash of 128 MiB */
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@ -138,6 +278,7 @@
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<0x80010000 0x4000>; /* NAND Base CMD */
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reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
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nand-skip-bbtscan;
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clocks = <&fsmc_clk>;
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partition@0 {
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label = "boot records";
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@ -158,6 +299,7 @@
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reg = <0xc0004000 0x1000>;
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interrupt-parent = <&vicb>;
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interrupts = <8>;
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clocks = <&i2c0_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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ab3100: ab3100@0x48 {
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@ -235,6 +377,7 @@
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reg = <0xc0005000 0x1000>;
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interrupt-parent = <&vicb>;
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interrupts = <9>;
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clocks = <&i2c1_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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fwcam0: fwcam@0x10 {
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@ -270,6 +413,8 @@
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reg = <0xc0013000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <22>;
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clocks = <&uart0_clk>, <&uart0_clk>;
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clock-names = "apb_pclk", "uart0_clk";
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dmas = <&dmac 17 &dmac 18>;
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dma-names = "tx", "rx";
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};
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@ -288,6 +433,8 @@
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reg = <0xc0001000 0x1000>;
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interrupt-parent = <&vicb>;
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interrupts = <6 7>;
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clocks = <&mmc_pclk>;
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clock-names = "apb_pclk";
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max-frequency = <24000000>;
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bus-width = <4>; // SD-card slot
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mmc-cap-mmc-highspeed;
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@ -304,6 +451,8 @@
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reg = <0xc0006000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <23>;
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clocks = <&spi_clk>, <&spi_clk>;
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clock-names = "apb_pclk", "spi_clk";
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dmas = <&dmac 27 &dmac 28>;
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dma-names = "tx", "rx";
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num-cs = <3>;
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@ -375,7 +375,7 @@ static void __init u300_timer_init_of(struct device_node *np)
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pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
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/* Clock the interrupt controller */
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clk = clk_get_sys("apptimer", NULL);
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clk = of_clk_get(np, 0);
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BUG_ON(IS_ERR(clk));
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clk_prepare_enable(clk);
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rate = clk_get_rate(clk);
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@ -728,6 +728,213 @@ syscon_clk_register(struct device *dev, const char *name,
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return clk;
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}
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#define U300_CLK_TYPE_SLOW 0
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#define U300_CLK_TYPE_FAST 1
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#define U300_CLK_TYPE_REST 2
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/**
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* struct u300_clock - defines the bits and pieces for a certain clock
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* @type: the clock type, slow fast or rest
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* @id: the bit in the slow/fast/rest register for this clock
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* @hw_ctrld: whether the clock is hardware controlled
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* @clk_val: a value to poke in the one-write enable/disable registers
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*/
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struct u300_clock {
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u8 type;
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u8 id;
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bool hw_ctrld;
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u16 clk_val;
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};
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struct u300_clock const __initconst u300_clk_lookup[] = {
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{
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.type = U300_CLK_TYPE_REST,
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.id = 3,
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.hw_ctrld = true,
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.clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
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},
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{
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.type = U300_CLK_TYPE_REST,
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.id = 4,
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.hw_ctrld = true,
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.clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
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},
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{
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.type = U300_CLK_TYPE_REST,
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.id = 5,
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.hw_ctrld = false,
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.clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
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},
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{
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.type = U300_CLK_TYPE_REST,
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.id = 6,
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.hw_ctrld = false,
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.clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
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},
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{
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.type = U300_CLK_TYPE_REST,
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.id = 8,
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.hw_ctrld = true,
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.clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
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},
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{
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.type = U300_CLK_TYPE_REST,
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.id = 9,
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.hw_ctrld = false,
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.clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
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},
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{
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.type = U300_CLK_TYPE_REST,
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.id = 10,
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.hw_ctrld = true,
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.clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
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},
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{
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.type = U300_CLK_TYPE_REST,
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.id = 12,
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.hw_ctrld = false,
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/* INTCON: cannot be enabled, just taken out of reset */
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.clk_val = 0xFFFFU,
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},
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{
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.type = U300_CLK_TYPE_FAST,
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.id = 0,
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.hw_ctrld = true,
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.clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
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},
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{
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.type = U300_CLK_TYPE_FAST,
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.id = 1,
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.hw_ctrld = false,
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.clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
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},
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{
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.type = U300_CLK_TYPE_FAST,
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.id = 2,
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.hw_ctrld = false,
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.clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
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},
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{
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.type = U300_CLK_TYPE_FAST,
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.id = 5,
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.hw_ctrld = false,
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.clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
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},
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{
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.type = U300_CLK_TYPE_FAST,
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.id = 6,
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.hw_ctrld = false,
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.clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
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},
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{
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.type = U300_CLK_TYPE_SLOW,
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.id = 0,
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.hw_ctrld = true,
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.clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
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},
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{
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.type = U300_CLK_TYPE_SLOW,
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.id = 1,
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.hw_ctrld = false,
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.clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
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},
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{
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.type = U300_CLK_TYPE_SLOW,
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.id = 4,
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.hw_ctrld = false,
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.clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
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},
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{
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.type = U300_CLK_TYPE_SLOW,
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.id = 6,
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.hw_ctrld = true,
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/* No clock enable register bit */
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.clk_val = 0xFFFFU,
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},
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{
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.type = U300_CLK_TYPE_SLOW,
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.id = 7,
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.hw_ctrld = false,
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.clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
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},
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{
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.type = U300_CLK_TYPE_SLOW,
|
||||
.id = 8,
|
||||
.hw_ctrld = false,
|
||||
.clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
|
||||
},
|
||||
};
|
||||
|
||||
static void __init of_u300_syscon_clk_init(struct device_node *np)
|
||||
{
|
||||
struct clk *clk = ERR_PTR(-EINVAL);
|
||||
const char *clk_name = np->name;
|
||||
const char *parent_name;
|
||||
void __iomem *res_reg;
|
||||
void __iomem *en_reg;
|
||||
u32 clk_type;
|
||||
u32 clk_id;
|
||||
int i;
|
||||
|
||||
if (of_property_read_u32(np, "clock-type", &clk_type)) {
|
||||
pr_err("%s: syscon clock \"%s\" missing clock-type property\n",
|
||||
__func__, clk_name);
|
||||
return;
|
||||
}
|
||||
if (of_property_read_u32(np, "clock-id", &clk_id)) {
|
||||
pr_err("%s: syscon clock \"%s\" missing clock-id property\n",
|
||||
__func__, clk_name);
|
||||
return;
|
||||
}
|
||||
parent_name = of_clk_get_parent_name(np, 0);
|
||||
|
||||
switch (clk_type) {
|
||||
case U300_CLK_TYPE_SLOW:
|
||||
res_reg = syscon_vbase + U300_SYSCON_RSR;
|
||||
en_reg = syscon_vbase + U300_SYSCON_CESR;
|
||||
break;
|
||||
case U300_CLK_TYPE_FAST:
|
||||
res_reg = syscon_vbase + U300_SYSCON_RFR;
|
||||
en_reg = syscon_vbase + U300_SYSCON_CEFR;
|
||||
break;
|
||||
case U300_CLK_TYPE_REST:
|
||||
res_reg = syscon_vbase + U300_SYSCON_RRR;
|
||||
en_reg = syscon_vbase + U300_SYSCON_CERR;
|
||||
break;
|
||||
default:
|
||||
pr_err("unknown clock type %x specified\n", clk_type);
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) {
|
||||
const struct u300_clock *u3clk = &u300_clk_lookup[i];
|
||||
|
||||
if (u3clk->type == clk_type && u3clk->id == clk_id)
|
||||
clk = syscon_clk_register(NULL,
|
||||
clk_name, parent_name,
|
||||
0, u3clk->hw_ctrld,
|
||||
res_reg, u3clk->id,
|
||||
en_reg, u3clk->id,
|
||||
u3clk->clk_val);
|
||||
}
|
||||
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
||||
|
||||
/*
|
||||
* Some few system clocks - device tree does not
|
||||
* represent clocks without a corresponding device node.
|
||||
* for now we add these three clocks here.
|
||||
*/
|
||||
if (clk_type == U300_CLK_TYPE_REST && clk_id == 5)
|
||||
clk_register_clkdev(clk, NULL, "pl172");
|
||||
if (clk_type == U300_CLK_TYPE_REST && clk_id == 9)
|
||||
clk_register_clkdev(clk, NULL, "semi");
|
||||
if (clk_type == U300_CLK_TYPE_REST && clk_id == 12)
|
||||
clk_register_clkdev(clk, NULL, "intcon");
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* struct clk_mclk - U300 MCLK clock (MMC/SD clock)
|
||||
* @hw: corresponding clock hardware entry
|
||||
|
|
@ -941,6 +1148,10 @@ static const __initconst struct of_device_id u300_clk_match[] = {
|
|||
.compatible = "fixed-factor-clock",
|
||||
.data = of_fixed_factor_clk_setup,
|
||||
},
|
||||
{
|
||||
.compatible = "stericsson,u300-syscon-clk",
|
||||
.data = of_u300_syscon_clk_init,
|
||||
},
|
||||
};
|
||||
|
||||
void __init u300_clk_init(void __iomem *base)
|
||||
|
|
@ -965,115 +1176,6 @@ void __init u300_clk_init(void __iomem *base)
|
|||
|
||||
of_clk_init(u300_clk_match);
|
||||
|
||||
/* Directly on the AMBA interconnect */
|
||||
clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
|
||||
syscon_vbase + U300_SYSCON_RRR, 3,
|
||||
syscon_vbase + U300_SYSCON_CERR, 3,
|
||||
U300_SYSCON_SBCER_CPU_CLK_EN);
|
||||
clk = syscon_clk_register(NULL, "dmac_clk", "app_52_clk", 0, true,
|
||||
syscon_vbase + U300_SYSCON_RRR, 4,
|
||||
syscon_vbase + U300_SYSCON_CERR, 4,
|
||||
U300_SYSCON_SBCER_DMAC_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "dma");
|
||||
clk = syscon_clk_register(NULL, "fsmc_clk", "app_52_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RRR, 6,
|
||||
syscon_vbase + U300_SYSCON_CERR, 6,
|
||||
U300_SYSCON_SBCER_NANDIF_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "fsmc-nand");
|
||||
clk = syscon_clk_register(NULL, "xgam_clk", "app_52_clk", 0, true,
|
||||
syscon_vbase + U300_SYSCON_RRR, 8,
|
||||
syscon_vbase + U300_SYSCON_CERR, 8,
|
||||
U300_SYSCON_SBCER_XGAM_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "xgam");
|
||||
clk = syscon_clk_register(NULL, "semi_clk", "app_104_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RRR, 9,
|
||||
syscon_vbase + U300_SYSCON_CERR, 9,
|
||||
U300_SYSCON_SBCER_SEMI_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "semi");
|
||||
|
||||
/* AHB bridge clocks */
|
||||
clk = syscon_clk_register(NULL, "ahb_subsys_clk", "app_52_clk", 0, true,
|
||||
syscon_vbase + U300_SYSCON_RRR, 10,
|
||||
syscon_vbase + U300_SYSCON_CERR, 10,
|
||||
U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN);
|
||||
clk = syscon_clk_register(NULL, "intcon_clk", "ahb_subsys_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RRR, 12,
|
||||
syscon_vbase + U300_SYSCON_CERR, 12,
|
||||
/* Cannot be enabled, just taken out of reset */
|
||||
0xFFFFU);
|
||||
clk_register_clkdev(clk, NULL, "intcon");
|
||||
clk = syscon_clk_register(NULL, "emif_clk", "ahb_subsys_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RRR, 5,
|
||||
syscon_vbase + U300_SYSCON_CERR, 5,
|
||||
U300_SYSCON_SBCER_EMIF_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "pl172");
|
||||
|
||||
/* FAST bridge clocks */
|
||||
clk = syscon_clk_register(NULL, "fast_clk", "app_26_clk", 0, true,
|
||||
syscon_vbase + U300_SYSCON_RFR, 0,
|
||||
syscon_vbase + U300_SYSCON_CEFR, 0,
|
||||
U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN);
|
||||
clk = syscon_clk_register(NULL, "i2c0_p_clk", "fast_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RFR, 1,
|
||||
syscon_vbase + U300_SYSCON_CEFR, 1,
|
||||
U300_SYSCON_SBCER_I2C0_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "stu300.0");
|
||||
clk = syscon_clk_register(NULL, "i2c1_p_clk", "fast_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RFR, 2,
|
||||
syscon_vbase + U300_SYSCON_CEFR, 2,
|
||||
U300_SYSCON_SBCER_I2C1_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "stu300.1");
|
||||
clk = syscon_clk_register(NULL, "mmc_p_clk", "fast_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RFR, 5,
|
||||
syscon_vbase + U300_SYSCON_CEFR, 5,
|
||||
U300_SYSCON_SBCER_MMC_CLK_EN);
|
||||
clk_register_clkdev(clk, "apb_pclk", "mmci");
|
||||
clk = syscon_clk_register(NULL, "spi_p_clk", "fast_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RFR, 6,
|
||||
syscon_vbase + U300_SYSCON_CEFR, 6,
|
||||
U300_SYSCON_SBCER_SPI_CLK_EN);
|
||||
/* The SPI has no external clock for the outward bus, uses the pclk */
|
||||
clk_register_clkdev(clk, NULL, "pl022");
|
||||
clk_register_clkdev(clk, "apb_pclk", "pl022");
|
||||
|
||||
/* SLOW bridge clocks */
|
||||
clk = syscon_clk_register(NULL, "slow_clk", "pll13", 0, true,
|
||||
syscon_vbase + U300_SYSCON_RSR, 0,
|
||||
syscon_vbase + U300_SYSCON_CESR, 0,
|
||||
U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN);
|
||||
clk = syscon_clk_register(NULL, "uart0_clk", "slow_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RSR, 1,
|
||||
syscon_vbase + U300_SYSCON_CESR, 1,
|
||||
U300_SYSCON_SBCER_UART_CLK_EN);
|
||||
/* Same clock is used for APB and outward bus */
|
||||
clk_register_clkdev(clk, NULL, "uart0");
|
||||
clk_register_clkdev(clk, "apb_pclk", "uart0");
|
||||
clk = syscon_clk_register(NULL, "gpio_clk", "slow_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RSR, 4,
|
||||
syscon_vbase + U300_SYSCON_CESR, 4,
|
||||
U300_SYSCON_SBCER_GPIO_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "u300-gpio");
|
||||
clk = syscon_clk_register(NULL, "keypad_clk", "slow_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RSR, 5,
|
||||
syscon_vbase + U300_SYSCON_CESR, 6,
|
||||
U300_SYSCON_SBCER_KEYPAD_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "coh901461-keypad");
|
||||
clk = syscon_clk_register(NULL, "rtc_clk", "slow_clk", 0, true,
|
||||
syscon_vbase + U300_SYSCON_RSR, 6,
|
||||
/* No clock enable register bit */
|
||||
NULL, 0, 0xFFFFU);
|
||||
clk_register_clkdev(clk, NULL, "rtc-coh901331");
|
||||
clk = syscon_clk_register(NULL, "app_tmr_clk", "slow_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RSR, 7,
|
||||
syscon_vbase + U300_SYSCON_CESR, 7,
|
||||
U300_SYSCON_SBCER_APP_TMR_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "apptimer");
|
||||
clk = syscon_clk_register(NULL, "acc_tmr_clk", "slow_clk", 0, false,
|
||||
syscon_vbase + U300_SYSCON_RSR, 8,
|
||||
syscon_vbase + U300_SYSCON_CESR, 8,
|
||||
U300_SYSCON_SBCER_ACC_TMR_CLK_EN);
|
||||
clk_register_clkdev(clk, NULL, "timer");
|
||||
|
||||
/* Then this special MMC/SD clock */
|
||||
clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
|
||||
clk_register_clkdev(clk, NULL, "mmci");
|
||||
|
|
|
|||
Loading…
Reference in a new issue