drm/radeon/kms: DCE5 atom dig encoder updates
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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a001182af8
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1 changed files with 26 additions and 5 deletions
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@ -743,6 +743,7 @@ union dig_encoder_control {
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DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
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DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
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DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
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DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
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};
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void
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@ -758,6 +759,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
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uint8_t frev, crev;
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int dp_clock = 0;
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int dp_lane_count = 0;
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int hpd_id = RADEON_HPD_NONE;
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if (connector) {
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struct radeon_connector *radeon_connector = to_radeon_connector(connector);
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@ -766,6 +768,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
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dp_clock = dig_connector->dp_clock;
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dp_lane_count = dig_connector->dp_lane_count;
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hpd_id = radeon_connector->hpd.hpd;
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}
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/* no dig encoder assigned */
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@ -790,19 +793,36 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
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args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
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args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
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if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
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if (dp_clock == 270000)
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args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
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if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
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(args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST))
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args.v1.ucLaneNum = dp_lane_count;
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} else if (radeon_encoder->pixel_clock > 165000)
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else if (radeon_encoder->pixel_clock > 165000)
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args.v1.ucLaneNum = 8;
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else
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args.v1.ucLaneNum = 4;
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if (ASIC_IS_DCE4(rdev)) {
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if (ASIC_IS_DCE5(rdev)) {
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if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
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(args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) {
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if (dp_clock == 270000)
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args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
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else if (dp_clock == 540000)
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args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
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}
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args.v4.acConfig.ucDigSel = dig->dig_encoder;
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args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
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if (hpd_id == RADEON_HPD_NONE)
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args.v4.ucHPD_ID = 0;
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else
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args.v4.ucHPD_ID = hpd_id + 1;
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} else if (ASIC_IS_DCE4(rdev)) {
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if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
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args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
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args.v3.acConfig.ucDigSel = dig->dig_encoder;
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args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
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} else {
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if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
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args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
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args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
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@ -1538,6 +1558,7 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
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struct radeon_encoder_atom_dig *dig;
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uint32_t dig_enc_in_use = 0;
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/* DCE4/5 */
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if (ASIC_IS_DCE4(rdev)) {
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dig = radeon_encoder->enc_priv;
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if (ASIC_IS_DCE41(rdev)) {
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