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video: exynos_dp: check time loop for RPLY_RECEIV

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This patch checks time loop for RPLY_RECEIV which means that
AUX channel command reply is received.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
This commit is contained in:
Jingoo Han 2012-08-08 10:10:59 +09:00 committed by Florian Tobias Schandinat
parent a654ddac08
commit bada55371f
1 changed files with 9 additions and 1 deletions
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10
drivers/video/exynos/exynos_dp_reg.c
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@ -401,6 +401,7 @@ int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
{ {
int reg; int reg;
int retval = 0; int retval = 0;
int timeout_loop = 0;
/* Enable AUX CH operation */ /* Enable AUX CH operation */
reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
@ -409,8 +410,15 @@ int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
/* Is AUX CH command reply received? */ /* Is AUX CH command reply received? */
reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
while (!(reg & RPLY_RECEIV)) while (!(reg & RPLY_RECEIV)) {
timeout_loop++;
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
dev_err(dp->dev, "AUX CH command reply failed!\n");
return -ETIMEDOUT;
}
reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
usleep_range(10, 11);
}
/* Clear interrupt source for AUX CH command reply */ /* Clear interrupt source for AUX CH command reply */
writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA); writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);