From 9be58f317d79278afc23186d861ada774cf386ea Mon Sep 17 00:00:00 2001 From: David Brown Date: Fri, 12 Nov 2010 13:49:27 -0800 Subject: [PATCH 01/33] msm: smd: Reduce driver log chatter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MSM smd driver logs numerous messages during startup that are useful for debug purposes. Change some of these to pr_debug() to match their purpose, and remove others that aren't really useful. Cc: Brian Swetland Cc: Arve Hjønnevåg Signed-off-by: David Brown Signed-off-by: Daniel Walker --- arch/arm/mach-msm/smd.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c index f07dc7c738f0..657be73297db 100644 --- a/arch/arm/mach-msm/smd.c +++ b/arch/arm/mach-msm/smd.c @@ -14,6 +14,8 @@ * */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + #include #include #include @@ -89,7 +91,7 @@ static void smd_diag(void) x = smem_find(ID_DIAG_ERR_MSG, SZ_DIAG_ERR_MSG); if (x != 0) { x[SZ_DIAG_ERR_MSG - 1] = 0; - pr_info("smem: DIAG '%s'\n", x); + pr_debug("DIAG '%s'\n", x); } } @@ -312,7 +314,7 @@ static void smd_state_change(struct smd_channel *ch, { ch->last_state = next; - pr_info("SMD: ch %d %d -> %d\n", ch->n, last, next); + pr_debug("ch %d %d -> %d\n", ch->n, last, next); switch (next) { case SMD_SS_OPENING: @@ -601,7 +603,7 @@ static int smd_alloc_channel(const char *name, uint32_t cid, uint32_t type) ch->pdev.name = ch->name; ch->pdev.id = -1; - pr_info("smd_alloc_channel() cid=%02d size=%05d '%s'\n", + pr_debug("smd_alloc_channel() cid=%02d size=%05d '%s'\n", ch->n, ch->fifo_size, ch->name); mutex_lock(&smd_creation_mutex); @@ -621,7 +623,7 @@ static void smd_channel_probe_worker(struct work_struct *work) shared = smem_find(ID_CH_ALLOC_TBL, sizeof(*shared) * 64); if (!shared) { - pr_err("smd: cannot find allocation table\n"); + pr_err("cannot find allocation table\n"); return; } for (n = 0; n < 64; n++) { @@ -725,8 +727,6 @@ int smd_close(smd_channel_t *ch) { unsigned long flags; - pr_info("smd_close(%p)\n", ch); - if (ch == 0) return -1; @@ -939,7 +939,6 @@ int smsm_set_sleep_duration(uint32_t delay) int smd_core_init(void) { int r; - pr_info("smd_core_init()\n"); /* wait for essential items to be initialized */ for (;;) { @@ -992,15 +991,11 @@ int smd_core_init(void) smsm_change_state(SMSM_STATE_APPS_DEM, ~0, 0); #endif - pr_info("smd_core_init() done\n"); - return 0; } static int __devinit msm_smd_probe(struct platform_device *pdev) { - pr_info("smd_init()\n"); - /* * If we haven't waited for the ARM9 to boot up till now, * then we need to wait here. Otherwise this should just From 5d1394bb6b781df8148565783b0671f9b11500b7 Mon Sep 17 00:00:00 2001 From: David Brown Date: Fri, 12 Nov 2010 13:49:51 -0800 Subject: [PATCH 02/33] msm: sirc: remove some unused variables Eliminate some unreferenced variables. arch/arm/mach-msm/sirc.c:43: warning: 'save_type' defined but not used arch/arm/mach-msm/sirc.c:44: warning: 'save_polarity' defined but not used Signed-off-by: David Brown [dwalker@codeaurora.org: changed the commit text a little.] Signed-off-by: Daniel Walker --- arch/arm/mach-msm/sirc.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c index b0794524ba6e..152eefda3ce6 100644 --- a/arch/arm/mach-msm/sirc.c +++ b/arch/arm/mach-msm/sirc.c @@ -40,9 +40,6 @@ static struct sirc_cascade_regs sirc_reg_table[] = { } }; -static unsigned int save_type; -static unsigned int save_polarity; - /* Mask off the given interrupt. Keep the int_enable mask in sync with the enable reg, so it can be restored after power collapse. */ static void sirc_irq_mask(unsigned int irq) From d2c5d2145f127fffb7498bee943a480de66910ff Mon Sep 17 00:00:00 2001 From: David Brown Date: Fri, 12 Nov 2010 13:49:52 -0800 Subject: [PATCH 03/33] msm: smd: ifdef adjustment to remove unused variables Put some variables inside of the same ifdef as the code that uses them. arch/arm/mach-msm/smd_debug.c: In function 'smsm_print_sleep_info': arch/arm/mach-msm/smd_debug.c:274: warning: unused variable 'int_info' arch/arm/mach-msm/smd_debug.c:273: warning: unused variable 'gpio' Signed-off-by: David Brown [dwalker@codeaurora.org: changed the commit text a little.] Signed-off-by: Daniel Walker --- arch/arm/mach-msm/smd_debug.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-msm/smd_debug.c b/arch/arm/mach-msm/smd_debug.c index f91c3b7bc655..8736afff82f3 100644 --- a/arch/arm/mach-msm/smd_debug.c +++ b/arch/arm/mach-msm/smd_debug.c @@ -270,8 +270,10 @@ void smsm_print_sleep_info(void) { unsigned long flags; uint32_t *ptr; +#ifndef CONFIG_ARCH_MSM_SCORPION struct tramp_gpio_smem *gpio; struct smsm_interrupt_info *int_info; +#endif spin_lock_irqsave(&smem_lock, flags); From 44d4a4f784d0e1a50b3f1fc52bd6a661846abdc5 Mon Sep 17 00:00:00 2001 From: David Brown Date: Fri, 12 Nov 2010 13:49:53 -0800 Subject: [PATCH 04/33] msm: make constant unsigned long to correct format warning Define VMALLOC_END as an unsigned long to match expected type. Eliminates a warning: arch/arm/mm/init.c: In function 'mem_init': arch/arm/mm/init.c:606: warning: format '%08lx' expects type 'long unsigned int', but argument 12 has type 'unsigned int' Signed-off-by: David Brown Signed-off-by: Daniel Walker --- arch/arm/mach-msm/include/mach/vmalloc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-msm/include/mach/vmalloc.h b/arch/arm/mach-msm/include/mach/vmalloc.h index 31a32ad062dc..d138448eff16 100644 --- a/arch/arm/mach-msm/include/mach/vmalloc.h +++ b/arch/arm/mach-msm/include/mach/vmalloc.h @@ -16,7 +16,7 @@ #ifndef __ASM_ARCH_MSM_VMALLOC_H #define __ASM_ARCH_MSM_VMALLOC_H -#define VMALLOC_END 0xd0000000 +#define VMALLOC_END 0xd0000000UL #endif From 4916a1083290edfb6cc53aa134f00597447de1ce Mon Sep 17 00:00:00 2001 From: Pavankumar Kondeti Date: Tue, 9 Nov 2010 15:41:29 +0530 Subject: [PATCH 05/33] msm: io: Export __msm_ioremap This is required for modules to use ioremap() Signed-off-by: Pavankumar Kondeti Signed-off-by: Daniel Walker --- arch/arm/mach-msm/io.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index d36b61074146..f912d7bf1889 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c @@ -163,3 +163,4 @@ __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) return __arm_ioremap_caller(phys_addr, size, mtype, __builtin_return_address(0)); } +EXPORT_SYMBOL(__msm_ioremap); From 0cc2fc1f2f5f1fcf6699b43d73ca3e753ef63582 Mon Sep 17 00:00:00 2001 From: Gregory Bean Date: Wed, 24 Nov 2010 11:53:51 -0800 Subject: [PATCH 06/33] msm: gpio: Add v2 gpio support to MSM SoCs. Beginning with the MSM8x60, the hardware block responsible for gpio support changes. Provide gpiolib support for the new v2 architecture. Cc: Baruch Siach Cc: Pavan Kondeti Signed-off-by: Gregory Bean Signed-off-by: Daniel Walker --- arch/arm/mach-msm/Makefile | 4 +- arch/arm/mach-msm/gpio-v2.c | 163 ++++++++++++++++++++++++++++++++++++ 2 files changed, 166 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-msm/gpio-v2.c diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index b5a7b07a44f5..4a1a7ea97c24 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -28,6 +28,8 @@ obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o -ifndef CONFIG_MSM_V2_TLMM +ifdef CONFIG_MSM_V2_TLMM +obj-y += gpio-v2.o +else obj-y += gpio.o endif diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c new file mode 100644 index 000000000000..d907af68c8ee --- /dev/null +++ b/arch/arm/mach-msm/gpio-v2.c @@ -0,0 +1,163 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include "gpiomux.h" + +/* Bits of interest in the GPIO_IN_OUT register. + */ +enum { + GPIO_IN_BIT = 0, + GPIO_OUT_BIT = 1 +}; + +/* Bits of interest in the GPIO_CFG register. + */ +enum { + GPIO_OE_BIT = 9, +}; + +#define GPIO_CONFIG(gpio) (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio))) +#define GPIO_IN_OUT(gpio) (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio))) + +static DEFINE_SPINLOCK(tlmm_lock); + +static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN_BIT); +} + +static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int val) +{ + writel(val ? BIT(GPIO_OUT_BIT) : 0, GPIO_IN_OUT(offset)); +} + +static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + unsigned long irq_flags; + + spin_lock_irqsave(&tlmm_lock, irq_flags); + writel(readl(GPIO_CONFIG(offset)) & ~BIT(GPIO_OE_BIT), + GPIO_CONFIG(offset)); + spin_unlock_irqrestore(&tlmm_lock, irq_flags); + return 0; +} + +static int msm_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, + int val) +{ + unsigned long irq_flags; + + spin_lock_irqsave(&tlmm_lock, irq_flags); + msm_gpio_set(chip, offset, val); + writel(readl(GPIO_CONFIG(offset)) | BIT(GPIO_OE_BIT), + GPIO_CONFIG(offset)); + spin_unlock_irqrestore(&tlmm_lock, irq_flags); + return 0; +} + +static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return msm_gpiomux_get(chip->base + offset); +} + +static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + msm_gpiomux_put(chip->base + offset); +} + +static struct gpio_chip msm_gpio = { + .base = 0, + .ngpio = NR_GPIO_IRQS, + .direction_input = msm_gpio_direction_input, + .direction_output = msm_gpio_direction_output, + .get = msm_gpio_get, + .set = msm_gpio_set, + .request = msm_gpio_request, + .free = msm_gpio_free, +}; + +static int __devinit msm_gpio_probe(struct platform_device *dev) +{ + int ret; + + msm_gpio.label = dev->name; + ret = gpiochip_add(&msm_gpio); + + return ret; +} + +static int __devexit msm_gpio_remove(struct platform_device *dev) +{ + int ret = gpiochip_remove(&msm_gpio); + + if (ret < 0) + return ret; + + set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); + + return 0; +} + +static struct platform_driver msm_gpio_driver = { + .probe = msm_gpio_probe, + .remove = __devexit_p(msm_gpio_remove), + .driver = { + .name = "msmgpio", + .owner = THIS_MODULE, + }, +}; + +static struct platform_device msm_device_gpio = { + .name = "msmgpio", + .id = -1, +}; + +static int __init msm_gpio_init(void) +{ + int rc; + + rc = platform_driver_register(&msm_gpio_driver); + if (!rc) { + rc = platform_device_register(&msm_device_gpio); + if (rc) + platform_driver_unregister(&msm_gpio_driver); + } + + return rc; +} + +static void __exit msm_gpio_exit(void) +{ + platform_device_unregister(&msm_device_gpio); + platform_driver_unregister(&msm_gpio_driver); +} + +postcore_initcall(msm_gpio_init); +module_exit(msm_gpio_exit); + +MODULE_AUTHOR("Gregory Bean "); +MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:msmgpio"); From 70cc2c00d7471f21120befeb7fc107c856e3985b Mon Sep 17 00:00:00 2001 From: Gregory Bean Date: Wed, 24 Nov 2010 11:53:52 -0800 Subject: [PATCH 07/33] msm: gpio: Add irq support to v2 gpiolib. Complete the MSM v2 gpio subsystem by adding irq_chip. Signed-off-by: Gregory Bean Signed-off-by: Daniel Walker --- arch/arm/mach-msm/gpio-v2.c | 309 +++++++++++++++++++++++++++++++++--- 1 file changed, 286 insertions(+), 23 deletions(-) diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c index d907af68c8ee..0de19ec74e34 100644 --- a/arch/arm/mach-msm/gpio-v2.c +++ b/arch/arm/mach-msm/gpio-v2.c @@ -15,7 +15,13 @@ * 02110-1301, USA. * */ +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include #include +#include +#include #include #include #include @@ -27,29 +33,103 @@ /* Bits of interest in the GPIO_IN_OUT register. */ enum { - GPIO_IN_BIT = 0, - GPIO_OUT_BIT = 1 + GPIO_IN = 0, + GPIO_OUT = 1 +}; + +/* Bits of interest in the GPIO_INTR_STATUS register. + */ +enum { + INTR_STATUS = 0, }; /* Bits of interest in the GPIO_CFG register. */ enum { - GPIO_OE_BIT = 9, + GPIO_OE = 9, }; +/* Bits of interest in the GPIO_INTR_CFG register. + * When a GPIO triggers, two separate decisions are made, controlled + * by two separate flags. + * + * - First, INTR_RAW_STATUS_EN controls whether or not the GPIO_INTR_STATUS + * register for that GPIO will be updated to reflect the triggering of that + * gpio. If this bit is 0, this register will not be updated. + * - Second, INTR_ENABLE controls whether an interrupt is triggered. + * + * If INTR_ENABLE is set and INTR_RAW_STATUS_EN is NOT set, an interrupt + * can be triggered but the status register will not reflect it. + */ +enum { + INTR_ENABLE = 0, + INTR_POL_CTL = 1, + INTR_DECT_CTL = 2, + INTR_RAW_STATUS_EN = 3, +}; + +/* Codes of interest in GPIO_INTR_CFG_SU. + */ +enum { + TARGET_PROC_SCORPION = 4, + TARGET_PROC_NONE = 7, +}; + + +#define GPIO_INTR_CFG_SU(gpio) (MSM_TLMM_BASE + 0x0400 + (0x04 * (gpio))) #define GPIO_CONFIG(gpio) (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio))) #define GPIO_IN_OUT(gpio) (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio))) +#define GPIO_INTR_CFG(gpio) (MSM_TLMM_BASE + 0x1008 + (0x10 * (gpio))) +#define GPIO_INTR_STATUS(gpio) (MSM_TLMM_BASE + 0x100c + (0x10 * (gpio))) + +/** + * struct msm_gpio_dev: the MSM8660 SoC GPIO device structure + * + * @enabled_irqs: a bitmap used to optimize the summary-irq handler. By + * keeping track of which gpios are unmasked as irq sources, we avoid + * having to do readl calls on hundreds of iomapped registers each time + * the summary interrupt fires in order to locate the active interrupts. + * + * @wake_irqs: a bitmap for tracking which interrupt lines are enabled + * as wakeup sources. When the device is suspended, interrupts which are + * not wakeup sources are disabled. + * + * @dual_edge_irqs: a bitmap used to track which irqs are configured + * as dual-edge, as this is not supported by the hardware and requires + * some special handling in the driver. + */ +struct msm_gpio_dev { + struct gpio_chip gpio_chip; + DECLARE_BITMAP(enabled_irqs, NR_GPIO_IRQS); + DECLARE_BITMAP(wake_irqs, NR_GPIO_IRQS); + DECLARE_BITMAP(dual_edge_irqs, NR_GPIO_IRQS); +}; static DEFINE_SPINLOCK(tlmm_lock); +static inline struct msm_gpio_dev *to_msm_gpio_dev(struct gpio_chip *chip) +{ + return container_of(chip, struct msm_gpio_dev, gpio_chip); +} + +static inline void set_gpio_bits(unsigned n, void __iomem *reg) +{ + writel(readl(reg) | n, reg); +} + +static inline void clear_gpio_bits(unsigned n, void __iomem *reg) +{ + writel(readl(reg) & ~n, reg); +} + static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) { - return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN_BIT); + return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN); } static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int val) { - writel(val ? BIT(GPIO_OUT_BIT) : 0, GPIO_IN_OUT(offset)); + writel(val ? BIT(GPIO_OUT) : 0, GPIO_IN_OUT(offset)); } static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) @@ -57,8 +137,7 @@ static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) unsigned long irq_flags; spin_lock_irqsave(&tlmm_lock, irq_flags); - writel(readl(GPIO_CONFIG(offset)) & ~BIT(GPIO_OE_BIT), - GPIO_CONFIG(offset)); + clear_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset)); spin_unlock_irqrestore(&tlmm_lock, irq_flags); return 0; } @@ -71,8 +150,7 @@ static int msm_gpio_direction_output(struct gpio_chip *chip, spin_lock_irqsave(&tlmm_lock, irq_flags); msm_gpio_set(chip, offset, val); - writel(readl(GPIO_CONFIG(offset)) | BIT(GPIO_OE_BIT), - GPIO_CONFIG(offset)); + set_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset)); spin_unlock_irqrestore(&tlmm_lock, irq_flags); return 0; } @@ -87,30 +165,215 @@ static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) msm_gpiomux_put(chip->base + offset); } -static struct gpio_chip msm_gpio = { - .base = 0, - .ngpio = NR_GPIO_IRQS, - .direction_input = msm_gpio_direction_input, - .direction_output = msm_gpio_direction_output, - .get = msm_gpio_get, - .set = msm_gpio_set, - .request = msm_gpio_request, - .free = msm_gpio_free, +static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + return MSM_GPIO_TO_INT(chip->base + offset); +} + +static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq) +{ + return irq - MSM_GPIO_TO_INT(chip->base); +} + +static struct msm_gpio_dev msm_gpio = { + .gpio_chip = { + .base = 0, + .ngpio = NR_GPIO_IRQS, + .direction_input = msm_gpio_direction_input, + .direction_output = msm_gpio_direction_output, + .get = msm_gpio_get, + .set = msm_gpio_set, + .to_irq = msm_gpio_to_irq, + .request = msm_gpio_request, + .free = msm_gpio_free, + }, +}; + +/* For dual-edge interrupts in software, since the hardware has no + * such support: + * + * At appropriate moments, this function may be called to flip the polarity + * settings of both-edge irq lines to try and catch the next edge. + * + * The attempt is considered successful if: + * - the status bit goes high, indicating that an edge was caught, or + * - the input value of the gpio doesn't change during the attempt. + * If the value changes twice during the process, that would cause the first + * test to fail but would force the second, as two opposite + * transitions would cause a detection no matter the polarity setting. + * + * The do-loop tries to sledge-hammer closed the timing hole between + * the initial value-read and the polarity-write - if the line value changes + * during that window, an interrupt is lost, the new polarity setting is + * incorrect, and the first success test will fail, causing a retry. + * + * Algorithm comes from Google's msmgpio driver, see mach-msm/gpio.c. + */ +static void msm_gpio_update_dual_edge_pos(unsigned gpio) +{ + int loop_limit = 100; + unsigned val, val2, intstat; + + do { + val = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN); + if (val) + clear_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio)); + else + set_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio)); + val2 = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN); + intstat = readl(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS); + if (intstat || val == val2) + return; + } while (loop_limit-- > 0); + pr_err("dual-edge irq failed to stabilize, " + "interrupts dropped. %#08x != %#08x\n", + val, val2); +} + +static void msm_gpio_irq_ack(unsigned int irq) +{ + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + + writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio)); + if (test_bit(gpio, msm_gpio.dual_edge_irqs)) + msm_gpio_update_dual_edge_pos(gpio); +} + +static void msm_gpio_irq_mask(unsigned int irq) +{ + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + unsigned long irq_flags; + + spin_lock_irqsave(&tlmm_lock, irq_flags); + writel(TARGET_PROC_NONE, GPIO_INTR_CFG_SU(gpio)); + clear_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio)); + __clear_bit(gpio, msm_gpio.enabled_irqs); + spin_unlock_irqrestore(&tlmm_lock, irq_flags); +} + +static void msm_gpio_irq_unmask(unsigned int irq) +{ + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + unsigned long irq_flags; + + spin_lock_irqsave(&tlmm_lock, irq_flags); + __set_bit(gpio, msm_gpio.enabled_irqs); + set_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio)); + writel(TARGET_PROC_SCORPION, GPIO_INTR_CFG_SU(gpio)); + spin_unlock_irqrestore(&tlmm_lock, irq_flags); +} + +static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) +{ + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + unsigned long irq_flags; + uint32_t bits; + + spin_lock_irqsave(&tlmm_lock, irq_flags); + + bits = readl(GPIO_INTR_CFG(gpio)); + + if (flow_type & IRQ_TYPE_EDGE_BOTH) { + bits |= BIT(INTR_DECT_CTL); + irq_desc[irq].handle_irq = handle_edge_irq; + if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) + __set_bit(gpio, msm_gpio.dual_edge_irqs); + else + __clear_bit(gpio, msm_gpio.dual_edge_irqs); + } else { + bits &= ~BIT(INTR_DECT_CTL); + irq_desc[irq].handle_irq = handle_level_irq; + __clear_bit(gpio, msm_gpio.dual_edge_irqs); + } + + if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) + bits |= BIT(INTR_POL_CTL); + else + bits &= ~BIT(INTR_POL_CTL); + + writel(bits, GPIO_INTR_CFG(gpio)); + + if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) + msm_gpio_update_dual_edge_pos(gpio); + + spin_unlock_irqrestore(&tlmm_lock, irq_flags); + + return 0; +} + +/* + * When the summary IRQ is raised, any number of GPIO lines may be high. + * It is the job of the summary handler to find all those GPIO lines + * which have been set as summary IRQ lines and which are triggered, + * and to call their interrupt handlers. + */ +static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + unsigned long i; + + for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS); + i < NR_GPIO_IRQS; + i = find_next_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS, i + 1)) { + if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS)) + generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip, + i)); + } + desc->chip->ack(irq); +} + +static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) +{ + int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); + + if (on) { + if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) + set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); + set_bit(gpio, msm_gpio.wake_irqs); + } else { + clear_bit(gpio, msm_gpio.wake_irqs); + if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) + set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); + } + + return 0; +} + +static struct irq_chip msm_gpio_irq_chip = { + .name = "msmgpio", + .mask = msm_gpio_irq_mask, + .unmask = msm_gpio_irq_unmask, + .ack = msm_gpio_irq_ack, + .set_type = msm_gpio_irq_set_type, + .set_wake = msm_gpio_irq_set_wake, }; static int __devinit msm_gpio_probe(struct platform_device *dev) { - int ret; + int i, irq, ret; - msm_gpio.label = dev->name; - ret = gpiochip_add(&msm_gpio); + bitmap_zero(msm_gpio.enabled_irqs, NR_GPIO_IRQS); + bitmap_zero(msm_gpio.wake_irqs, NR_GPIO_IRQS); + bitmap_zero(msm_gpio.dual_edge_irqs, NR_GPIO_IRQS); + msm_gpio.gpio_chip.label = dev->name; + ret = gpiochip_add(&msm_gpio.gpio_chip); + if (ret < 0) + return ret; - return ret; + for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) { + irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i); + set_irq_chip(irq, &msm_gpio_irq_chip); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } + + set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ, + msm_summary_irq_handler); + return 0; } static int __devexit msm_gpio_remove(struct platform_device *dev) { - int ret = gpiochip_remove(&msm_gpio); + int ret = gpiochip_remove(&msm_gpio.gpio_chip); if (ret < 0) return ret; From 23513c3b39207c569da2c8afdced62ec43b4a272 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:47 -0800 Subject: [PATCH 08/33] msm: iommu: Increase maximum MID size to 5 bits On msm8x60, the MID field on the AXI connection to the IOMMU can be up to five bits wide. Thus, allow the IOMMU context platform data to map up to 32 MIDs. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/include/mach/iommu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h index 218ef5732a24..17fc79fc8bc2 100644 --- a/arch/arm/mach-msm/include/mach/iommu.h +++ b/arch/arm/mach-msm/include/mach/iommu.h @@ -26,7 +26,7 @@ * be present. These mappings are typically determined at design time and are * not expected to change at run time. */ -#define MAX_NUM_MIDS 16 +#define MAX_NUM_MIDS 32 /** * struct msm_iommu_dev - a single IOMMU hardware instance From c4bd2eebee37b885b47ec48961923b671148703f Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:48 -0800 Subject: [PATCH 09/33] msm: iomap: Addresses and IRQs for 2nd GFX core IOMMU Add register addresses and IRQ numbers for the IOMMU used for the second 2D graphics core. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/include/mach/irqs-8x60.h | 7 ++++++- arch/arm/mach-msm/include/mach/msm_iomap-8x60.h | 3 +++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-msm/include/mach/irqs-8x60.h b/arch/arm/mach-msm/include/mach/irqs-8x60.h index 36074cfc9ad2..f65841c74c0b 100644 --- a/arch/arm/mach-msm/include/mach/irqs-8x60.h +++ b/arch/arm/mach-msm/include/mach/irqs-8x60.h @@ -237,7 +237,12 @@ #define GSBI11_QUP_IRQ (GIC_SPI_START + 194) #define INT_UART12DM_IRQ (GIC_SPI_START + 195) #define GSBI12_QUP_IRQ (GIC_SPI_START + 196) -/*SPI 197 to 216 arent used in 8x60*/ + +/*SPI 197 to 209 arent used in 8x60*/ +#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210) +#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211) + +/*SPI 212 to 216 arent used in 8x60*/ #define SMPSS_SPARE_1 (GIC_SPI_START + 217) #define SMPSS_SPARE_2 (GIC_SPI_START + 218) #define SMPSS_SPARE_3 (GIC_SPI_START + 219) diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index 45bab50e3ee6..7c43a9bff1a9 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h @@ -98,4 +98,7 @@ #define MSM_IOMMU_GFX2D0_PHYS 0x07D00000 #define MSM_IOMMU_GFX2D0_SIZE SZ_1M +#define MSM_IOMMU_GFX2D1_PHYS 0x07E00000 +#define MSM_IOMMU_GFX2D1_SIZE SZ_1M + #endif From 12943325cda3be10819e047cd8b5032a4fef6080 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:49 -0800 Subject: [PATCH 10/33] msm: iommu: Use more consistent naming in platform data Rename all the IOMMU platform devices so that the names are more consistent with the rest of the codebase. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/devices-msm8x60-iommu.c | 136 +++++++++++----------- 1 file changed, 68 insertions(+), 68 deletions(-) diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-msm8x60-iommu.c index 89b9d4437e92..9e657e0ee181 100644 --- a/arch/arm/mach-msm/devices-msm8x60-iommu.c +++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c @@ -259,55 +259,55 @@ static struct platform_device msm_root_iommu_dev = { .id = -1, }; -static struct msm_iommu_dev jpegd_smmu = { +static struct msm_iommu_dev jpegd_iommu = { .name = "jpegd", .clk_rate = -1 }; -static struct msm_iommu_dev vpe_smmu = { +static struct msm_iommu_dev vpe_iommu = { .name = "vpe" }; -static struct msm_iommu_dev mdp0_smmu = { +static struct msm_iommu_dev mdp0_iommu = { .name = "mdp0" }; -static struct msm_iommu_dev mdp1_smmu = { +static struct msm_iommu_dev mdp1_iommu = { .name = "mdp1" }; -static struct msm_iommu_dev rot_smmu = { +static struct msm_iommu_dev rot_iommu = { .name = "rot" }; -static struct msm_iommu_dev ijpeg_smmu = { +static struct msm_iommu_dev ijpeg_iommu = { .name = "ijpeg" }; -static struct msm_iommu_dev vfe_smmu = { +static struct msm_iommu_dev vfe_iommu = { .name = "vfe", .clk_rate = -1 }; -static struct msm_iommu_dev vcodec_a_smmu = { +static struct msm_iommu_dev vcodec_a_iommu = { .name = "vcodec_a" }; -static struct msm_iommu_dev vcodec_b_smmu = { +static struct msm_iommu_dev vcodec_b_iommu = { .name = "vcodec_b" }; -static struct msm_iommu_dev gfx3d_smmu = { +static struct msm_iommu_dev gfx3d_iommu = { .name = "gfx3d", .clk_rate = 27000000 }; -static struct msm_iommu_dev gfx2d0_smmu = { +static struct msm_iommu_dev gfx2d0_iommu = { .name = "gfx2d0", .clk_rate = 27000000 }; -static struct platform_device msm_device_smmu_jpegd = { +static struct platform_device msm_device_iommu_jpegd = { .name = "msm_iommu", .id = 0, .dev = { @@ -317,7 +317,7 @@ static struct platform_device msm_device_smmu_jpegd = { .resource = msm_iommu_jpegd_resources, }; -static struct platform_device msm_device_smmu_vpe = { +static struct platform_device msm_device_iommu_vpe = { .name = "msm_iommu", .id = 1, .dev = { @@ -327,7 +327,7 @@ static struct platform_device msm_device_smmu_vpe = { .resource = msm_iommu_vpe_resources, }; -static struct platform_device msm_device_smmu_mdp0 = { +static struct platform_device msm_device_iommu_mdp0 = { .name = "msm_iommu", .id = 2, .dev = { @@ -337,7 +337,7 @@ static struct platform_device msm_device_smmu_mdp0 = { .resource = msm_iommu_mdp0_resources, }; -static struct platform_device msm_device_smmu_mdp1 = { +static struct platform_device msm_device_iommu_mdp1 = { .name = "msm_iommu", .id = 3, .dev = { @@ -347,7 +347,7 @@ static struct platform_device msm_device_smmu_mdp1 = { .resource = msm_iommu_mdp1_resources, }; -static struct platform_device msm_device_smmu_rot = { +static struct platform_device msm_device_iommu_rot = { .name = "msm_iommu", .id = 4, .dev = { @@ -357,7 +357,7 @@ static struct platform_device msm_device_smmu_rot = { .resource = msm_iommu_rot_resources, }; -static struct platform_device msm_device_smmu_ijpeg = { +static struct platform_device msm_device_iommu_ijpeg = { .name = "msm_iommu", .id = 5, .dev = { @@ -367,7 +367,7 @@ static struct platform_device msm_device_smmu_ijpeg = { .resource = msm_iommu_ijpeg_resources, }; -static struct platform_device msm_device_smmu_vfe = { +static struct platform_device msm_device_iommu_vfe = { .name = "msm_iommu", .id = 6, .dev = { @@ -377,7 +377,7 @@ static struct platform_device msm_device_smmu_vfe = { .resource = msm_iommu_vfe_resources, }; -static struct platform_device msm_device_smmu_vcodec_a = { +static struct platform_device msm_device_iommu_vcodec_a = { .name = "msm_iommu", .id = 7, .dev = { @@ -387,7 +387,7 @@ static struct platform_device msm_device_smmu_vcodec_a = { .resource = msm_iommu_vcodec_a_resources, }; -static struct platform_device msm_device_smmu_vcodec_b = { +static struct platform_device msm_device_iommu_vcodec_b = { .name = "msm_iommu", .id = 8, .dev = { @@ -397,7 +397,7 @@ static struct platform_device msm_device_smmu_vcodec_b = { .resource = msm_iommu_vcodec_b_resources, }; -static struct platform_device msm_device_smmu_gfx3d = { +static struct platform_device msm_device_iommu_gfx3d = { .name = "msm_iommu", .id = 9, .dev = { @@ -407,7 +407,7 @@ static struct platform_device msm_device_smmu_gfx3d = { .resource = msm_iommu_gfx3d_resources, }; -static struct platform_device msm_device_smmu_gfx2d0 = { +static struct platform_device msm_device_iommu_gfx2d0 = { .name = "msm_iommu", .id = 10, .dev = { @@ -553,7 +553,7 @@ static struct platform_device msm_device_jpegd_src_ctx = { .name = "msm_iommu_ctx", .id = 0, .dev = { - .parent = &msm_device_smmu_jpegd.dev, + .parent = &msm_device_iommu_jpegd.dev, }, }; @@ -561,7 +561,7 @@ static struct platform_device msm_device_jpegd_dst_ctx = { .name = "msm_iommu_ctx", .id = 1, .dev = { - .parent = &msm_device_smmu_jpegd.dev, + .parent = &msm_device_iommu_jpegd.dev, }, }; @@ -569,7 +569,7 @@ static struct platform_device msm_device_vpe_src_ctx = { .name = "msm_iommu_ctx", .id = 2, .dev = { - .parent = &msm_device_smmu_vpe.dev, + .parent = &msm_device_iommu_vpe.dev, }, }; @@ -577,7 +577,7 @@ static struct platform_device msm_device_vpe_dst_ctx = { .name = "msm_iommu_ctx", .id = 3, .dev = { - .parent = &msm_device_smmu_vpe.dev, + .parent = &msm_device_iommu_vpe.dev, }, }; @@ -585,7 +585,7 @@ static struct platform_device msm_device_mdp_vg1_ctx = { .name = "msm_iommu_ctx", .id = 4, .dev = { - .parent = &msm_device_smmu_mdp0.dev, + .parent = &msm_device_iommu_mdp0.dev, }, }; @@ -593,7 +593,7 @@ static struct platform_device msm_device_mdp_rgb1_ctx = { .name = "msm_iommu_ctx", .id = 5, .dev = { - .parent = &msm_device_smmu_mdp0.dev, + .parent = &msm_device_iommu_mdp0.dev, }, }; @@ -601,7 +601,7 @@ static struct platform_device msm_device_mdp_vg2_ctx = { .name = "msm_iommu_ctx", .id = 6, .dev = { - .parent = &msm_device_smmu_mdp1.dev, + .parent = &msm_device_iommu_mdp1.dev, }, }; @@ -609,7 +609,7 @@ static struct platform_device msm_device_mdp_rgb2_ctx = { .name = "msm_iommu_ctx", .id = 7, .dev = { - .parent = &msm_device_smmu_mdp1.dev, + .parent = &msm_device_iommu_mdp1.dev, }, }; @@ -617,7 +617,7 @@ static struct platform_device msm_device_rot_src_ctx = { .name = "msm_iommu_ctx", .id = 8, .dev = { - .parent = &msm_device_smmu_rot.dev, + .parent = &msm_device_iommu_rot.dev, }, }; @@ -625,7 +625,7 @@ static struct platform_device msm_device_rot_dst_ctx = { .name = "msm_iommu_ctx", .id = 9, .dev = { - .parent = &msm_device_smmu_rot.dev, + .parent = &msm_device_iommu_rot.dev, }, }; @@ -633,7 +633,7 @@ static struct platform_device msm_device_ijpeg_src_ctx = { .name = "msm_iommu_ctx", .id = 10, .dev = { - .parent = &msm_device_smmu_ijpeg.dev, + .parent = &msm_device_iommu_ijpeg.dev, }, }; @@ -641,7 +641,7 @@ static struct platform_device msm_device_ijpeg_dst_ctx = { .name = "msm_iommu_ctx", .id = 11, .dev = { - .parent = &msm_device_smmu_ijpeg.dev, + .parent = &msm_device_iommu_ijpeg.dev, }, }; @@ -649,7 +649,7 @@ static struct platform_device msm_device_vfe_imgwr_ctx = { .name = "msm_iommu_ctx", .id = 12, .dev = { - .parent = &msm_device_smmu_vfe.dev, + .parent = &msm_device_iommu_vfe.dev, }, }; @@ -657,7 +657,7 @@ static struct platform_device msm_device_vfe_misc_ctx = { .name = "msm_iommu_ctx", .id = 13, .dev = { - .parent = &msm_device_smmu_vfe.dev, + .parent = &msm_device_iommu_vfe.dev, }, }; @@ -665,7 +665,7 @@ static struct platform_device msm_device_vcodec_a_stream_ctx = { .name = "msm_iommu_ctx", .id = 14, .dev = { - .parent = &msm_device_smmu_vcodec_a.dev, + .parent = &msm_device_iommu_vcodec_a.dev, }, }; @@ -673,7 +673,7 @@ static struct platform_device msm_device_vcodec_a_mm1_ctx = { .name = "msm_iommu_ctx", .id = 15, .dev = { - .parent = &msm_device_smmu_vcodec_a.dev, + .parent = &msm_device_iommu_vcodec_a.dev, }, }; @@ -681,7 +681,7 @@ static struct platform_device msm_device_vcodec_b_mm2_ctx = { .name = "msm_iommu_ctx", .id = 16, .dev = { - .parent = &msm_device_smmu_vcodec_b.dev, + .parent = &msm_device_iommu_vcodec_b.dev, }, }; @@ -689,7 +689,7 @@ static struct platform_device msm_device_gfx3d_rbpa_ctx = { .name = "msm_iommu_ctx", .id = 17, .dev = { - .parent = &msm_device_smmu_gfx3d.dev, + .parent = &msm_device_iommu_gfx3d.dev, }, }; @@ -697,7 +697,7 @@ static struct platform_device msm_device_gfx3d_cpvgttc_ctx = { .name = "msm_iommu_ctx", .id = 18, .dev = { - .parent = &msm_device_smmu_gfx3d.dev, + .parent = &msm_device_iommu_gfx3d.dev, }, }; @@ -705,7 +705,7 @@ static struct platform_device msm_device_gfx3d_smmu_ctx = { .name = "msm_iommu_ctx", .id = 19, .dev = { - .parent = &msm_device_smmu_gfx3d.dev, + .parent = &msm_device_iommu_gfx3d.dev, }, }; @@ -713,7 +713,7 @@ static struct platform_device msm_device_gfx2d0_pixv1_ctx = { .name = "msm_iommu_ctx", .id = 20, .dev = { - .parent = &msm_device_smmu_gfx2d0.dev, + .parent = &msm_device_iommu_gfx2d0.dev, }, }; @@ -721,36 +721,36 @@ static struct platform_device msm_device_gfx2d0_texv3_ctx = { .name = "msm_iommu_ctx", .id = 21, .dev = { - .parent = &msm_device_smmu_gfx2d0.dev, + .parent = &msm_device_iommu_gfx2d0.dev, }, }; static struct platform_device *msm_iommu_devs[] = { - &msm_device_smmu_jpegd, - &msm_device_smmu_vpe, - &msm_device_smmu_mdp0, - &msm_device_smmu_mdp1, - &msm_device_smmu_rot, - &msm_device_smmu_ijpeg, - &msm_device_smmu_vfe, - &msm_device_smmu_vcodec_a, - &msm_device_smmu_vcodec_b, - &msm_device_smmu_gfx3d, - &msm_device_smmu_gfx2d0, + &msm_device_iommu_jpegd, + &msm_device_iommu_vpe, + &msm_device_iommu_mdp0, + &msm_device_iommu_mdp1, + &msm_device_iommu_rot, + &msm_device_iommu_ijpeg, + &msm_device_iommu_vfe, + &msm_device_iommu_vcodec_a, + &msm_device_iommu_vcodec_b, + &msm_device_iommu_gfx3d, + &msm_device_iommu_gfx2d0, }; static struct msm_iommu_dev *msm_iommu_data[] = { - &jpegd_smmu, - &vpe_smmu, - &mdp0_smmu, - &mdp1_smmu, - &rot_smmu, - &ijpeg_smmu, - &vfe_smmu, - &vcodec_a_smmu, - &vcodec_b_smmu, - &gfx3d_smmu, - &gfx2d0_smmu, + &jpegd_iommu, + &vpe_iommu, + &mdp0_iommu, + &mdp1_iommu, + &rot_iommu, + &ijpeg_iommu, + &vfe_iommu, + &vcodec_a_iommu, + &vcodec_b_iommu, + &gfx3d_iommu, + &gfx2d0_iommu, }; static struct platform_device *msm_iommu_ctx_devs[] = { @@ -826,7 +826,7 @@ static int msm8x60_iommu_init(void) ret = platform_device_register(msm_iommu_devs[i]); if (ret != 0) { - pr_err("platform_device_register smmu failed, " + pr_err("platform_device_register iommu failed, " "i = %d\n", i); goto failure_unwind; } @@ -837,7 +837,7 @@ static int msm8x60_iommu_init(void) msm_iommu_ctx_data[i], sizeof(*msm_iommu_ctx_devs[i])); if (ret != 0) { - pr_err("platform_device_add_data smmu failed, " + pr_err("platform_device_add_data iommu failed, " "i = %d\n", i); goto failure_unwind2; } From a5fcd5f59a2658a579533d6774e871aea7ab5e92 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:50 -0800 Subject: [PATCH 11/33] msm: iommu: Revise GFX3D IOMMU contexts and M2V mappings Based on recommendations from chip designers, optimize the Machine ID to translation context mappings for the 3D core's IOMMU. Remove the the "gfx3d_smmu" context device, as it is no longer needed under the new mapping scheme. Signed-off-by: Stepan Moskovchenko [dwalker@codeaurora.org: updated commit text] Signed-off-by: Daniel Walker --- arch/arm/mach-msm/devices-msm8x60-iommu.c | 45 ++++++++--------------- 1 file changed, 15 insertions(+), 30 deletions(-) diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-msm8x60-iommu.c index 9e657e0ee181..22d0c7cb71f6 100644 --- a/arch/arm/mach-msm/devices-msm8x60-iommu.c +++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c @@ -519,22 +519,17 @@ static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = { .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} }; -static struct msm_iommu_ctx_dev gfx3d_rbpa_ctx = { - .name = "gfx3d_rbpa", +static struct msm_iommu_ctx_dev gfx3d_user_ctx = { + .name = "gfx3d_user", .num = 0, - .mids = {-1} + .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} }; -static struct msm_iommu_ctx_dev gfx3d_cpvgttc_ctx = { - .name = "gfx3d_cpvgttc", +static struct msm_iommu_ctx_dev gfx3d_priv_ctx = { + .name = "gfx3d_priv", .num = 1, - .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} -}; - -static struct msm_iommu_ctx_dev gfx3d_smmu_ctx = { - .name = "gfx3d_smmu", - .num = 2, - .mids = {8, 9, 10, 11, 12, -1} + .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, + 31, -1} }; static struct msm_iommu_ctx_dev gfx2d0_pixv1_ctx = { @@ -685,7 +680,7 @@ static struct platform_device msm_device_vcodec_b_mm2_ctx = { }, }; -static struct platform_device msm_device_gfx3d_rbpa_ctx = { +static struct platform_device msm_device_gfx3d_user_ctx = { .name = "msm_iommu_ctx", .id = 17, .dev = { @@ -693,7 +688,7 @@ static struct platform_device msm_device_gfx3d_rbpa_ctx = { }, }; -static struct platform_device msm_device_gfx3d_cpvgttc_ctx = { +static struct platform_device msm_device_gfx3d_priv_ctx = { .name = "msm_iommu_ctx", .id = 18, .dev = { @@ -701,17 +696,9 @@ static struct platform_device msm_device_gfx3d_cpvgttc_ctx = { }, }; -static struct platform_device msm_device_gfx3d_smmu_ctx = { - .name = "msm_iommu_ctx", - .id = 19, - .dev = { - .parent = &msm_device_iommu_gfx3d.dev, - }, -}; - static struct platform_device msm_device_gfx2d0_pixv1_ctx = { .name = "msm_iommu_ctx", - .id = 20, + .id = 19, .dev = { .parent = &msm_device_iommu_gfx2d0.dev, }, @@ -719,7 +706,7 @@ static struct platform_device msm_device_gfx2d0_pixv1_ctx = { static struct platform_device msm_device_gfx2d0_texv3_ctx = { .name = "msm_iommu_ctx", - .id = 21, + .id = 20, .dev = { .parent = &msm_device_iommu_gfx2d0.dev, }, @@ -771,9 +758,8 @@ static struct platform_device *msm_iommu_ctx_devs[] = { &msm_device_vcodec_a_stream_ctx, &msm_device_vcodec_a_mm1_ctx, &msm_device_vcodec_b_mm2_ctx, - &msm_device_gfx3d_rbpa_ctx, - &msm_device_gfx3d_cpvgttc_ctx, - &msm_device_gfx3d_smmu_ctx, + &msm_device_gfx3d_user_ctx, + &msm_device_gfx3d_priv_ctx, &msm_device_gfx2d0_pixv1_ctx, &msm_device_gfx2d0_texv3_ctx, }; @@ -796,9 +782,8 @@ static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { &vcodec_a_stream_ctx, &vcodec_a_mm1_ctx, &vcodec_b_mm2_ctx, - &gfx3d_rbpa_ctx, - &gfx3d_cpvgttc_ctx, - &gfx3d_smmu_ctx, + &gfx3d_user_ctx, + &gfx3d_priv_ctx, &gfx2d0_pixv1_ctx, &gfx2d0_texv3_ctx, }; From ff25ff842ea6afd58ccc2e3f386ee5ac540b6a63 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:51 -0800 Subject: [PATCH 12/33] msm: iommu: Revise GFX2D0 IOMMU contexts and M2V mappings Based on recommendations from chip designers, optimize the Machine ID to translation context mappings for the first 2D core's IOMMU. Remove the "gfx2d0_texv3_smmu" context, as it is no longer needed under the new mapping scheme. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/devices-msm8x60-iommu.c | 28 +++++------------------ 1 file changed, 6 insertions(+), 22 deletions(-) diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-msm8x60-iommu.c index 22d0c7cb71f6..8cccb2680542 100644 --- a/arch/arm/mach-msm/devices-msm8x60-iommu.c +++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c @@ -532,16 +532,10 @@ static struct msm_iommu_ctx_dev gfx3d_priv_ctx = { 31, -1} }; -static struct msm_iommu_ctx_dev gfx2d0_pixv1_ctx = { - .name = "gfx2d0_pixv1_smmu", +static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = { + .name = "gfx2d0_2d0", .num = 0, - .mids = {0, 3, 4, -1} -}; - -static struct msm_iommu_ctx_dev gfx2d0_texv3_ctx = { - .name = "gfx2d0_texv3_smmu", - .num = 1, - .mids = {1, 6, 7, -1} + .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} }; static struct platform_device msm_device_jpegd_src_ctx = { @@ -696,7 +690,7 @@ static struct platform_device msm_device_gfx3d_priv_ctx = { }, }; -static struct platform_device msm_device_gfx2d0_pixv1_ctx = { +static struct platform_device msm_device_gfx2d0_2d0_ctx = { .name = "msm_iommu_ctx", .id = 19, .dev = { @@ -704,14 +698,6 @@ static struct platform_device msm_device_gfx2d0_pixv1_ctx = { }, }; -static struct platform_device msm_device_gfx2d0_texv3_ctx = { - .name = "msm_iommu_ctx", - .id = 20, - .dev = { - .parent = &msm_device_iommu_gfx2d0.dev, - }, -}; - static struct platform_device *msm_iommu_devs[] = { &msm_device_iommu_jpegd, &msm_device_iommu_vpe, @@ -760,8 +746,7 @@ static struct platform_device *msm_iommu_ctx_devs[] = { &msm_device_vcodec_b_mm2_ctx, &msm_device_gfx3d_user_ctx, &msm_device_gfx3d_priv_ctx, - &msm_device_gfx2d0_pixv1_ctx, - &msm_device_gfx2d0_texv3_ctx, + &msm_device_gfx2d0_2d0_ctx, }; static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { @@ -784,8 +769,7 @@ static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { &vcodec_b_mm2_ctx, &gfx3d_user_ctx, &gfx3d_priv_ctx, - &gfx2d0_pixv1_ctx, - &gfx2d0_texv3_ctx, + &gfx2d0_2d0_ctx, }; static int msm8x60_iommu_init(void) From e8952e3b32701817705b216b492a9be4fa5cbefc Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:52 -0800 Subject: [PATCH 13/33] msm: iommu: Support for the 2nd GFX core's IOMMU Add the platform data and resources needed for the second 2D graphics core's IOMMU. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/devices-msm8x60-iommu.c | 54 +++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-msm8x60-iommu.c index 8cccb2680542..a6ecd39ae069 100644 --- a/arch/arm/mach-msm/devices-msm8x60-iommu.c +++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c @@ -254,6 +254,27 @@ static struct resource msm_iommu_gfx2d0_resources[] = { }, }; +static struct resource msm_iommu_gfx2d1_resources[] = { + { + .start = MSM_IOMMU_GFX2D1_PHYS, + .end = MSM_IOMMU_GFX2D1_PHYS + MSM_IOMMU_GFX2D1_SIZE - 1, + .name = "physbase", + .flags = IORESOURCE_MEM, + }, + { + .name = "nonsecure_irq", + .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ, + .end = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, + { + .name = "secure_irq", + .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ, + .end = SMMU_GFX2D1_CB_SC_SECURE_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + static struct platform_device msm_root_iommu_dev = { .name = "msm_iommu", .id = -1, @@ -307,6 +328,11 @@ static struct msm_iommu_dev gfx2d0_iommu = { .clk_rate = 27000000 }; +static struct msm_iommu_dev gfx2d1_iommu = { + .name = "gfx2d1", + .clk_rate = 27000000 +}; + static struct platform_device msm_device_iommu_jpegd = { .name = "msm_iommu", .id = 0, @@ -417,6 +443,16 @@ static struct platform_device msm_device_iommu_gfx2d0 = { .resource = msm_iommu_gfx2d0_resources, }; +struct platform_device msm_device_iommu_gfx2d1 = { + .name = "msm_iommu", + .id = 11, + .dev = { + .parent = &msm_root_iommu_dev.dev, + }, + .num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources), + .resource = msm_iommu_gfx2d1_resources, +}; + static struct msm_iommu_ctx_dev jpegd_src_ctx = { .name = "jpegd_src", .num = 0, @@ -538,6 +574,12 @@ static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = { .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} }; +static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = { + .name = "gfx2d1_2d1", + .num = 0, + .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} +}; + static struct platform_device msm_device_jpegd_src_ctx = { .name = "msm_iommu_ctx", .id = 0, @@ -698,6 +740,14 @@ static struct platform_device msm_device_gfx2d0_2d0_ctx = { }, }; +static struct platform_device msm_device_gfx2d1_2d1_ctx = { + .name = "msm_iommu_ctx", + .id = 20, + .dev = { + .parent = &msm_device_iommu_gfx2d1.dev, + }, +}; + static struct platform_device *msm_iommu_devs[] = { &msm_device_iommu_jpegd, &msm_device_iommu_vpe, @@ -710,6 +760,7 @@ static struct platform_device *msm_iommu_devs[] = { &msm_device_iommu_vcodec_b, &msm_device_iommu_gfx3d, &msm_device_iommu_gfx2d0, + &msm_device_iommu_gfx2d1, }; static struct msm_iommu_dev *msm_iommu_data[] = { @@ -724,6 +775,7 @@ static struct msm_iommu_dev *msm_iommu_data[] = { &vcodec_b_iommu, &gfx3d_iommu, &gfx2d0_iommu, + &gfx2d1_iommu, }; static struct platform_device *msm_iommu_ctx_devs[] = { @@ -747,6 +799,7 @@ static struct platform_device *msm_iommu_ctx_devs[] = { &msm_device_gfx3d_user_ctx, &msm_device_gfx3d_priv_ctx, &msm_device_gfx2d0_2d0_ctx, + &msm_device_gfx2d1_2d1_ctx, }; static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { @@ -770,6 +823,7 @@ static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { &gfx3d_user_ctx, &gfx3d_priv_ctx, &gfx2d0_2d0_ctx, + &gfx2d1_2d1_ctx, }; static int msm8x60_iommu_init(void) From 516cbc793eb4be5123289d067b54dfcdabeddb25 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:53 -0800 Subject: [PATCH 14/33] msm: iommu: Mark functions with the right section names Mark the init and exit functions as __init and __exit where appropriate. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/devices-msm8x60-iommu.c | 4 ++-- arch/arm/mach-msm/iommu.c | 2 +- arch/arm/mach-msm/iommu_dev.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-msm8x60-iommu.c index a6ecd39ae069..f9e7bd34ec59 100644 --- a/arch/arm/mach-msm/devices-msm8x60-iommu.c +++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c @@ -826,7 +826,7 @@ static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { &gfx2d1_2d1_ctx, }; -static int msm8x60_iommu_init(void) +static int __init msm8x60_iommu_init(void) { int ret, i; @@ -886,7 +886,7 @@ static int msm8x60_iommu_init(void) return ret; } -static void msm8x60_iommu_exit(void) +static void __exit msm8x60_iommu_exit(void) { int i; diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c index f71747db3bee..134add789187 100644 --- a/arch/arm/mach-msm/iommu.c +++ b/arch/arm/mach-msm/iommu.c @@ -585,7 +585,7 @@ static struct iommu_ops msm_iommu_ops = { .domain_has_cap = msm_iommu_domain_has_cap }; -static int msm_iommu_init(void) +static int __init msm_iommu_init(void) { register_iommu(&msm_iommu_ops); return 0; diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c index 9019cee2907b..b83c73b41fd1 100644 --- a/arch/arm/mach-msm/iommu_dev.c +++ b/arch/arm/mach-msm/iommu_dev.c @@ -346,7 +346,7 @@ static struct platform_driver msm_iommu_ctx_driver = { .remove = msm_iommu_ctx_remove, }; -static int msm_iommu_driver_init(void) +static int __init msm_iommu_driver_init(void) { int ret; ret = platform_driver_register(&msm_iommu_driver); @@ -365,7 +365,7 @@ static int msm_iommu_driver_init(void) return ret; } -static void msm_iommu_driver_exit(void) +static void __exit msm_iommu_driver_exit(void) { platform_driver_unregister(&msm_iommu_ctx_driver); platform_driver_unregister(&msm_iommu_driver); From f6f41eb9ccc0e6fad0ccba4c5e0a97de935db734 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:54 -0800 Subject: [PATCH 15/33] msm: iommu: Don't flush page tables if no devices attached Don't flush the page tables on an IOMMU domain if there are no IOMMU devices attached to the domain. The act of attaching to the domain will cause an implicit flush of those areas if the page tables are configured to not be L2 cacheable. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/iommu.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c index 134add789187..74f2157eba4e 100644 --- a/arch/arm/mach-msm/iommu.c +++ b/arch/arm/mach-msm/iommu.c @@ -50,13 +50,16 @@ static void __flush_iotlb(struct iommu_domain *domain) unsigned long *fl_table = priv->pgtable; int i; - dmac_flush_range(fl_table, fl_table + SZ_16K); + if (!list_empty(&priv->list_attached)) { + dmac_flush_range(fl_table, fl_table + SZ_16K); - for (i = 0; i < NUM_FL_PTE; i++) - if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) { - void *sl_table = __va(fl_table[i] & FL_BASE_MASK); - dmac_flush_range(sl_table, sl_table + SZ_4K); - } + for (i = 0; i < NUM_FL_PTE; i++) + if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) { + void *sl_table = __va(fl_table[i] & + FL_BASE_MASK); + dmac_flush_range(sl_table, sl_table + SZ_4K); + } + } #endif list_for_each_entry(ctx_drvdata, &priv->list_attached, attached_elm) { From 2607b0a26094b2d2d174c3e27b2ecc9c49d86f40 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Mon, 15 Nov 2010 17:46:10 -0800 Subject: [PATCH 16/33] msm: iommu: Kconfig item for cacheable page tables Add a Kconfig item to allow the IOMMU page tables to be coherent in the L2 cache. This generally reduces IOTLB miss latencies and has been shown to improve multimedia performance. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index dbbcfeb919db..1c6f76b3d1ac 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -122,6 +122,10 @@ config MACH_MSM8X60_FFA endmenu +config IOMMU_PGTABLES_L2 + def_bool y + depends on ARCH_MSM8X60 && MMU && SMP && CPU_DCACHE_DISABLE=n + config MSM_DEBUG_UART int default 1 if MSM_DEBUG_UART1 From 00d4b2bb03b9ed27f28336b0a68f2bd7f67caa40 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:56 -0800 Subject: [PATCH 17/33] msm: iommu: Check if device is already attached An IOMMU device can only be attached to one IOMMU domain at any given time. Check whether the device is already attached to a domain before allowing it to be attached to another domain. If so, return busy. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/iommu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c index 74f2157eba4e..67e8f531b7af 100644 --- a/arch/arm/mach-msm/iommu.c +++ b/arch/arm/mach-msm/iommu.c @@ -241,6 +241,11 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) goto fail; } + if (!list_empty(&ctx_drvdata->attached_elm)) { + ret = -EBUSY; + goto fail; + } + list_for_each_entry(tmp_drvdata, &priv->list_attached, attached_elm) if (tmp_drvdata == ctx_drvdata) { ret = -EBUSY; From 0ab84745ef65043a616b36b26bec58e1cb62a742 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:29:57 -0800 Subject: [PATCH 18/33] msm: iommu: Kconfig dependency for the IOMMU API Make the IOMMU driver select the IOMMU API in the kernel configuration. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 1c6f76b3d1ac..1a11f1ed216d 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -44,6 +44,7 @@ config ARCH_MSM8X60 select CPU_V7 select MSM_V2_TLMM select MSM_GPIOMUX + select IOMMU_API endchoice @@ -166,4 +167,7 @@ config MSM_GPIOMUX config MSM_V2_TLMM bool + +config IOMMU_API + bool endif From 08bd6839783319085ee0db4c888534e626225774 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Mon, 15 Nov 2010 18:19:35 -0800 Subject: [PATCH 19/33] msm: iommu: Definitions for extended memory attributes Add the register field definitions and memory attribute definitions that will be needed to support IOMMU transactions with cache-coherent memory access. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/include/mach/iommu.h | 13 +++++++++++ .../arm/mach-msm/include/mach/iommu_hw-8xxx.h | 22 ++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h index 17fc79fc8bc2..296c0f10f230 100644 --- a/arch/arm/mach-msm/include/mach/iommu.h +++ b/arch/arm/mach-msm/include/mach/iommu.h @@ -20,6 +20,19 @@ #include +/* Sharability attributes of MSM IOMMU mappings */ +#define MSM_IOMMU_ATTR_NON_SH 0x0 +#define MSM_IOMMU_ATTR_SH 0x4 + +/* Cacheability attributes of MSM IOMMU mappings */ +#define MSM_IOMMU_ATTR_NONCACHED 0x0 +#define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1 +#define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2 +#define MSM_IOMMU_ATTR_CACHED_WT 0x3 + +/* Mask for the cache policy attribute */ +#define MSM_IOMMU_CP_MASK 0x03 + /* Maximum number of Machine IDs that we are allowing to be mapped to the same * context bank. The number of MIDs mapped to the same CB does not affect * performance, but there is a practical limit on how many distinct MIDs may diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h index f9386d3a2f77..c2c3da9444f4 100644 --- a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h +++ b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h @@ -54,6 +54,7 @@ do { \ #define NUM_FL_PTE 4096 #define NUM_SL_PTE 256 +#define NUM_TEX_CLASS 8 /* First-level page table bits */ #define FL_BASE_MASK 0xFFFFFC00 @@ -63,6 +64,9 @@ do { \ #define FL_AP_WRITE (1 << 10) #define FL_AP_READ (1 << 11) #define FL_SHARED (1 << 16) +#define FL_BUFFERABLE (1 << 2) +#define FL_CACHEABLE (1 << 3) +#define FL_TEX0 (1 << 12) #define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20) /* Second-level page table bits */ @@ -73,8 +77,20 @@ do { \ #define SL_AP0 (1 << 4) #define SL_AP1 (2 << 4) #define SL_SHARED (1 << 10) +#define SL_BUFFERABLE (1 << 2) +#define SL_CACHEABLE (1 << 3) +#define SL_TEX0 (1 << 6) #define SL_OFFSET(va) (((va) & 0xFF000) >> 12) +/* Memory type and cache policy attributes */ +#define MT_SO 0 +#define MT_DEV 1 +#define MT_NORMAL 2 +#define CP_NONCACHED 0 +#define CP_WB_WA 1 +#define CP_WT 2 +#define CP_WB_NWA 3 + /* Global register setters / getters */ #define SET_M2VCBR_N(b, N, v) SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v)) #define SET_CBACR_N(b, N, v) SET_GLOBAL_REG_N(CBACR_N, N, (b), (v)) @@ -706,7 +722,9 @@ do { \ #define GET_OCPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC5) #define GET_OCPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC6) #define GET_OCPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC7) - +#define NMRR_ICP(nmrr, n) (((nmrr) & (3 << ((n) * 2))) >> ((n) * 2)) +#define NMRR_OCP(nmrr, n) (((nmrr) & (3 << ((n) * 2 + 16))) >> \ + ((n) * 2 + 16)) /* PAR */ #define GET_FAULT(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT) @@ -750,6 +768,8 @@ do { \ #define GET_NOS5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS5) #define GET_NOS6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS6) #define GET_NOS7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS7) +#define PRRR_NOS(prrr, n) ((prrr) & (1 << ((n) + 24)) ? 1 : 0) +#define PRRR_MT(prrr, n) ((((prrr) & (3 << ((n) * 2))) >> ((n) * 2))) /* RESUME */ From 100832c9b6adb3d63407416931caeba3f3b9a777 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Mon, 15 Nov 2010 18:20:08 -0800 Subject: [PATCH 20/33] msm: iommu: Support cache-coherent memory access Add support for allowing IOMMU memory transactions to be cache coherent, eliminating the need for software cache management in certain situations. This can lead to improvements in performance and power usage, assuming the multimedia core's access pattern exhibits spatial locality and that its working set fits into the cache. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/iommu.c | 93 ++++++++++++++++++++++++++++++++++----- 1 file changed, 82 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c index 67e8f531b7af..a468ee309d65 100644 --- a/arch/arm/mach-msm/iommu.c +++ b/arch/arm/mach-msm/iommu.c @@ -33,6 +33,16 @@ #include #include +#define MRC(reg, processor, op1, crn, crm, op2) \ +__asm__ __volatile__ ( \ +" mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \ +: "=r" (reg)) + +#define RCP15_PRRR(reg) MRC(reg, p15, 0, c10, c2, 0) +#define RCP15_NMRR(reg) MRC(reg, p15, 0, c10, c2, 1) + +static int msm_iommu_tex_class[4]; + DEFINE_SPINLOCK(msm_iommu_lock); struct msm_priv { @@ -98,6 +108,7 @@ static void __reset_context(void __iomem *base, int ctx) static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable) { + unsigned int prrr, nmrr; __reset_context(base, ctx); /* Set up HTW mode */ @@ -130,11 +141,11 @@ static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable) /* Turn on TEX Remap */ SET_TRE(base, ctx, 1); - /* Do not configure PRRR / NMRR on the IOMMU for now. We will assume - * TEX class 0 for everything until attributes are properly worked out - */ - SET_PRRR(base, ctx, 0); - SET_NMRR(base, ctx, 0); + /* Set TEX remap attributes */ + RCP15_PRRR(prrr); + RCP15_NMRR(nmrr); + SET_PRRR(base, ctx, prrr); + SET_NMRR(base, ctx, nmrr); /* Turn on BFB prefetch */ SET_BFBDFE(base, ctx, 1); @@ -304,12 +315,21 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, unsigned long *sl_table; unsigned long *sl_pte; unsigned long sl_offset; + unsigned int pgprot; size_t len = 0x1000UL << order; - int ret = 0; + int ret = 0, tex, sh; spin_lock_irqsave(&msm_iommu_lock, flags); - priv = domain->priv; + sh = (prot & MSM_IOMMU_ATTR_SH) ? 1 : 0; + tex = msm_iommu_tex_class[prot & MSM_IOMMU_CP_MASK]; + + if (tex < 0 || tex > NUM_TEX_CLASS - 1) { + ret = -EINVAL; + goto fail; + } + + priv = domain->priv; if (!priv) { ret = -EINVAL; goto fail; @@ -330,6 +350,18 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, goto fail; } + if (len == SZ_16M || len == SZ_1M) { + pgprot = sh ? FL_SHARED : 0; + pgprot |= tex & 0x01 ? FL_BUFFERABLE : 0; + pgprot |= tex & 0x02 ? FL_CACHEABLE : 0; + pgprot |= tex & 0x04 ? FL_TEX0 : 0; + } else { + pgprot = sh ? SL_SHARED : 0; + pgprot |= tex & 0x01 ? SL_BUFFERABLE : 0; + pgprot |= tex & 0x02 ? SL_CACHEABLE : 0; + pgprot |= tex & 0x04 ? SL_TEX0 : 0; + } + fl_offset = FL_OFFSET(va); /* Upper 12 bits */ fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */ @@ -338,12 +370,12 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, for (i = 0; i < 16; i++) *(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION | FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT | - FL_SHARED; + FL_SHARED | pgprot; } if (len == SZ_1M) *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE | - FL_TYPE_SECT | FL_SHARED; + FL_TYPE_SECT | FL_SHARED | pgprot; /* Need a 2nd level table */ if ((len == SZ_4K || len == SZ_64K) && (*fl_pte) == 0) { @@ -368,14 +400,14 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, if (len == SZ_4K) *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 | - SL_SHARED | SL_TYPE_SMALL; + SL_SHARED | SL_TYPE_SMALL | pgprot; if (len == SZ_64K) { int i; for (i = 0; i < 16; i++) *(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 | - SL_AP1 | SL_SHARED | SL_TYPE_LARGE; + SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot; } __flush_iotlb(domain); @@ -593,8 +625,47 @@ static struct iommu_ops msm_iommu_ops = { .domain_has_cap = msm_iommu_domain_has_cap }; +static int __init get_tex_class(int icp, int ocp, int mt, int nos) +{ + int i = 0; + unsigned int prrr = 0; + unsigned int nmrr = 0; + int c_icp, c_ocp, c_mt, c_nos; + + RCP15_PRRR(prrr); + RCP15_NMRR(nmrr); + + for (i = 0; i < NUM_TEX_CLASS; i++) { + c_nos = PRRR_NOS(prrr, i); + c_mt = PRRR_MT(prrr, i); + c_icp = NMRR_ICP(nmrr, i); + c_ocp = NMRR_OCP(nmrr, i); + + if (icp == c_icp && ocp == c_ocp && c_mt == mt && c_nos == nos) + return i; + } + + return -ENODEV; +} + +static void __init setup_iommu_tex_classes(void) +{ + msm_iommu_tex_class[MSM_IOMMU_ATTR_NONCACHED] = + get_tex_class(CP_NONCACHED, CP_NONCACHED, MT_NORMAL, 1); + + msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_WA] = + get_tex_class(CP_WB_WA, CP_WB_WA, MT_NORMAL, 1); + + msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_NWA] = + get_tex_class(CP_WB_NWA, CP_WB_NWA, MT_NORMAL, 1); + + msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WT] = + get_tex_class(CP_WT, CP_WT, MT_NORMAL, 1); +} + static int __init msm_iommu_init(void) { + setup_iommu_tex_classes(); register_iommu(&msm_iommu_ops); return 0; } From 33069739d1c2f03734d5b5b003593e9552d412c1 Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 12 Nov 2010 19:30:00 -0800 Subject: [PATCH 21/33] msm: iommu: Miscellaneous code cleanup Remove some unneeded assignments and messages, restructure a failure path in iova_to_phys, and make __flush_iotlb return int in preparation for adding IOMMU clock control. Signed-off-by: Stepan Moskovchenko Signed-off-by: Daniel Walker --- arch/arm/mach-msm/iommu.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c index a468ee309d65..f65101742a74 100644 --- a/arch/arm/mach-msm/iommu.c +++ b/arch/arm/mach-msm/iommu.c @@ -50,12 +50,12 @@ struct msm_priv { struct list_head list_attached; }; -static void __flush_iotlb(struct iommu_domain *domain) +static int __flush_iotlb(struct iommu_domain *domain) { struct msm_priv *priv = domain->priv; struct msm_iommu_drvdata *iommu_drvdata; struct msm_iommu_ctx_drvdata *ctx_drvdata; - + int ret = 0; #ifndef CONFIG_IOMMU_PGTABLES_L2 unsigned long *fl_table = priv->pgtable; int i; @@ -79,6 +79,8 @@ static void __flush_iotlb(struct iommu_domain *domain) iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent); SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0); } + + return ret; } static void __reset_context(void __iomem *base, int ctx) @@ -267,7 +269,7 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) __pa(priv->pgtable)); list_add(&(ctx_drvdata->attached_elm), &priv->list_attached); - __flush_iotlb(domain); + ret = __flush_iotlb(domain); fail: spin_unlock_irqrestore(&msm_iommu_lock, flags); @@ -282,6 +284,7 @@ static void msm_iommu_detach_dev(struct iommu_domain *domain, struct msm_iommu_drvdata *iommu_drvdata; struct msm_iommu_ctx_drvdata *ctx_drvdata; unsigned long flags; + int ret; spin_lock_irqsave(&msm_iommu_lock, flags); priv = domain->priv; @@ -296,7 +299,10 @@ static void msm_iommu_detach_dev(struct iommu_domain *domain, if (!iommu_drvdata || !ctx_drvdata || !ctx_dev) goto fail; - __flush_iotlb(domain); + ret = __flush_iotlb(domain); + if (ret) + goto fail; + __reset_context(iommu_drvdata->base, ctx_dev->num); list_del_init(&ctx_drvdata->attached_elm); @@ -410,7 +416,7 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot; } - __flush_iotlb(domain); + ret = __flush_iotlb(domain); fail: spin_unlock_irqrestore(&msm_iommu_lock, flags); return ret; @@ -495,7 +501,7 @@ static int msm_iommu_unmap(struct iommu_domain *domain, unsigned long va, } } - __flush_iotlb(domain); + ret = __flush_iotlb(domain); fail: spin_unlock_irqrestore(&msm_iommu_lock, flags); return ret; @@ -530,9 +536,6 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain, SET_CTX_TLBIALL(base, ctx, 0); SET_V2PPR_VA(base, ctx, va >> V2Pxx_VA_SHIFT); - if (GET_FAULT(base, ctx)) - goto fail; - par = GET_PAR(base, ctx); /* We are dealing with a supersection */ @@ -541,6 +544,9 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain, else /* Upper 20 bits from PAR, lower 12 from VA */ ret = (par & 0xFFFFF000) | (va & 0x00000FFF); + if (GET_FAULT(base, ctx)) + ret = 0; + fail: spin_unlock_irqrestore(&msm_iommu_lock, flags); return ret; @@ -583,8 +589,8 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) { struct msm_iommu_drvdata *drvdata = dev_id; void __iomem *base; - unsigned int fsr = 0; - int ncb = 0, i = 0; + unsigned int fsr; + int ncb, i; spin_lock(&msm_iommu_lock); @@ -595,7 +601,6 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) base = drvdata->base; - pr_err("===== WOAH! =====\n"); pr_err("Unexpected IOMMU page fault!\n"); pr_err("base = %08x\n", (unsigned int) base); From dc6bbc991b0c408daad5df43e5851f1d369e50f7 Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Thu, 9 Dec 2010 15:51:32 +0100 Subject: [PATCH 22/33] msm_serial: Remove redundant unlikely() IS_ERR() already implies unlikely(), so it can be omitted here. Signed-off-by: Tobias Klauser Signed-off-by: David Brown --- drivers/serial/msm_serial.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/msm_serial.c b/drivers/serial/msm_serial.c index f8c816e7725d..8e43a7b69e64 100644 --- a/drivers/serial/msm_serial.c +++ b/drivers/serial/msm_serial.c @@ -686,7 +686,7 @@ static int __init msm_serial_probe(struct platform_device *pdev) msm_port = UART_TO_MSM(port); msm_port->clk = clk_get(&pdev->dev, "uart_clk"); - if (unlikely(IS_ERR(msm_port->clk))) + if (IS_ERR(msm_port->clk)) return PTR_ERR(msm_port->clk); port->uartclk = clk_get_rate(msm_port->clk); printk(KERN_INFO "uartclk = %d\n", port->uartclk); From 294b2dea83ba0a6d6034a7521bc62c317efab17b Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Fri, 10 Dec 2010 14:12:03 -0800 Subject: [PATCH 23/33] msm: iommu: Use the correct memory allocation flag Change msm_iommu_map to use GFP_ATOMIC instead of GFP_KERNEL due to the fact that the call occurs within a spinlock-protected region. Signed-off-by: Stepan Moskovchenko Signed-off-by: David Brown --- arch/arm/mach-msm/iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c index f65101742a74..e2d58e4cb0d7 100644 --- a/arch/arm/mach-msm/iommu.c +++ b/arch/arm/mach-msm/iommu.c @@ -386,7 +386,7 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, /* Need a 2nd level table */ if ((len == SZ_4K || len == SZ_64K) && (*fl_pte) == 0) { unsigned long *sl; - sl = (unsigned long *) __get_free_pages(GFP_KERNEL, + sl = (unsigned long *) __get_free_pages(GFP_ATOMIC, get_order(SZ_4K)); if (!sl) { From 940f2efc28564c478033b075bcfc8e7b694831e1 Mon Sep 17 00:00:00 2001 From: Daniel Walker Date: Mon, 13 Dec 2010 14:35:07 -0800 Subject: [PATCH 24/33] msm: trout: add gpio_to_irq trout has gpiolib support and interrupt support, but was missing the gpio_to_irq function. This adds that functions which should allow proper translation. Signed-off-by: Daniel Walker Signed-off-by: David Brown --- arch/arm/mach-msm/board-trout-gpio.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c index c50f3afc3134..f8c09ef6666f 100644 --- a/arch/arm/mach-msm/board-trout-gpio.c +++ b/arch/arm/mach-msm/board-trout-gpio.c @@ -72,6 +72,13 @@ static int msm_gpiolib_direction_output(struct gpio_chip *chip, return 0; } +static int trout_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip); + + return TROUT_GPIO_TO_INT(offset + chip->base); +} + #define TROUT_GPIO_BANK(name, reg_num, base_gpio, shadow_val) \ { \ .chip = { \ @@ -80,6 +87,7 @@ static int msm_gpiolib_direction_output(struct gpio_chip *chip, .direction_output = msm_gpiolib_direction_output, \ .get = msm_gpiolib_get, \ .set = msm_gpiolib_set, \ + .to_irq = trout_gpio_to_irq, \ .base = base_gpio, \ .ngpio = 8, \ }, \ From 078dde9311dd067a76275ea2c903623cec504e31 Mon Sep 17 00:00:00 2001 From: Daniel Walker Date: Mon, 13 Dec 2010 14:35:08 -0800 Subject: [PATCH 25/33] msm: add CLK_MINMAX to pmdh_clk This adds in the CLK_MINMAX flag to the pmdh_clk since it's actual a min/max clock instead of a single frequency clock. Signed-off-by: Daniel Walker Signed-off-by: David Brown --- arch/arm/mach-msm/devices-msm7x00.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c index 4e8c0bcdc92d..3bf8cb5c8090 100644 --- a/arch/arm/mach-msm/devices-msm7x00.c +++ b/arch/arm/mach-msm/devices-msm7x00.c @@ -364,7 +364,7 @@ struct clk msm_clocks_7x01a[] = { CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF), CLK_PCOM("pbus_clk", PBUS_CLK, NULL, 0), CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), - CLK_PCOM("pmdh_clk", PMDH_CLK, NULL, OFF ), + CLK_PCOM("pmdh_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX), CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), CLK_PCOM("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF), CLK_PCOM("sdc_pclk", SDC1_P_CLK, &msm_device_sdc1.dev, OFF), From 304a09c3251c7c74660fc2ff9c590edf3d4bdd7e Mon Sep 17 00:00:00 2001 From: Daniel Walker Date: Mon, 13 Dec 2010 14:35:09 -0800 Subject: [PATCH 26/33] msm: trout: change name of pmdh_clk to mddi_clk This clock is used in the framebuffer driver as mddi_clk. This just changes the name to match that. This also mirrors a change in Google tree. Signed-off-by: Daniel Walker Signed-off-by: David Brown --- arch/arm/mach-msm/devices-msm7x00.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c index 3bf8cb5c8090..b00a94b84f37 100644 --- a/arch/arm/mach-msm/devices-msm7x00.c +++ b/arch/arm/mach-msm/devices-msm7x00.c @@ -364,7 +364,7 @@ struct clk msm_clocks_7x01a[] = { CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF), CLK_PCOM("pbus_clk", PBUS_CLK, NULL, 0), CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), - CLK_PCOM("pmdh_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX), + CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX), CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), CLK_PCOM("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF), CLK_PCOM("sdc_pclk", SDC1_P_CLK, &msm_device_sdc1.dev, OFF), From 3a790bbe790e79a9744adf105ed135624a590f5b Mon Sep 17 00:00:00 2001 From: Daniel Walker Date: Mon, 13 Dec 2010 14:35:10 -0800 Subject: [PATCH 27/33] msm: add handling for clocks tagged as CLK_MINMAX CLK_MINMAX is used to denote clocks that have a wide variation in possible frequencies. This handling just sets the min and max values to the same value. Signed-off-by: Daniel Walker Signed-off-by: David Brown --- arch/arm/mach-msm/clock.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c index c57210f4f06a..2069bfaa3a26 100644 --- a/arch/arm/mach-msm/clock.c +++ b/arch/arm/mach-msm/clock.c @@ -120,6 +120,21 @@ EXPORT_SYMBOL(clk_get_rate); int clk_set_rate(struct clk *clk, unsigned long rate) { + int ret; + if (clk->flags & CLKFLAG_MAX) { + ret = clk->ops->set_max_rate(clk->id, rate); + if (ret) + return ret; + } + if (clk->flags & CLKFLAG_MIN) { + ret = clk->ops->set_min_rate(clk->id, rate); + if (ret) + return ret; + } + + if (clk->flags & CLKFLAG_MAX || clk->flags & CLKFLAG_MIN) + return ret; + return clk->ops->set_rate(clk->id, rate); } EXPORT_SYMBOL(clk_set_rate); From 50bc0ef42c76879f5d68a88c7063603dc0c9789b Mon Sep 17 00:00:00 2001 From: Daniel Walker Date: Mon, 13 Dec 2010 14:35:11 -0800 Subject: [PATCH 28/33] msm: initial framebuffer support Initial framebuffer components. Add board-trout-panel.c as well as platform parts to enable the framebuffer. This code comes directly from Google's tree. Signed-off-by: Daniel Walker Signed-off-by: David Brown --- arch/arm/mach-msm/Makefile | 1 + arch/arm/mach-msm/board-trout-panel.c | 297 ++++++++++++++++++++++++++ arch/arm/mach-msm/devices-msm7x00.c | 67 ++++++ arch/arm/mach-msm/devices.h | 4 + 4 files changed, 369 insertions(+) create mode 100644 arch/arm/mach-msm/board-trout-panel.c diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 4a1a7ea97c24..59646bbd6195 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o obj-$(CONFIG_MSM_SMD) += last_radio_log.o obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o +obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o diff --git a/arch/arm/mach-msm/board-trout-panel.c b/arch/arm/mach-msm/board-trout-panel.c new file mode 100644 index 000000000000..729bb49a44ca --- /dev/null +++ b/arch/arm/mach-msm/board-trout-panel.c @@ -0,0 +1,297 @@ +/* linux/arch/arm/mach-msm/board-trout-mddi.c +** Author: Brian Swetland +*/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "board-trout.h" +#include "proc_comm.h" +#include "devices.h" + +#define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255 + +#define MDDI_CLIENT_CORE_BASE 0x108000 +#define LCD_CONTROL_BLOCK_BASE 0x110000 +#define SPI_BLOCK_BASE 0x120000 +#define I2C_BLOCK_BASE 0x130000 +#define PWM_BLOCK_BASE 0x140000 +#define GPIO_BLOCK_BASE 0x150000 +#define SYSTEM_BLOCK1_BASE 0x160000 +#define SYSTEM_BLOCK2_BASE 0x170000 + + +#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24) +#define SYSCLKENA (MDDI_CLIENT_CORE_BASE|0x2C) +#define PWM0OFF (PWM_BLOCK_BASE|0x1C) + +#define V_VDDE2E_VDD2_GPIO 0 +#define MDDI_RST_N 82 + +#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00) +#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04) +#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08) +#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C) +#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10) +#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14) +#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18) +#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C) +#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20) +#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24) +#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28) +#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C) +#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30) +#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34) +#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38) +#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C) +#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40) +#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44) +#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48) +#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C) +#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50) +#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54) + +#define SRST (LCD_CONTROL_BLOCK_BASE|0x00) +#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04) +#define START (LCD_CONTROL_BLOCK_BASE|0x08) +#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C) +#define CMN (LCD_CONTROL_BLOCK_BASE|0x10) +#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14) +#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18) +#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C) +#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20) +#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24) +#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28) +#define PXL (LCD_CONTROL_BLOCK_BASE|0x30) +#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34) +#define HSW (LCD_CONTROL_BLOCK_BASE|0x38) +#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C) +#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40) +#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44) +#define VSW (LCD_CONTROL_BLOCK_BASE|0x48) +#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C) +#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50) +#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54) +#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58) +#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C) +#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60) +#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64) +#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68) +#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C) +#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70) +#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74) +#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78) +#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C) +#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80) +#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84) +#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88) +#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C) + +#define SSICTL (SPI_BLOCK_BASE|0x00) +#define SSITIME (SPI_BLOCK_BASE|0x04) +#define SSITX (SPI_BLOCK_BASE|0x08) +#define SSIRX (SPI_BLOCK_BASE|0x0C) +#define SSIINTC (SPI_BLOCK_BASE|0x10) +#define SSIINTS (SPI_BLOCK_BASE|0x14) +#define SSIDBG1 (SPI_BLOCK_BASE|0x18) +#define SSIDBG2 (SPI_BLOCK_BASE|0x1C) +#define SSIID (SPI_BLOCK_BASE|0x20) + +#define WKREQ (SYSTEM_BLOCK1_BASE|0x00) +#define CLKENB (SYSTEM_BLOCK1_BASE|0x04) +#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08) +#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C) +#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00) + +#define GPIODATA (GPIO_BLOCK_BASE|0x00) +#define GPIODIR (GPIO_BLOCK_BASE|0x04) +#define GPIOIS (GPIO_BLOCK_BASE|0x08) +#define GPIOIBE (GPIO_BLOCK_BASE|0x0C) +#define GPIOIEV (GPIO_BLOCK_BASE|0x10) +#define GPIOIE (GPIO_BLOCK_BASE|0x14) +#define GPIORIS (GPIO_BLOCK_BASE|0x18) +#define GPIOMIS (GPIO_BLOCK_BASE|0x1C) +#define GPIOIC (GPIO_BLOCK_BASE|0x20) +#define GPIOOMS (GPIO_BLOCK_BASE|0x24) +#define GPIOPC (GPIO_BLOCK_BASE|0x28) +#define GPIOID (GPIO_BLOCK_BASE|0x30) + +#define SPI_WRITE(reg, val) \ + { SSITX, 0x00010000 | (((reg) & 0xff) << 8) | ((val) & 0xff) }, \ + { 0, 5 }, + +#define SPI_WRITE1(reg) \ + { SSITX, (reg) & 0xff }, \ + { 0, 5 }, + +struct mddi_table { + uint32_t reg; + uint32_t value; +}; +static struct mddi_table mddi_toshiba_init_table[] = { + { DPSET0, 0x09e90046 }, + { DPSET1, 0x00000118 }, + { DPSUS, 0x00000000 }, + { DPRUN, 0x00000001 }, + { 1, 14 }, /* msleep 14 */ + { SYSCKENA, 0x00000001 }, + { CLKENB, 0x0000A1EF }, /* # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK) */ + + { GPIODATA, 0x02000200 }, /* # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0 */ + { GPIODIR, 0x000030D }, /* 24D # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output) */ + { GPIOSEL, 0/*0x00000173*/}, /* # SYS.GPIOSEL # GPIO port multiplexing control */ + { GPIOPC, 0x03C300C0 }, /* # GPI .GPIOPC # GPIO2,3 PD cut */ + { WKREQ, 0x00000000 }, /* # SYS.WKREQ # Wake-up request event is VSYNC alignment */ + + { GPIOIBE, 0x000003FF }, + { GPIOIS, 0x00000000 }, + { GPIOIC, 0x000003FF }, + { GPIOIE, 0x00000000 }, + + { GPIODATA, 0x00040004 }, /* # GPI .GPIODATA # eDRAM VD supply */ + { 1, 1 }, /* msleep 1 */ + { GPIODATA, 0x02040004 }, /* # GPI .GPIODATA # eDRAM VD supply */ + { DRAMPWR, 0x00000001 }, /* eDRAM power */ +}; + +#define GPIOSEL_VWAKEINT (1U << 0) +#define INTMASK_VWAKEOUT (1U << 0) + + +static struct clk *gp_clk; +static int trout_new_backlight = 1; +static struct vreg *vreg_mddi_1v5; +static struct vreg *vreg_lcm_2v85; + +static void trout_process_mddi_table(struct msm_mddi_client_data *client_data, + struct mddi_table *table, size_t count) +{ + int i; + for (i = 0; i < count; i++) { + uint32_t reg = table[i].reg; + uint32_t value = table[i].value; + + if (reg == 0) + udelay(value); + else if (reg == 1) + msleep(value); + else + client_data->remote_write(client_data, value, reg); + } +} + +static int trout_mddi_toshiba_client_init( + struct msm_mddi_bridge_platform_data *bridge_data, + struct msm_mddi_client_data *client_data) +{ + int panel_id; + + client_data->auto_hibernate(client_data, 0); + trout_process_mddi_table(client_data, mddi_toshiba_init_table, + ARRAY_SIZE(mddi_toshiba_init_table)); + client_data->auto_hibernate(client_data, 1); + panel_id = (client_data->remote_read(client_data, GPIODATA) >> 4) & 3; + if (panel_id > 1) { + printk(KERN_WARNING "unknown panel id at mddi_enable\n"); + return -1; + } + return 0; +} + +static int trout_mddi_toshiba_client_uninit( + struct msm_mddi_bridge_platform_data *bridge_data, + struct msm_mddi_client_data *client_data) +{ + return 0; +} + +static struct resource resources_msm_fb[] = { + { + .start = MSM_FB_BASE, + .end = MSM_FB_BASE + MSM_FB_SIZE, + .flags = IORESOURCE_MEM, + }, +}; + +struct msm_mddi_bridge_platform_data toshiba_client_data = { + .init = trout_mddi_toshiba_client_init, + .uninit = trout_mddi_toshiba_client_uninit, + .fb_data = { + .xres = 320, + .yres = 480, + .width = 45, + .height = 67, + .output_format = 0, + }, +}; + +static struct msm_mddi_platform_data mddi_pdata = { + .clk_rate = 122880000, + .fb_resource = resources_msm_fb, + .num_clients = 1, + .client_platform_data = { + { + .product_id = (0xd263 << 16 | 0), + .name = "mddi_c_d263_0000", + .id = 0, + .client_data = &toshiba_client_data, + .clk_rate = 0, + }, + }, +}; + +int __init trout_init_panel(void) +{ + int rc; + + if (!machine_is_trout()) + return 0; + vreg_mddi_1v5 = vreg_get(0, "gp2"); + if (IS_ERR(vreg_mddi_1v5)) + return PTR_ERR(vreg_mddi_1v5); + vreg_lcm_2v85 = vreg_get(0, "gp4"); + if (IS_ERR(vreg_lcm_2v85)) + return PTR_ERR(vreg_lcm_2v85); + + trout_new_backlight = system_rev >= 5; + if (trout_new_backlight) { + uint32_t config = PCOM_GPIO_CFG(27, 0, GPIO_OUTPUT, + GPIO_NO_PULL, GPIO_8MA); + msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0); + } else { + uint32_t config = PCOM_GPIO_CFG(27, 1, GPIO_OUTPUT, + GPIO_NO_PULL, GPIO_8MA); + msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0); + + gp_clk = clk_get(NULL, "gp_clk"); + if (IS_ERR(gp_clk)) { + printk(KERN_ERR "trout_init_panel: could not get gp" + "clock\n"); + gp_clk = NULL; + } + rc = clk_set_rate(gp_clk, 19200000); + if (rc) + printk(KERN_ERR "trout_init_panel: set clock rate " + "failed\n"); + } + + rc = platform_device_register(&msm_device_mdp); + if (rc) + return rc; + msm_device_mddi0.dev.platform_data = &mddi_pdata; + return platform_device_register(&msm_device_mddi0); +} + +device_initcall(trout_init_panel); diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c index b00a94b84f37..fb548a8a21db 100644 --- a/arch/arm/mach-msm/devices-msm7x00.c +++ b/arch/arm/mach-msm/devices-msm7x00.c @@ -347,6 +347,73 @@ int __init msm_add_sdcc(unsigned int controller, return platform_device_register(pdev); } +static struct resource resources_mddi0[] = { + { + .start = MSM_PMDH_PHYS, + .end = MSM_PMDH_PHYS + MSM_PMDH_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_MDDI_PRI, + .end = INT_MDDI_PRI, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource resources_mddi1[] = { + { + .start = MSM_EMDH_PHYS, + .end = MSM_EMDH_PHYS + MSM_EMDH_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_MDDI_EXT, + .end = INT_MDDI_EXT, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device msm_device_mddi0 = { + .name = "msm_mddi", + .id = 0, + .num_resources = ARRAY_SIZE(resources_mddi0), + .resource = resources_mddi0, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +struct platform_device msm_device_mddi1 = { + .name = "msm_mddi", + .id = 1, + .num_resources = ARRAY_SIZE(resources_mddi1), + .resource = resources_mddi1, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +static struct resource resources_mdp[] = { + { + .start = MSM_MDP_PHYS, + .end = MSM_MDP_PHYS + MSM_MDP_SIZE - 1, + .name = "mdp", + .flags = IORESOURCE_MEM + }, + { + .start = INT_MDP, + .end = INT_MDP, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device msm_device_mdp = { + .name = "msm_mdp", + .id = 0, + .num_resources = ARRAY_SIZE(resources_mdp), + .resource = resources_mdp, +}; + struct clk msm_clocks_7x01a[] = { CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h index 568443e76423..68b8075f8ca4 100644 --- a/arch/arm/mach-msm/devices.h +++ b/arch/arm/mach-msm/devices.h @@ -35,6 +35,10 @@ extern struct platform_device msm_device_smd; extern struct platform_device msm_device_nand; +extern struct platform_device msm_device_mddi0; +extern struct platform_device msm_device_mddi1; +extern struct platform_device msm_device_mdp; + extern struct clk msm_clocks_7x01a[]; extern unsigned msm_num_clocks_7x01a; From 62612cf9d97068dc75b48a7a3044ee907a3283ec Mon Sep 17 00:00:00 2001 From: Sahitya Tummala Date: Wed, 8 Dec 2010 15:03:03 +0530 Subject: [PATCH 29/33] mmc: msm_sdcc: Fix possible circular locking dependency warning In the context of request processing thread, data mover lock is acquired after the host lock. In another context, in the completion handler of data mover the locks are acquired in the reverse order, resulting in possible circular lock dependency warning. Hence, schedule a tasklet to process the dma completion so as to avoid nested locks. Signed-off-by: Sahitya Tummala Signed-off-by: David Brown --- drivers/mmc/host/msm_sdcc.c | 49 +++++++++++++++++++++++++------------ drivers/mmc/host/msm_sdcc.h | 3 +++ 2 files changed, 36 insertions(+), 16 deletions(-) diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c index 1290d14c5839..b147971a96ef 100644 --- a/drivers/mmc/host/msm_sdcc.c +++ b/drivers/mmc/host/msm_sdcc.c @@ -189,42 +189,40 @@ msmsdcc_dma_exec_func(struct msm_dmov_cmd *cmd) } static void -msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd, - unsigned int result, - struct msm_dmov_errdata *err) +msmsdcc_dma_complete_tlet(unsigned long data) { - struct msmsdcc_dma_data *dma_data = - container_of(cmd, struct msmsdcc_dma_data, hdr); - struct msmsdcc_host *host = dma_data->host; + struct msmsdcc_host *host = (struct msmsdcc_host *)data; unsigned long flags; struct mmc_request *mrq; + struct msm_dmov_errdata err; spin_lock_irqsave(&host->lock, flags); host->dma.active = 0; + err = host->dma.err; mrq = host->curr.mrq; BUG_ON(!mrq); WARN_ON(!mrq->data); - if (!(result & DMOV_RSLT_VALID)) { + if (!(host->dma.result & DMOV_RSLT_VALID)) { pr_err("msmsdcc: Invalid DataMover result\n"); goto out; } - if (result & DMOV_RSLT_DONE) { + if (host->dma.result & DMOV_RSLT_DONE) { host->curr.data_xfered = host->curr.xfer_size; } else { /* Error or flush */ - if (result & DMOV_RSLT_ERROR) + if (host->dma.result & DMOV_RSLT_ERROR) pr_err("%s: DMA error (0x%.8x)\n", - mmc_hostname(host->mmc), result); - if (result & DMOV_RSLT_FLUSH) + mmc_hostname(host->mmc), host->dma.result); + if (host->dma.result & DMOV_RSLT_FLUSH) pr_err("%s: DMA channel flushed (0x%.8x)\n", - mmc_hostname(host->mmc), result); - if (err) - pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n", - err->flush[0], err->flush[1], err->flush[2], - err->flush[3], err->flush[4], err->flush[5]); + mmc_hostname(host->mmc), host->dma.result); + + pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n", + err.flush[0], err.flush[1], err.flush[2], + err.flush[3], err.flush[4], err.flush[5]); if (!mrq->data->error) mrq->data->error = -EIO; } @@ -273,6 +271,22 @@ msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd, return; } +static void +msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd, + unsigned int result, + struct msm_dmov_errdata *err) +{ + struct msmsdcc_dma_data *dma_data = + container_of(cmd, struct msmsdcc_dma_data, hdr); + struct msmsdcc_host *host = dma_data->host; + + dma_data->result = result; + if (err) + memcpy(&dma_data->err, err, sizeof(struct msm_dmov_errdata)); + + tasklet_schedule(&host->dma_tlet); +} + static int validate_dma(struct msmsdcc_host *host, struct mmc_data *data) { if (host->dma.channel == -1) @@ -1118,6 +1132,9 @@ msmsdcc_probe(struct platform_device *pdev) host->dmares = dmares; spin_lock_init(&host->lock); + tasklet_init(&host->dma_tlet, msmsdcc_dma_complete_tlet, + (unsigned long)host); + /* * Setup DMA */ diff --git a/drivers/mmc/host/msm_sdcc.h b/drivers/mmc/host/msm_sdcc.h index ff2b0f74f6f4..996990dfc7cc 100644 --- a/drivers/mmc/host/msm_sdcc.h +++ b/drivers/mmc/host/msm_sdcc.h @@ -172,6 +172,8 @@ struct msmsdcc_dma_data { struct msmsdcc_host *host; int busy; /* Set if DM is busy */ int active; + unsigned int result; + struct msm_dmov_errdata err; }; struct msmsdcc_pio_data { @@ -235,6 +237,7 @@ struct msmsdcc_host { int cmdpoll; struct msmsdcc_stats stats; + struct tasklet_struct dma_tlet; /* Command parameters */ unsigned int cmd_timeout; unsigned int cmd_pio_irqmask; From d5137bdd91b8267ada3973806443013f4bf079f6 Mon Sep 17 00:00:00 2001 From: Sahitya Tummala Date: Wed, 8 Dec 2010 15:03:04 +0530 Subject: [PATCH 30/33] mmc: msm_sdcc: Add prog done interrupt support Enable prog done interrupt for stop command(CMD12) that is sent after a multi-block write(CMD25). The PROG_DONE bit is set when the card has finished its programming and is ready for next data. After every write request the card will be polled for ready status using CMD13. For a multi-block write(CMD25) before sending CMD13, stop command (CMD12) will be sent. If we enable prog done interrupt for CMD12, then CMD13 polling can be avoided. The prog done interrupt means that the card is done with its programming and is ready for next request. Signed-off-by: Sahitya Tummala Signed-off-by: David Brown --- drivers/mmc/host/msm_sdcc.c | 28 +++++++++++++++++++++++++--- drivers/mmc/host/msm_sdcc.h | 4 +++- 2 files changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c index b147971a96ef..67f536ca31d3 100644 --- a/drivers/mmc/host/msm_sdcc.c +++ b/drivers/mmc/host/msm_sdcc.c @@ -438,6 +438,11 @@ msmsdcc_start_command_deferred(struct msmsdcc_host *host, (cmd->opcode == 53)) *c |= MCI_CSPM_DATCMD; + if (host->prog_scan && (cmd->opcode == 12)) { + *c |= MCI_CPSM_PROGENA; + host->prog_enable = true; + } + if (cmd == cmd->mrq->stop) *c |= MCI_CSPM_MCIABORT; @@ -508,6 +513,8 @@ msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data, host->cmd_c = c; } msm_dmov_enqueue_cmd(host->dma.channel, &host->dma.hdr); + if (data->flags & MMC_DATA_WRITE) + host->prog_scan = true; } else { msmsdcc_writel(host, timeout, MMCIDATATIMER); @@ -718,8 +725,23 @@ static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status) else if (host->curr.data) { /* Non DMA */ msmsdcc_stop_data(host); msmsdcc_request_end(host, cmd->mrq); - } else /* host->data == NULL */ - msmsdcc_request_end(host, cmd->mrq); + } else { /* host->data == NULL */ + if (!cmd->error && host->prog_enable) { + if (status & MCI_PROGDONE) { + host->prog_scan = false; + host->prog_enable = false; + msmsdcc_request_end(host, cmd->mrq); + } else { + host->curr.cmd = cmd; + } + } else { + if (host->prog_enable) { + host->prog_scan = false; + host->prog_enable = false; + } + msmsdcc_request_end(host, cmd->mrq); + } + } } else if (cmd->data) if (!(cmd->data->flags & MMC_DATA_READ)) msmsdcc_start_data(host, cmd->data, @@ -733,7 +755,7 @@ msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status, struct mmc_data *data = host->curr.data; if (status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL | - MCI_CMDTIMEOUT) && host->curr.cmd) { + MCI_CMDTIMEOUT | MCI_PROGDONE) && host->curr.cmd) { msmsdcc_do_cmdirq(host, status); } diff --git a/drivers/mmc/host/msm_sdcc.h b/drivers/mmc/host/msm_sdcc.h index 996990dfc7cc..e0579a1cc9e5 100644 --- a/drivers/mmc/host/msm_sdcc.h +++ b/drivers/mmc/host/msm_sdcc.h @@ -138,7 +138,7 @@ #define MCI_IRQENABLE \ (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ - MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATAENDMASK) + MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATAENDMASK|MCI_PROGDONEMASK) /* * The size of the FIFO in bytes. @@ -245,6 +245,8 @@ struct msmsdcc_host { struct mmc_command *cmd_cmd; u32 cmd_c; + bool prog_scan; + bool prog_enable; }; #endif From b08bb35d1a5ee5426198eb3a2861008c2e9e6fc4 Mon Sep 17 00:00:00 2001 From: Sahitya Tummala Date: Wed, 8 Dec 2010 15:03:05 +0530 Subject: [PATCH 31/33] mmc: msm_sdcc: Reset SDCC in case of data transfer errors SDCC uses an asynchronous FIFOs for data synchronization (one for TX and one for RX). For any error when DPSM (Data path state machine) is involved the transfer is terminated with the remaining data stuck inside FIFOs. Reset the controller in case of data errors to ensure that any left over data in FIFOs is flushed out and DPSM is in good state. The following problems are observed without this reset functionality - 1. After the card is removed in an unsafe way (removed when there is an on going data transfer), the card will not be detected upon its next insertion. This is because the controller wouldn't respond to few initialization commands. 2. When an error occurs for a data transfer in non-DMA mode, sometimes we get spurious PIO interrupt after the request is processed. Signed-off-by: Sahitya Tummala Signed-off-by: David Brown --- drivers/mmc/host/msm_sdcc.c | 39 +++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c index 67f536ca31d3..81ed16fb42b5 100644 --- a/drivers/mmc/host/msm_sdcc.c +++ b/drivers/mmc/host/msm_sdcc.c @@ -44,6 +44,7 @@ #include #include #include +#include #include "msm_sdcc.h" @@ -126,6 +127,40 @@ static void msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c); +static void msmsdcc_reset_and_restore(struct msmsdcc_host *host) +{ + u32 mci_clk = 0; + u32 mci_mask0 = 0; + int ret = 0; + + /* Save the controller state */ + mci_clk = readl(host->base + MMCICLOCK); + mci_mask0 = readl(host->base + MMCIMASK0); + + /* Reset the controller */ + ret = clk_reset(host->clk, CLK_RESET_ASSERT); + if (ret) + pr_err("%s: Clock assert failed at %u Hz with err %d\n", + mmc_hostname(host->mmc), host->clk_rate, ret); + + ret = clk_reset(host->clk, CLK_RESET_DEASSERT); + if (ret) + pr_err("%s: Clock deassert failed at %u Hz with err %d\n", + mmc_hostname(host->mmc), host->clk_rate, ret); + + pr_info("%s: Controller has been re-initialiazed\n", + mmc_hostname(host->mmc)); + + /* Restore the contoller state */ + writel(host->pwr, host->base + MMCIPOWER); + writel(mci_clk, host->base + MMCICLOCK); + writel(mci_mask0, host->base + MMCIMASK0); + ret = clk_set_rate(host->clk, host->clk_rate); + if (ret) + pr_err("%s: Failed to set clk rate %u Hz (%d)\n", + mmc_hostname(host->mmc), host->clk_rate, ret); +} + static void msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq) { @@ -223,6 +258,8 @@ msmsdcc_dma_complete_tlet(unsigned long data) pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n", err.flush[0], err.flush[1], err.flush[2], err.flush[3], err.flush[4], err.flush[5]); + + msmsdcc_reset_and_restore(host); if (!mrq->data->error) mrq->data->error = -EIO; } @@ -723,6 +760,7 @@ static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status) msm_dmov_stop_cmd(host->dma.channel, &host->dma.hdr, 0); else if (host->curr.data) { /* Non DMA */ + msmsdcc_reset_and_restore(host); msmsdcc_stop_data(host); msmsdcc_request_end(host, cmd->mrq); } else { /* host->data == NULL */ @@ -771,6 +809,7 @@ msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status, msm_dmov_stop_cmd(host->dma.channel, &host->dma.hdr, 0); else { + msmsdcc_reset_and_restore(host); if (host->curr.data) msmsdcc_stop_data(host); if (!data->stop) From 71dd9106af54de0f758875fa4b595af42a327448 Mon Sep 17 00:00:00 2001 From: Sahitya Tummala Date: Wed, 8 Dec 2010 15:03:06 +0530 Subject: [PATCH 32/33] mmc: msm_sdcc: Fix bug in PIO mode when data size is not word aligned The current code for PIO doesn't transfer whole data when data size is not in multiple of 4 bytes. The last few bytes are not written to the card resulting in no DATAEND interrupt from SDCC. This patch allows data transfer for non-aligned data size in PIO mode. Signed-off-by: Sahitya Tummala Signed-off-by: David Brown --- drivers/mmc/host/msm_sdcc.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c index 81ed16fb42b5..9badc51bc4db 100644 --- a/drivers/mmc/host/msm_sdcc.c +++ b/drivers/mmc/host/msm_sdcc.c @@ -613,6 +613,9 @@ msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain) uint32_t *ptr = (uint32_t *) buffer; int count = 0; + if (remain % 4) + remain = ((remain >> 2) + 1) << 2; + while (msmsdcc_readl(host, MMCISTATUS) & MCI_RXDATAAVLBL) { *ptr = msmsdcc_readl(host, MMCIFIFO + (count % MCI_FIFOSIZE)); ptr++; @@ -633,13 +636,14 @@ msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer, char *ptr = buffer; do { - unsigned int count, maxcnt; + unsigned int count, maxcnt, sz; maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE; count = min(remain, maxcnt); - writesl(base + MMCIFIFO, ptr, count >> 2); + sz = count % 4 ? (count >> 2) + 1 : (count >> 2); + writesl(base + MMCIFIFO, ptr, sz); ptr += count; remain -= count; From 0c521ccbd0c9ad5623ff9b37b20b3ff9d4ad65a7 Mon Sep 17 00:00:00 2001 From: Sahitya Tummala Date: Wed, 8 Dec 2010 15:03:07 +0530 Subject: [PATCH 33/33] mmc: msm_sdcc: Check for only DATA_END interrupt to end a request The current code checks for both DATA_END and DATA_BLK_END bits in MCI_STATUS register and ends a request only if both are set at a time. The hardware doesn't always set DATA_BLK_END when DATA_END is set. But DATA_END status itself is sufficient condition from hardware that data transfer is done and hence, check for only DATA_END interrupt in software to end a request. Signed-off-by: Sahitya Tummala Signed-off-by: David Brown --- drivers/mmc/host/msm_sdcc.c | 15 ++++----------- drivers/mmc/host/msm_sdcc.h | 1 - 2 files changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c index 9badc51bc4db..5decfd0bd61d 100644 --- a/drivers/mmc/host/msm_sdcc.c +++ b/drivers/mmc/host/msm_sdcc.c @@ -190,7 +190,7 @@ static void msmsdcc_stop_data(struct msmsdcc_host *host) { host->curr.data = NULL; - host->curr.got_dataend = host->curr.got_datablkend = 0; + host->curr.got_dataend = 0; } uint32_t msmsdcc_fifo_addr(struct msmsdcc_host *host) @@ -277,8 +277,7 @@ msmsdcc_dma_complete_tlet(unsigned long data) host->dma.sg = NULL; host->dma.busy = 0; - if ((host->curr.got_dataend && host->curr.got_datablkend) - || mrq->data->error) { + if (host->curr.got_dataend || mrq->data->error) { /* * If we've already gotten our DATAEND / DATABLKEND @@ -506,7 +505,6 @@ msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data, host->curr.xfer_remain = host->curr.xfer_size; host->curr.data_xfered = 0; host->curr.got_dataend = 0; - host->curr.got_datablkend = 0; memset(&host->pio, 0, sizeof(host->pio)); @@ -827,14 +825,10 @@ msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status, if (!host->curr.got_dataend && (status & MCI_DATAEND)) host->curr.got_dataend = 1; - if (!host->curr.got_datablkend && (status & MCI_DATABLOCKEND)) - host->curr.got_datablkend = 1; - /* * If DMA is still in progress, we complete via the completion handler */ - if (host->curr.got_dataend && host->curr.got_datablkend && - !host->dma.busy) { + if (host->curr.got_dataend && !host->dma.busy) { /* * There appears to be an issue in the controller where * if you request a small block transfer (< fifo size), @@ -871,8 +865,7 @@ msmsdcc_irq(int irq, void *dev_id) do { status = msmsdcc_readl(host, MMCISTATUS); - status &= (msmsdcc_readl(host, MMCIMASK0) | - MCI_DATABLOCKENDMASK); + status &= msmsdcc_readl(host, MMCIMASK0); msmsdcc_writel(host, status, MMCICLEAR); if (status & MCI_SDIOINTR) diff --git a/drivers/mmc/host/msm_sdcc.h b/drivers/mmc/host/msm_sdcc.h index e0579a1cc9e5..939557af266d 100644 --- a/drivers/mmc/host/msm_sdcc.h +++ b/drivers/mmc/host/msm_sdcc.h @@ -190,7 +190,6 @@ struct msmsdcc_curr_req { unsigned int xfer_remain; /* Bytes remaining to send */ unsigned int data_xfered; /* Bytes acked by BLKEND irq */ int got_dataend; - int got_datablkend; int user_pages; };