rt2x00: rt2800pci: use the rt2x00mmio_* routines
Use the recently introduced rt2x00mmio_* routines instead of the rt2x00pci_* variants. The patch contains no functional changes. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Acked-by: Helmut Schaa <helmut.schaa@googlemail.com> Acked-by: Gertjan van Wingerde <gwingerde@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Gabor Juhos
John W. Linville
parent
1d6205d0da
commit
b9570b6687
1 changed files with 121 additions and 116 deletions
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@ -72,7 +72,7 @@ static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
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return;
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for (i = 0; i < 200; i++) {
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rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, ®);
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rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID, ®);
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if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
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(rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
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@ -86,8 +86,8 @@ static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
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if (i == 200)
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ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
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rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
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rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
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rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
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rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
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}
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#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
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@ -116,7 +116,7 @@ static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
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struct rt2x00_dev *rt2x00dev = eeprom->data;
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u32 reg;
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rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
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rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®);
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eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
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eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
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@ -138,7 +138,7 @@ static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
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rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
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!!eeprom->reg_chip_select);
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rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
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rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
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}
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static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
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@ -146,7 +146,7 @@ static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
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struct eeprom_93cx6 eeprom;
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u32 reg;
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rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
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rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®);
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eeprom.data = rt2x00dev;
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eeprom.register_read = rt2800pci_eepromregister_read;
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@ -210,20 +210,20 @@ static void rt2800pci_start_queue(struct data_queue *queue)
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switch (queue->qid) {
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case QID_RX:
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rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
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rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
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rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1);
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rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
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rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
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break;
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case QID_BEACON:
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rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
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rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, ®);
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rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1);
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rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1);
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rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1);
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rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
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rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
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rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, ®);
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rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN, ®);
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rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
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rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
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rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);
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break;
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default:
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break;
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@ -241,13 +241,13 @@ static void rt2800pci_kick_queue(struct data_queue *queue)
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case QID_AC_BE:
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case QID_AC_BK:
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entry = rt2x00queue_get_entry(queue, Q_INDEX);
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rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
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entry->entry_idx);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
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entry->entry_idx);
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break;
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case QID_MGMT:
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entry = rt2x00queue_get_entry(queue, Q_INDEX);
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rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5),
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entry->entry_idx);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX(5),
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entry->entry_idx);
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break;
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default:
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break;
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@ -261,20 +261,20 @@ static void rt2800pci_stop_queue(struct data_queue *queue)
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switch (queue->qid) {
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case QID_RX:
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rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
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rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
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rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
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rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
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rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
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break;
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case QID_BEACON:
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rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
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rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, ®);
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rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0);
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rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0);
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rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
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rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
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rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
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rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, ®);
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rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN, ®);
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rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
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rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
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rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);
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/*
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* Wait for current invocation to finish. The tasklet
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@ -314,19 +314,19 @@ static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
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*/
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reg = 0;
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rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
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rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
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rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
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/*
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* Write firmware to device.
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*/
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rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
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data, len);
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rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
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data, len);
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rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
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rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
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rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
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rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
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rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
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rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
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rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
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rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
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return 0;
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}
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@ -336,7 +336,7 @@ static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
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*/
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static bool rt2800pci_get_entry_state(struct queue_entry *entry)
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{
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struct queue_entry_priv_pci *entry_priv = entry->priv_data;
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struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
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u32 word;
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if (entry->queue->qid == QID_RX) {
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@ -352,7 +352,7 @@ static bool rt2800pci_get_entry_state(struct queue_entry *entry)
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static void rt2800pci_clear_entry(struct queue_entry *entry)
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{
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struct queue_entry_priv_pci *entry_priv = entry->priv_data;
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struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
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struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
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struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
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u32 word;
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@ -370,8 +370,8 @@ static void rt2800pci_clear_entry(struct queue_entry *entry)
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* Set RX IDX in register to inform hardware that we have
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* handled this entry and it is available for reuse again.
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*/
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rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
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entry->entry_idx);
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rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
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entry->entry_idx);
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} else {
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rt2x00_desc_read(entry_priv->desc, 1, &word);
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rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
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@ -381,60 +381,65 @@ static void rt2800pci_clear_entry(struct queue_entry *entry)
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static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
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{
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struct queue_entry_priv_pci *entry_priv;
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struct queue_entry_priv_mmio *entry_priv;
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/*
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* Initialize registers.
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*/
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entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
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rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
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rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
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rt2x00dev->tx[0].limit);
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rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
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rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR0,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT0,
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rt2x00dev->tx[0].limit);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX0, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX0, 0);
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entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
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rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
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rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
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rt2x00dev->tx[1].limit);
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rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
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rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR1,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT1,
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rt2x00dev->tx[1].limit);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX1, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX1, 0);
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entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
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rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
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rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
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rt2x00dev->tx[2].limit);
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rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
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rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR2,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT2,
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rt2x00dev->tx[2].limit);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX2, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX2, 0);
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entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
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rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
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rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
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rt2x00dev->tx[3].limit);
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rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
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rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR3,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT3,
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rt2x00dev->tx[3].limit);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX3, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX3, 0);
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rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR4, 0);
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rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT4, 0);
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rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX4, 0);
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rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX4, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR4, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT4, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX4, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX4, 0);
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rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR5, 0);
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rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT5, 0);
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rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX5, 0);
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rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX5, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR5, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT5, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX5, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX5, 0);
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entry_priv = rt2x00dev->rx->entries[0].priv_data;
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rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
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rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
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rt2x00dev->rx[0].limit);
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rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
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rt2x00dev->rx[0].limit - 1);
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rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
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rt2x00mmio_register_write(rt2x00dev, RX_BASE_PTR,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, RX_MAX_CNT,
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rt2x00dev->rx[0].limit);
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rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
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rt2x00dev->rx[0].limit - 1);
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rt2x00mmio_register_write(rt2x00dev, RX_DRX_IDX, 0);
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rt2800_disable_wpdma(rt2x00dev);
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rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
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rt2x00mmio_register_write(rt2x00dev, DELAY_INT_CFG, 0);
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return 0;
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}
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@ -453,8 +458,8 @@ static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
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* should clear the register to assure a clean state.
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*/
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if (state == STATE_RADIO_IRQ_ON) {
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rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
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rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
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rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
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rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
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}
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spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
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@ -466,7 +471,7 @@ static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
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rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, 1);
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rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, 1);
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}
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rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
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rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
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spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
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if (state == STATE_RADIO_IRQ_OFF) {
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@ -488,7 +493,7 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
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/*
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* Reset DMA indexes
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*/
|
||||
rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, WPDMA_RST_IDX, ®);
|
||||
rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1);
|
||||
rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1);
|
||||
rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1);
|
||||
|
|
@ -496,29 +501,29 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
|
|||
rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1);
|
||||
rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1);
|
||||
rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1);
|
||||
rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
|
||||
|
||||
rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
|
||||
rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
|
||||
rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
|
||||
rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
|
||||
|
||||
if (rt2x00_is_pcie(rt2x00dev) &&
|
||||
(rt2x00_rt(rt2x00dev, RT3572) ||
|
||||
rt2x00_rt(rt2x00dev, RT5390) ||
|
||||
rt2x00_rt(rt2x00dev, RT5392))) {
|
||||
rt2x00pci_register_read(rt2x00dev, AUX_CTRL, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, AUX_CTRL, ®);
|
||||
rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1);
|
||||
rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1);
|
||||
rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, AUX_CTRL, reg);
|
||||
}
|
||||
|
||||
rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
|
||||
rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
|
||||
|
||||
reg = 0;
|
||||
rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1);
|
||||
rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1);
|
||||
rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
|
||||
|
||||
rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
|
||||
rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -538,8 +543,8 @@ static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
|
|||
return retval;
|
||||
|
||||
/* After resume MCU_BOOT_SIGNAL will trash these. */
|
||||
rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
|
||||
rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
|
||||
rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
|
||||
rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
|
||||
|
||||
rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
|
||||
rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
|
||||
|
|
@ -554,8 +559,8 @@ static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
|
|||
{
|
||||
if (rt2x00_is_soc(rt2x00dev)) {
|
||||
rt2800_disable_radio(rt2x00dev);
|
||||
rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
|
||||
rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
|
||||
rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0);
|
||||
rt2x00mmio_register_write(rt2x00dev, TX_PIN_CFG, 0);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -567,10 +572,10 @@ static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
|
|||
0, 0x02);
|
||||
rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
|
||||
} else if (state == STATE_SLEEP) {
|
||||
rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
|
||||
0xffffffff);
|
||||
rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
|
||||
0xffffffff);
|
||||
rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
|
||||
0xffffffff);
|
||||
rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID,
|
||||
0xffffffff);
|
||||
rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
|
||||
0xff, 0x01);
|
||||
}
|
||||
|
|
@ -629,7 +634,7 @@ static void rt2800pci_write_tx_desc(struct queue_entry *entry,
|
|||
struct txentry_desc *txdesc)
|
||||
{
|
||||
struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
|
||||
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
|
||||
struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
|
||||
__le32 *txd = entry_priv->desc;
|
||||
u32 word;
|
||||
|
||||
|
|
@ -683,7 +688,7 @@ static void rt2800pci_write_tx_desc(struct queue_entry *entry,
|
|||
static void rt2800pci_fill_rxdone(struct queue_entry *entry,
|
||||
struct rxdone_entry_desc *rxdesc)
|
||||
{
|
||||
struct queue_entry_priv_pci *entry_priv = entry->priv_data;
|
||||
struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
|
||||
__le32 *rxd = entry_priv->desc;
|
||||
u32 word;
|
||||
|
||||
|
|
@ -914,9 +919,9 @@ static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
|
|||
* access needs locking.
|
||||
*/
|
||||
spin_lock_irq(&rt2x00dev->irqmask_lock);
|
||||
rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®);
|
||||
rt2x00_set_field32(®, irq_field, 1);
|
||||
rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
|
||||
spin_unlock_irq(&rt2x00dev->irqmask_lock);
|
||||
}
|
||||
|
||||
|
|
@ -957,15 +962,15 @@ static void rt2800pci_tbtt_tasklet(unsigned long data)
|
|||
* interval every 64 beacons by 64us to mitigate this effect.
|
||||
*/
|
||||
if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {
|
||||
rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, ®);
|
||||
rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
|
||||
(rt2x00dev->beacon_int * 16) - 1);
|
||||
rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
|
||||
} else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {
|
||||
rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, ®);
|
||||
rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
|
||||
(rt2x00dev->beacon_int * 16));
|
||||
rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
|
||||
}
|
||||
drv_data->tbtt_tick++;
|
||||
drv_data->tbtt_tick %= BCN_TBTT_OFFSET;
|
||||
|
|
@ -978,7 +983,7 @@ static void rt2800pci_tbtt_tasklet(unsigned long data)
|
|||
static void rt2800pci_rxdone_tasklet(unsigned long data)
|
||||
{
|
||||
struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
|
||||
if (rt2x00pci_rxdone(rt2x00dev))
|
||||
if (rt2x00mmio_rxdone(rt2x00dev))
|
||||
tasklet_schedule(&rt2x00dev->rxdone_tasklet);
|
||||
else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
|
||||
rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
|
||||
|
|
@ -1016,7 +1021,7 @@ static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
|
|||
* need to lock the kfifo.
|
||||
*/
|
||||
for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
|
||||
rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &status);
|
||||
rt2x00mmio_register_read(rt2x00dev, TX_STA_FIFO, &status);
|
||||
|
||||
if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
|
||||
break;
|
||||
|
|
@ -1038,8 +1043,8 @@ static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
|
|||
u32 reg, mask;
|
||||
|
||||
/* Read status and ACK all interrupts */
|
||||
rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
|
||||
rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
|
||||
rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
|
||||
rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
|
||||
|
||||
if (!reg)
|
||||
return IRQ_NONE;
|
||||
|
|
@ -1079,9 +1084,9 @@ static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
|
|||
* the tasklet will reenable the appropriate interrupts.
|
||||
*/
|
||||
spin_lock(&rt2x00dev->irqmask_lock);
|
||||
rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
|
||||
rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®);
|
||||
reg &= mask;
|
||||
rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
|
||||
rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
|
||||
spin_unlock(&rt2x00dev->irqmask_lock);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
|
|
@ -1132,13 +1137,13 @@ static const struct ieee80211_ops rt2800pci_mac80211_ops = {
|
|||
};
|
||||
|
||||
static const struct rt2800_ops rt2800pci_rt2800_ops = {
|
||||
.register_read = rt2x00pci_register_read,
|
||||
.register_read_lock = rt2x00pci_register_read, /* same for PCI */
|
||||
.register_write = rt2x00pci_register_write,
|
||||
.register_write_lock = rt2x00pci_register_write, /* same for PCI */
|
||||
.register_multiread = rt2x00pci_register_multiread,
|
||||
.register_multiwrite = rt2x00pci_register_multiwrite,
|
||||
.regbusy_read = rt2x00pci_regbusy_read,
|
||||
.register_read = rt2x00mmio_register_read,
|
||||
.register_read_lock = rt2x00mmio_register_read, /* same for PCI */
|
||||
.register_write = rt2x00mmio_register_write,
|
||||
.register_write_lock = rt2x00mmio_register_write, /* same for PCI */
|
||||
.register_multiread = rt2x00mmio_register_multiread,
|
||||
.register_multiwrite = rt2x00mmio_register_multiwrite,
|
||||
.regbusy_read = rt2x00mmio_regbusy_read,
|
||||
.read_eeprom = rt2800pci_read_eeprom,
|
||||
.hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
|
||||
.drv_write_firmware = rt2800pci_write_firmware,
|
||||
|
|
@ -1157,8 +1162,8 @@ static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
|
|||
.get_firmware_name = rt2800pci_get_firmware_name,
|
||||
.check_firmware = rt2800_check_firmware,
|
||||
.load_firmware = rt2800_load_firmware,
|
||||
.initialize = rt2x00pci_initialize,
|
||||
.uninitialize = rt2x00pci_uninitialize,
|
||||
.initialize = rt2x00mmio_initialize,
|
||||
.uninitialize = rt2x00mmio_uninitialize,
|
||||
.get_entry_state = rt2800pci_get_entry_state,
|
||||
.clear_entry = rt2800pci_clear_entry,
|
||||
.set_device_state = rt2800pci_set_device_state,
|
||||
|
|
@ -1171,7 +1176,7 @@ static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
|
|||
.start_queue = rt2800pci_start_queue,
|
||||
.kick_queue = rt2800pci_kick_queue,
|
||||
.stop_queue = rt2800pci_stop_queue,
|
||||
.flush_queue = rt2x00pci_flush_queue,
|
||||
.flush_queue = rt2x00mmio_flush_queue,
|
||||
.write_tx_desc = rt2800pci_write_tx_desc,
|
||||
.write_tx_data = rt2800_write_tx_data,
|
||||
.write_beacon = rt2800_write_beacon,
|
||||
|
|
@ -1192,21 +1197,21 @@ static const struct data_queue_desc rt2800pci_queue_rx = {
|
|||
.entry_num = 128,
|
||||
.data_size = AGGREGATION_SIZE,
|
||||
.desc_size = RXD_DESC_SIZE,
|
||||
.priv_size = sizeof(struct queue_entry_priv_pci),
|
||||
.priv_size = sizeof(struct queue_entry_priv_mmio),
|
||||
};
|
||||
|
||||
static const struct data_queue_desc rt2800pci_queue_tx = {
|
||||
.entry_num = 64,
|
||||
.data_size = AGGREGATION_SIZE,
|
||||
.desc_size = TXD_DESC_SIZE,
|
||||
.priv_size = sizeof(struct queue_entry_priv_pci),
|
||||
.priv_size = sizeof(struct queue_entry_priv_mmio),
|
||||
};
|
||||
|
||||
static const struct data_queue_desc rt2800pci_queue_bcn = {
|
||||
.entry_num = 8,
|
||||
.data_size = 0, /* No DMA required for beacons */
|
||||
.desc_size = TXWI_DESC_SIZE,
|
||||
.priv_size = sizeof(struct queue_entry_priv_pci),
|
||||
.priv_size = sizeof(struct queue_entry_priv_mmio),
|
||||
};
|
||||
|
||||
static const struct rt2x00_ops rt2800pci_ops = {
|
||||
|
|
|
|||
Loading…
Reference in a new issue