ixgbe: Update TXDCTL configuration to correctly handle WTHRESH
This change updated the TXDCTL configuration. The main goal is to be much more explicit about the configuration and avoid a possible fake TX hang when the interrupt throttle rate is set to 0. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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1 changed files with 18 additions and 17 deletions
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@ -2359,13 +2359,11 @@ void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
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struct ixgbe_hw *hw = &adapter->hw;
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u64 tdba = ring->dma;
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int wait_loop = 10;
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u32 txdctl;
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u32 txdctl = IXGBE_TXDCTL_ENABLE;
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u8 reg_idx = ring->reg_idx;
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/* disable queue to avoid issues while updating state */
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txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
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IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
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txdctl & ~IXGBE_TXDCTL_ENABLE);
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IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
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IXGBE_WRITE_FLUSH(hw);
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IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
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@ -2377,18 +2375,22 @@ void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
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IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
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ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
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/* configure fetching thresholds */
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if (adapter->rx_itr_setting == 0) {
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/* cannot set wthresh when itr==0 */
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txdctl &= ~0x007F0000;
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} else {
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/* enable WTHRESH=8 descriptors, to encourage burst writeback */
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txdctl |= (8 << 16);
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}
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if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
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/* PThresh workaround for Tx hang with DFP enabled. */
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txdctl |= 32;
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}
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/*
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* set WTHRESH to encourage burst writeback, it should not be set
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* higher than 1 when ITR is 0 as it could cause false TX hangs
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*
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* In order to avoid issues WTHRESH + PTHRESH should always be equal
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* to or less than the number of on chip descriptors, which is
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* currently 40.
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*/
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if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
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txdctl |= (1 << 16); /* WTHRESH = 1 */
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else
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txdctl |= (8 << 16); /* WTHRESH = 8 */
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/* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
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txdctl |= (1 << 8) | /* HTHRESH = 1 */
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32; /* PTHRESH = 32 */
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/* reinitialize flowdirector state */
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if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
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@ -2403,7 +2405,6 @@ void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
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clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
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/* enable queue */
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txdctl |= IXGBE_TXDCTL_ENABLE;
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IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
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/* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
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