[PATCH] powerpc: Add FSL SEC node to documentation
Documentation: Added FSL SOC SEC node definition Updated the documentation to include the definition of the SEC device node format for Freescale SOC devices. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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@ -1365,6 +1365,78 @@ platforms are moved over to use the flattened-device-tree model.
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};
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g) Freescale SOC SEC Security Engines
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Required properties:
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- device_type : Should be "crypto"
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- model : Model of the device. Should be "SEC1" or "SEC2"
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- compatible : Should be "talitos"
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- reg : Offset and length of the register set for the device
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- interrupts : <a b> where a is the interrupt number and b is a
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field that represents an encoding of the sense and level
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information for the interrupt. This should be encoded based on
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the information in section 2) depending on the type of interrupt
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controller you have.
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- interrupt-parent : the phandle for the interrupt controller that
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services interrupts for this device.
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- num-channels : An integer representing the number of channels
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available.
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- channel-fifo-len : An integer representing the number of
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descriptor pointers each channel fetch fifo can hold.
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- exec-units-mask : The bitmask representing what execution units
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(EUs) are available. It's a single 32 bit cell. EU information
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should be encoded following the SEC's Descriptor Header Dword
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EU_SEL0 field documentation, i.e. as follows:
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bit 0 = reserved - should be 0
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bit 1 = set if SEC has the ARC4 EU (AFEU)
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bit 2 = set if SEC has the DES/3DES EU (DEU)
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bit 3 = set if SEC has the message digest EU (MDEU)
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bit 4 = set if SEC has the random number generator EU (RNG)
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bit 5 = set if SEC has the public key EU (PKEU)
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bit 6 = set if SEC has the AES EU (AESU)
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bit 7 = set if SEC has the Kasumi EU (KEU)
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bits 8 through 31 are reserved for future SEC EUs.
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- descriptor-types-mask : The bitmask representing what descriptors
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are available. It's a single 32 bit cell. Descriptor type
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information should be encoded following the SEC's Descriptor
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Header Dword DESC_TYPE field documentation, i.e. as follows:
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bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
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bit 1 = set if SEC supports the ipsec_esp descriptor type
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bit 2 = set if SEC supports the common_nonsnoop desc. type
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bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
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bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
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bit 5 = set if SEC supports the srtp descriptor type
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bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
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bit 7 = set if SEC supports the pkeu_assemble descriptor type
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bit 8 = set if SEC supports the aesu_key_expand_output desc.type
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bit 9 = set if SEC supports the pkeu_ptmul descriptor type
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bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
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bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
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..and so on and so forth.
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Example:
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/* MPC8548E */
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crypto@30000 {
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device_type = "crypto";
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model = "SEC2";
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compatible = "talitos";
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reg = <30000 10000>;
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interrupts = <1d 3>;
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interrupt-parent = <40000>;
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num-channels = <4>;
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channel-fifo-len = <24>;
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exec-units-mask = <000000fe>;
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descriptor-types-mask = <073f1127>;
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};
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More devices will be defined as this spec matures.
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