iommu: arm-smmu: Add atos self test
Add atos self test to perform atos for different sids. To enable, set CONFIG_ARM_SMMU_SELFTEST and arm_smmu.selftest=1 and set the sids and masks in arm_smmu.selftestsids in the below format smmu_name,no_of_sids,sid:mask. for eg: arm_smmu.selftestsids=kgsl,0x1,0x7:0x400,apps,0x2, 0x1:0x0,0x51f:0x0 Change-Id: I74134ed712e06a17b1570256e2ee3820df2f4457 Signed-off-by: Charan Teja Reddy <charante@codeaurora.org> Signed-off-by: Prakash Gupta <guptap@codeaurora.org> Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
This commit is contained in:
Prakash Gupta
Vijayanand Jitta
parent
70f32294d6
commit
b86d7318eb
4 changed files with 351 additions and 22 deletions
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@ -417,7 +417,6 @@ struct qsmmuv500_archdata {
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u32 actlr_tbl_size;
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u32 testbus_version;
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};
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#define get_qsmmuv500_archdata(smmu) \
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((struct qsmmuv500_archdata *)(smmu->archdata))
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@ -491,6 +490,7 @@ static int arm_smmu_setup_default_domain(struct device *dev,
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struct iommu_domain *domain);
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static int __arm_smmu_domain_set_attr(struct iommu_domain *domain,
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enum iommu_attr attr, void *data);
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struct iommu_device *get_iommu_by_fwnode(struct fwnode_handle *fwnode);
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static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
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{
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@ -585,12 +585,37 @@ static void arm_smmu_secure_domain_unlock(struct arm_smmu_domain *smmu_domain)
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mutex_unlock(&smmu_domain->assign_lock);
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}
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static struct qsmmuv500_tbu_device *qsmmuv500_find_tbu(
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struct arm_smmu_device *smmu, u32 sid)
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{
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struct qsmmuv500_tbu_device *tbu = NULL;
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struct qsmmuv500_archdata *data = get_qsmmuv500_archdata(smmu);
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list_for_each_entry(tbu, &data->tbus, list) {
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if (tbu->sid_start <= sid &&
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sid < tbu->sid_start + tbu->num_sids)
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return tbu;
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}
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return NULL;
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}
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static bool selftest_running;
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#ifdef CONFIG_ARM_SMMU_SELFTEST
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struct sme_pair {
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u32 num_smrs;
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struct arm_smmu_smr *smrs;
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};
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static int selftest;
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module_param_named(selftest, selftest, int, 0644);
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static int irq_count;
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#define MAXLEN 1000
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static char selftestsids[MAXLEN];
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module_param_string(selftestsids, selftestsids, sizeof(selftestsids), 0644);
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static DECLARE_WAIT_QUEUE_HEAD(wait_int);
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static irqreturn_t arm_smmu_cf_selftest(int irq, void *cb_base)
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{
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@ -681,10 +706,273 @@ static void arm_smmu_interrupt_selftest(struct arm_smmu_device *smmu)
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WARN_ON(cb_count != irq_count);
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irq_count = 0;
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}
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static int arm_smmu_find_sme(struct arm_smmu_smr *, u32, u16, u16);
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static int arm_smmu_run_atos(struct device *dev)
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{
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dma_addr_t iova;
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phys_addr_t phys, output, phys_soft;
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struct page *page = NULL;
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struct iommu_domain *domain;
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int ret = 0;
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page = alloc_page(GFP_KERNEL);
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if (!page) {
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dev_err(dev, "Unable to allocate memory\n");
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return -ENOMEM;
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}
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phys = page_to_phys(page);
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domain = iommu_get_domain_for_dev(dev);
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domain->is_debug_domain = true;
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iova = 0x1000;
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if (iommu_map(domain, iova, phys, SZ_4K,
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IOMMU_READ | IOMMU_WRITE)) {
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dev_err(dev, "Mapping failed\n");
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goto out_detach;
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}
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output = iommu_iova_to_phys_hard(domain, iova, IOMMU_TRANS_DEFAULT);
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if (!output || output != phys) {
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phys_soft = arm_smmu_iova_to_phys(domain, iova);
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dev_err(dev, "atos is failed, output : %pa\n", &output);
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dev_err(dev, "soft iova-to-phys : %pa\n", &phys_soft);
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} else
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dev_err(dev, "atos succeeded, output : %pa\n", &output);
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iommu_unmap(domain, iova, SZ_4K);
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out_detach:
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__free_pages(page, 0);
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return ret;
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}
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static int of_iommu_do_atos(struct device *dev, struct sme_pair *sme,
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struct of_phandle_args *iommu_spec)
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{
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u16 i;
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int err = 0;
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bool set_iommu_ops = false;
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const struct iommu_ops *ops = NULL;
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for (i = 0; i < sme->num_smrs; ++i) {
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struct arm_smmu_smr *smr;
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smr = &sme->smrs[i];
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if (!smr->valid) {
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dev_info(dev, "Can't run atos smr idx %d\n", i);
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continue;
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}
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iommu_spec->args[0] = smr->id;
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iommu_spec->args[1] = smr->mask;
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dev_dbg(dev, "ATOS for : SID 0x%x, MASK 0x%x\n",
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iommu_spec->args[0], iommu_spec->args[1]);
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err = of_iommu_fill_fwspec(dev, iommu_spec);
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if (err) {
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dev_err(dev, "Failed to do the of_iommu_xlate\n");
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break;
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}
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ops = dev->iommu_fwspec->ops;
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if (!platform_bus_type.iommu_ops) {
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platform_bus_type.iommu_ops = ops;
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set_iommu_ops = true;
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}
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if (ops && ops->add_device && dev->bus && !dev->iommu_group)
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err = ops->add_device(dev);
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if (err) {
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dev_err(dev, "Adding to IOMMU failed: %d\n", err);
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return err;
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}
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/* Now we have every thing. Run ATOS. */
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arm_smmu_run_atos(dev);
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if (ops->remove_device && dev->iommu_group)
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ops->remove_device(dev);
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if (set_iommu_ops)
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platform_bus_type.iommu_ops = NULL;
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}
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return err;
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}
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static bool arm_smmu_valid_smr(struct arm_smmu_device *smmu, u32 idx,
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u32 sid, u32 mask)
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{
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u32 smr1, smr2;
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void __iomem *gr0_smr = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_SMR(idx);
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smr1 = SMR_VALID | sid << SMR_ID_SHIFT | mask << SMR_MASK_SHIFT;
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writel_relaxed(smr1, gr0_smr);
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smr2 = readl_relaxed(gr0_smr);
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writel_relaxed(0, gr0_smr);
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return smr1 == smr2;
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}
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static int get_atos_selftest_sids(struct arm_smmu_device *smmu,
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struct sme_pair *sme)
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{
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struct device *dev = smmu->dev;
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struct arm_smmu_smr *smrs = smmu->smrs;
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struct arm_smmu_smr *selftest_smrs;
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enum arm_smmu_implementation model;
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struct qsmmuv500_tbu_device *tbu;
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int i, idx, sid_count, ret = 0;
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char *name, *buf, *split, *sid, *buf_start;
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buf = kstrdup(selftestsids, GFP_KERNEL);
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buf_start = buf;
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while (buf) {
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name = strsep(&buf, ",");
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if (strnstr(dev_name(dev), name, strlen(dev_name(dev)))) {
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kstrtoint(strsep(&buf, ","), 0, &sid_count);
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if (sid_count <= 0) {
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dev_err(smmu->dev, "Invalid sid_count : %d\n",
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sid_count);
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goto out;
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}
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sme->smrs = kcalloc(sid_count, sizeof(*smmu->smrs),
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GFP_KERNEL);
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if (!sme->smrs) {
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ret = -ENOMEM;
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goto out;
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}
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selftest_smrs = sme->smrs;
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for (i = 0; i < sid_count; i++) {
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split = strsep(&buf, ",");
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sid = strsep(&split, ":");
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if (!split) {
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ret = -EINVAL;
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goto invalid_format;
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}
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kstrtou16(sid, 0,
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&selftest_smrs[i].id);
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kstrtou16(split, 0, &selftest_smrs[i].mask);
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}
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sme->num_smrs = sid_count;
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for (i = 0; i < sid_count; i++) {
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mutex_lock(&smmu->stream_map_mutex);
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idx = arm_smmu_find_sme(smrs,
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smmu->num_mapping_groups,
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selftest_smrs[i].id,
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selftest_smrs[i].mask);
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mutex_unlock(&smmu->stream_map_mutex);
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if (idx < 0) {
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selftest_smrs[i].valid = false;
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} else if ((idx >= 0) && smrs &&
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(smrs[idx].valid)) {
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dev_err(dev,
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"sid : 0x%x is already present at idx = %d choose a different sid\n",
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selftest_smrs[i].id, idx);
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selftest_smrs[i].valid = false;
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} else {
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if (!arm_smmu_valid_smr(smmu, idx,
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selftest_smrs[i].id,
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selftest_smrs[i].mask))
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selftest_smrs[i].valid = false;
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else
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selftest_smrs[i].valid = true;
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}
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model = smmu->model;
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switch (model) {
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case QCOM_SMMUV500:
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tbu = qsmmuv500_find_tbu(smmu,
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selftest_smrs[i].id);
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dev_info(tbu->dev, "idx = %d valid: %d, sid : 0x%x, mask: 0x%x\n",
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idx,
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selftest_smrs[i].valid,
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selftest_smrs[i].id,
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selftest_smrs[i].mask);
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break;
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case QCOM_SMMUV2:
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dev_info(smmu->dev, "idx = %d valid: %d, sid : 0x%x, mask: 0x%x\n",
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idx,
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selftest_smrs[i].valid,
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selftest_smrs[i].id,
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selftest_smrs[i].mask);
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break;
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default:
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ret = -EINVAL;
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goto out;
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}
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}
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}
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}
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ret = sid_count;
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goto out;
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invalid_format:
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dev_err(smmu->dev, "Invalid Format : <%s> Expected Format : <smmu_name,sid_count,sid:mask>\n",
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selftestsids);
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kfree(sme->smrs);
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out:
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kfree(buf_start);
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return ret;
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}
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static void arm_smmu_atos_selftest(struct arm_smmu_device *smmu)
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{
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struct platform_device *pdev;
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struct device *smmu_dev = smmu->dev;
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struct device *atos_dev;
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struct of_phandle_args iommu_spec = {0};
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struct sme_pair sme = {0};
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int ret;
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if (!selftest)
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return;
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dev_notice(smmu_dev, "ATOS Self test started\n");
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ret = get_atos_selftest_sids(smmu, &sme);
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if (ret <= 0) {
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dev_err(smmu_dev, "ATOS Self test failed ret %d!!\n", ret);
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return;
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}
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pdev = platform_device_register_simple("atos_test_device",
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-1, NULL, 0);
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if (!pdev) {
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dev_err(smmu_dev, "Unable to create a atos test device\n");
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return;
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}
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atos_dev = &pdev->dev;
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/* try to fill the iommu_fwspec to use. */
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iommu_spec.np = of_node_get(smmu_dev->of_node);
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iommu_spec.args_count = (smmu->model == QCOM_SMMUV2) ? 1 : 2;
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selftest_running = true;
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of_iommu_do_atos(atos_dev, &sme, &iommu_spec);
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selftest_running = false;
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dev_notice(smmu_dev, "ATOS Self test complete\n");
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kfree(sme.smrs);
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of_node_put(iommu_spec.np);
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platform_device_unregister(pdev);
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}
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#else
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static void arm_smmu_interrupt_selftest(struct arm_smmu_device *smmu)
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{
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}
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static void arm_smmu_atos_selftest(struct arm_smmu_device *smmu)
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{
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}
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#endif
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/*
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@ -1156,20 +1444,6 @@ static void arm_smmu_domain_power_off(struct iommu_domain *domain,
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arm_smmu_power_off(smmu->pwr);
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}
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static struct qsmmuv500_tbu_device *qsmmuv500_find_tbu(
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struct arm_smmu_device *smmu, u32 sid)
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{
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struct qsmmuv500_tbu_device *tbu = NULL;
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struct qsmmuv500_archdata *data = get_qsmmuv500_archdata(smmu);
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list_for_each_entry(tbu, &data->tbus, list) {
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if (tbu->sid_start <= sid &&
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sid < tbu->sid_start + tbu->num_sids)
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return tbu;
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}
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return NULL;
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}
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static void arm_smmu_testbus_dump(struct arm_smmu_device *smmu, u16 sid)
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{
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if (smmu->model == QCOM_SMMUV500 &&
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@ -2616,9 +2890,9 @@ static void arm_smmu_test_smr_masks(struct arm_smmu_device *smmu)
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smmu->smr_mask_mask = smr >> SMR_MASK_SHIFT;
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}
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static int arm_smmu_find_sme(struct arm_smmu_device *smmu, u16 id, u16 mask)
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static int arm_smmu_find_sme(struct arm_smmu_smr *smrs, u32 count, u16 id,
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u16 mask)
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{
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struct arm_smmu_smr *smrs = smmu->smrs;
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int i, free_idx = -ENOSPC;
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/* Stream indexing is blissfully easy */
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@ -2626,7 +2900,7 @@ static int arm_smmu_find_sme(struct arm_smmu_device *smmu, u16 id, u16 mask)
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return id;
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/* Validating SMRs is... less so */
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for (i = 0; i < smmu->num_mapping_groups; ++i) {
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for (i = 0; i < count; ++i) {
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if (!smrs[i].valid) {
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/*
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* Note the first free entry we come across, which
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@ -2691,7 +2965,8 @@ static int arm_smmu_master_alloc_smes(struct device *dev)
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goto sme_err;
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}
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ret = arm_smmu_find_sme(smmu, sid, mask);
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ret = arm_smmu_find_sme(smrs, smmu->num_mapping_groups, sid,
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mask);
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if (ret < 0)
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goto sme_err;
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@ -3486,7 +3761,8 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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if (smmu->options & ARM_SMMU_OPT_DISABLE_ATOS)
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return 0;
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if (!selftest_running)
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return 0;
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if (arm_smmu_power_on(smmu_domain->smmu->pwr))
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return 0;
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@ -3613,13 +3889,28 @@ static int arm_smmu_add_device(struct device *dev)
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if (ret)
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goto out_free;
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} else if (fwspec && fwspec->ops == &arm_smmu_ops) {
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struct fwnode_handle *iommu_fwnode = fwspec->iommu_fwnode;
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smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode);
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if (!smmu)
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if (!smmu) {
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if (IS_ENABLED(CONFIG_ARM_SMMU_SELFTEST)) {
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struct iommu_device *iommu = NULL;
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iommu = get_iommu_by_fwnode(iommu_fwnode);
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smmu = iommu ? container_of(iommu, struct
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arm_smmu_device,
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iommu) : NULL;
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if (smmu)
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goto cont;
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}
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return -ENODEV;
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}
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} else {
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return -ENODEV;
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}
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cont:
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ret = arm_smmu_power_on(smmu->pwr);
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if (ret)
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goto out_free;
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@ -5377,6 +5668,7 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
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arm_smmu_device_reset(smmu);
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arm_smmu_test_smr_masks(smmu);
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arm_smmu_interrupt_selftest(smmu);
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arm_smmu_atos_selftest(smmu);
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arm_smmu_power_off(smmu->pwr);
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/*
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@ -5657,7 +5949,6 @@ static void qsmmuv500_tbu_resume(struct qsmmuv500_tbu_device *tbu)
|
|||
spin_unlock_irqrestore(&tbu->halt_lock, flags);
|
||||
}
|
||||
|
||||
|
||||
static int qsmmuv500_ecats_lock(struct arm_smmu_domain *smmu_domain,
|
||||
struct qsmmuv500_tbu_device *tbu,
|
||||
unsigned long *flags)
|
||||
|
|
|
|||
|
|
@ -102,6 +102,29 @@ int iommu_device_register(struct iommu_device *iommu)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARM_SMMU_SELFTEST
|
||||
struct iommu_device *get_iommu_by_fwnode(struct fwnode_handle *fwnode)
|
||||
{
|
||||
struct iommu_device *iommu;
|
||||
|
||||
spin_lock(&iommu_device_lock);
|
||||
list_for_each_entry(iommu, &iommu_device_list, list) {
|
||||
if (iommu->fwnode == fwnode) {
|
||||
spin_unlock(&iommu_device_lock);
|
||||
return iommu;
|
||||
}
|
||||
}
|
||||
spin_unlock(&iommu_device_lock);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
#else
|
||||
struct iommu_device *get_iommu_by_fwnode(struct fwnode_handle *fwnode)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
#endif
|
||||
|
||||
void iommu_device_unregister(struct iommu_device *iommu)
|
||||
{
|
||||
spin_lock(&iommu_device_lock);
|
||||
|
|
|
|||
|
|
@ -222,3 +222,15 @@ const struct iommu_ops *of_iommu_configure(struct device *dev,
|
|||
|
||||
return ops;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARM_SMMU_SELFTEST
|
||||
int of_iommu_fill_fwspec(struct device *dev, struct of_phandle_args *iommu_spec)
|
||||
{
|
||||
return of_iommu_xlate(dev, iommu_spec);
|
||||
}
|
||||
#else
|
||||
int of_iommu_fill_fwspec(struct device *dev, struct of_phandle_args *iommu_spec)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -15,6 +15,9 @@ extern int of_get_dma_window(struct device_node *dn, const char *prefix,
|
|||
extern const struct iommu_ops *of_iommu_configure(struct device *dev,
|
||||
struct device_node *master_np);
|
||||
|
||||
extern int of_iommu_fill_fwspec(struct device *dev, struct of_phandle_args
|
||||
*iommu_spec);
|
||||
|
||||
#else
|
||||
|
||||
static inline int of_get_dma_window(struct device_node *dn, const char *prefix,
|
||||
|
|
|
|||
Loading…
Reference in a new issue