Merge branch 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/radeon/kms: enable unmappable vram for evergreen drm/radeon/kms: fix tiled db height calculation on 6xx/7xx drm/radeon/kms: fix handling of tex lookup disable in cs checker on r2xx
This commit is contained in:
commit
b83db1deb2
6 changed files with 17 additions and 6 deletions
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@ -495,6 +495,7 @@ int evergreen_blit_init(struct radeon_device *rdev)
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dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
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return r;
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}
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rdev->mc.active_vram_size = rdev->mc.real_vram_size;
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return 0;
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}
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@ -502,6 +503,7 @@ void evergreen_blit_fini(struct radeon_device *rdev)
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{
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int r;
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rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
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if (rdev->r600_blit.shader_obj == NULL)
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return;
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/* If we can't reserve the bo, unref should be enough to destroy
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@ -3180,6 +3180,8 @@ static int r100_cs_track_texture_check(struct radeon_device *rdev,
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for (u = 0; u < track->num_texture; u++) {
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if (!track->textures[u].enabled)
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continue;
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if (track->textures[u].lookup_disable)
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continue;
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robj = track->textures[u].robj;
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if (robj == NULL) {
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DRM_ERROR("No texture bound to unit %u\n", u);
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@ -3414,6 +3416,7 @@ void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track
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track->textures[i].robj = NULL;
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/* CS IB emission code makes sure texture unit are disabled */
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track->textures[i].enabled = false;
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track->textures[i].lookup_disable = false;
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track->textures[i].roundup_w = true;
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track->textures[i].roundup_h = true;
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if (track->separate_cube)
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@ -46,6 +46,7 @@ struct r100_cs_track_texture {
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unsigned height_11;
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bool use_pitch;
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bool enabled;
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bool lookup_disable;
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bool roundup_w;
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bool roundup_h;
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unsigned compress_format;
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@ -447,6 +447,8 @@ int r200_packet0_check(struct radeon_cs_parser *p,
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track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
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track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
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}
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if (idx_value & R200_TXFORMAT_LOOKUP_DISABLE)
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track->textures[i].lookup_disable = true;
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switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
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case R200_TXFORMAT_I8:
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case R200_TXFORMAT_RGB332:
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@ -310,7 +310,7 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
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/* Check depth buffer */
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if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
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G_028800_Z_ENABLE(track->db_depth_control)) {
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u32 nviews, bpe, ntiles, pitch, pitch_align, height, size;
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u32 nviews, bpe, ntiles, pitch, pitch_align, height, size, slice_tile_max;
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if (track->db_bo == NULL) {
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dev_warn(p->dev, "z/stencil with no depth buffer\n");
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return -EINVAL;
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@ -354,11 +354,11 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
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} else {
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size = radeon_bo_size(track->db_bo);
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pitch = G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1;
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height = size / (pitch * 8 * bpe);
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height &= ~0x7;
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if (!height)
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height = 8;
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slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
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slice_tile_max *= 64;
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height = slice_tile_max / (pitch * 8);
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if (height > 8192)
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height = 8192;
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switch (G_028010_ARRAY_MODE(track->db_depth_info)) {
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case V_028010_ARRAY_1D_TILED_THIN1:
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pitch_align = (max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8);
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@ -367,6 +367,8 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
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__func__, __LINE__, pitch);
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return -EINVAL;
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}
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/* don't break userspace */
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height &= ~0x7;
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if (!IS_ALIGNED(height, 8)) {
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dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
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__func__, __LINE__, height);
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@ -2836,6 +2836,7 @@
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# define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24)
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# define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24)
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# define R200_TXFORMAT_ST_ROUTE_SHIFT 24
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# define R200_TXFORMAT_LOOKUP_DISABLE (1 << 27)
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# define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)
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# define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)
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# define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)
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