[ARM] OMAP3 clock: DPLL{1,2}_FCLK clksel can divide by 4
OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this into the OMAP3 clock framework. linux-omap source commit is 050684c18f2ea0b08fdd5233a0cd3c7f96e00a0e. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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1 changed files with 16 additions and 4 deletions
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@ -1060,8 +1060,15 @@ static struct clk corex2_fck = {
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/* DPLL power domain clock controls */
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static const struct clksel div2_core_clksel[] = {
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{ .parent = &core_ck, .rates = div2_rates },
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static const struct clksel_rate div4_rates[] = {
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{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
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{ .div = 2, .val = 2, .flags = RATE_IN_343X },
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{ .div = 4, .val = 4, .flags = RATE_IN_343X },
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{ .div = 0 }
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};
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static const struct clksel div4_core_clksel[] = {
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{ .parent = &core_ck, .rates = div4_rates },
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{ .parent = NULL }
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};
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@ -1076,7 +1083,7 @@ static struct clk dpll1_fck = {
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.init = &omap2_init_clksel_parent,
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.clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
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.clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
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.clksel = div2_core_clksel,
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.clksel = div4_core_clksel,
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.flags = RATE_PROPAGATES,
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.recalc = &omap2_clksel_recalc,
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};
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@ -1151,7 +1158,7 @@ static struct clk dpll2_fck = {
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.init = &omap2_init_clksel_parent,
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.clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
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.clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
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.clksel = div2_core_clksel,
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.clksel = div4_core_clksel,
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.flags = RATE_PROPAGATES,
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.recalc = &omap2_clksel_recalc,
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};
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@ -1187,6 +1194,11 @@ static struct clk iva2_ck = {
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/* Common interface clocks */
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static const struct clksel div2_core_clksel[] = {
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{ .parent = &core_ck, .rates = div2_rates },
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{ .parent = NULL }
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};
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static struct clk l3_ick = {
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.name = "l3_ick",
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.ops = &clkops_null,
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