dmaengine/amba-pl08x: Add support for sg len greater than one for slave transfers
Untill now, sg_len greater than one is not supported. This patch adds support to do that. Note: Still, if peripheral is flow controller, sg_len can't be greater that one. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
parent
937bb6e4c6
commit
b7f69d9d42
2 changed files with 243 additions and 181 deletions
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@ -352,7 +352,9 @@ static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
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if (!list_empty(&plchan->pend_list)) {
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struct pl08x_txd *txdi;
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list_for_each_entry(txdi, &plchan->pend_list, node) {
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bytes += txdi->len;
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struct pl08x_sg *dsg;
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list_for_each_entry(dsg, &txd->dsg_list, node)
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bytes += dsg->len;
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}
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}
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@ -567,8 +569,9 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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struct pl08x_lli_build_data bd;
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int num_llis = 0;
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u32 cctl, early_bytes = 0;
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size_t max_bytes_per_lli, total_bytes = 0;
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size_t max_bytes_per_lli, total_bytes;
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struct pl08x_lli *llis_va;
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struct pl08x_sg *dsg;
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txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus);
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if (!txd->llis_va) {
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@ -578,13 +581,9 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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pl08x->pool_ctr++;
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/* Get the default CCTL */
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cctl = txd->cctl;
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bd.txd = txd;
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bd.srcbus.addr = txd->src_addr;
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bd.dstbus.addr = txd->dst_addr;
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bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0;
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cctl = txd->cctl;
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/* Find maximum width of the source bus */
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bd.srcbus.maxwidth =
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@ -596,13 +595,16 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
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PL080_CONTROL_DWIDTH_SHIFT);
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/* Set up the bus widths to the maximum */
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list_for_each_entry(dsg, &txd->dsg_list, node) {
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total_bytes = 0;
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cctl = txd->cctl;
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bd.srcbus.addr = dsg->src_addr;
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bd.dstbus.addr = dsg->dst_addr;
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bd.remainder = dsg->len;
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bd.srcbus.buswidth = bd.srcbus.maxwidth;
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bd.dstbus.buswidth = bd.dstbus.maxwidth;
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/* We need to count this down to zero */
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bd.remainder = txd->len;
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pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);
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dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n",
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@ -616,23 +618,25 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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sbus == &bd.srcbus ? "src" : "dst");
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/*
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* Zero length is only allowed if all these requirements are met:
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* Zero length is only allowed if all these requirements are
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* met:
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* - flow controller is peripheral.
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* - src.addr is aligned to src.width
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* - dst.addr is aligned to dst.width
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*
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* sg_len == 1 should be true, as there can be two cases here:
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* - Memory addresses are contiguous and are not scattered. Here, Only
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* one sg will be passed by user driver, with memory address and zero
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* length. We pass this to controller and after the transfer it will
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* receive the last burst request from peripheral and so transfer
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* finishes.
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*
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* - Memory addresses are scattered and are not contiguous. Here,
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* Obviously as DMA controller doesn't know when a lli's transfer gets
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* over, it can't load next lli. So in this case, there has to be an
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* assumption that only one lli is supported. Thus, we can't have
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* scattered addresses.
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* - Memory addresses are contiguous and are not scattered.
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* Here, Only one sg will be passed by user driver, with
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* memory address and zero length. We pass this to controller
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* and after the transfer it will receive the last burst
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* request from peripheral and so transfer finishes.
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*
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* - Memory addresses are scattered and are not contiguous.
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* Here, Obviously as DMA controller doesn't know when a lli's
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* transfer gets over, it can't load next lli. So in this
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* case, there has to be an assumption that only one lli is
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* supported. Thus, we can't have scattered addresses.
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*/
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if (!bd.remainder) {
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u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >>
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@ -656,6 +660,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
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bd.dstbus.buswidth, 0);
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pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl);
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break;
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}
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/*
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@ -666,14 +671,16 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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if (bd.remainder < mbus->buswidth)
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early_bytes = bd.remainder;
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else if ((mbus->addr) % (mbus->buswidth)) {
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early_bytes = mbus->buswidth - (mbus->addr) % (mbus->buswidth);
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early_bytes = mbus->buswidth - (mbus->addr) %
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(mbus->buswidth);
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if ((bd.remainder - early_bytes) < mbus->buswidth)
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early_bytes = bd.remainder;
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}
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if (early_bytes) {
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dev_vdbg(&pl08x->adev->dev, "%s byte width LLIs "
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"(remain 0x%08x)\n", __func__, bd.remainder);
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dev_vdbg(&pl08x->adev->dev,
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"%s byte width LLIs (remain 0x%08x)\n",
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__func__, bd.remainder);
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prep_byte_width_lli(&bd, &cctl, early_bytes, num_llis++,
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&total_bytes);
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}
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@ -691,9 +698,15 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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sbus->buswidth = 1;
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}
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/* Bytes transferred = tsize * src width, not MIN(buswidths) */
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/*
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* Bytes transferred = tsize * src width, not
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* MIN(buswidths)
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*/
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max_bytes_per_lli = bd.srcbus.buswidth *
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PL080_CONTROL_TRANSFER_SIZE_MASK;
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dev_vdbg(&pl08x->adev->dev,
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"%s max bytes per lli = %zu\n",
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__func__, max_bytes_per_lli);
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/*
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* Make largest possible LLIs until less than one bus
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@ -709,9 +722,10 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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lli_len = min(bd.remainder, max_bytes_per_lli);
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/*
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* Check against maximum bus alignment: Calculate actual
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* transfer size in relation to bus width and get a
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* maximum remainder of the highest bus width - 1
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* Check against maximum bus alignment:
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* Calculate actual transfer size in relation to
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* bus width an get a maximum remainder of the
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* highest bus width - 1
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*/
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width = max(mbus->buswidth, sbus->buswidth);
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lli_len = (lli_len / width) * width;
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@ -724,7 +738,8 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
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bd.dstbus.buswidth, tsize);
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pl08x_fill_lli_for_desc(&bd, num_llis++, lli_len, cctl);
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pl08x_fill_lli_for_desc(&bd, num_llis++,
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lli_len, cctl);
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total_bytes += lli_len;
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}
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@ -740,10 +755,10 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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}
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}
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if (total_bytes != txd->len) {
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if (total_bytes != dsg->len) {
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dev_err(&pl08x->adev->dev,
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"%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
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__func__, total_bytes, txd->len);
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__func__, total_bytes, dsg->len);
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return 0;
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}
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@ -753,6 +768,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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__func__, (u32) MAX_NUM_TSFR_LLIS);
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return 0;
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}
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}
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llis_va = txd->llis_va;
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/* The final LLI terminates the LLI. */
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@ -784,11 +800,18 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
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struct pl08x_txd *txd)
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{
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struct pl08x_sg *dsg, *_dsg;
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/* Free the LLI */
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dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
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pl08x->pool_ctr--;
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list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) {
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list_del(&dsg->node);
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kfree(dsg);
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}
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kfree(txd);
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}
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@ -1234,6 +1257,7 @@ static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan,
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txd->tx.flags = flags;
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txd->tx.tx_submit = pl08x_tx_submit;
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INIT_LIST_HEAD(&txd->node);
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INIT_LIST_HEAD(&txd->dsg_list);
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/* Always enable error and terminal interrupts */
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txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
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struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
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struct pl08x_driver_data *pl08x = plchan->host;
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struct pl08x_txd *txd;
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struct pl08x_sg *dsg;
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int ret;
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txd = pl08x_get_txd(plchan, flags);
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@ -1261,10 +1286,19 @@ static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
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return NULL;
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}
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dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
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if (!dsg) {
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pl08x_free_txd(pl08x, txd);
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dev_err(&pl08x->adev->dev, "%s no memory for pl080 sg\n",
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__func__);
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return NULL;
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}
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list_add_tail(&dsg->node, &txd->dsg_list);
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txd->direction = DMA_NONE;
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txd->src_addr = src;
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txd->dst_addr = dest;
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txd->len = len;
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dsg->src_addr = src;
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dsg->dst_addr = dest;
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dsg->len = len;
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/* Set platform data for m2m */
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txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
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struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
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struct pl08x_driver_data *pl08x = plchan->host;
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struct pl08x_txd *txd;
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struct pl08x_sg *dsg;
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struct scatterlist *sg;
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dma_addr_t slave_addr;
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int ret, tmp;
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/*
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* Current implementation ASSUMES only one sg
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*/
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if (sg_len != 1) {
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dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
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__func__);
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BUG();
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}
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dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
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__func__, sgl->length, plchan->name);
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@ -1324,17 +1352,15 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
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* channel target address dynamically at runtime.
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*/
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txd->direction = direction;
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txd->len = sgl->length;
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if (direction == DMA_TO_DEVICE) {
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txd->cctl = plchan->dst_cctl;
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txd->src_addr = sgl->dma_address;
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txd->dst_addr = plchan->dst_addr;
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slave_addr = plchan->dst_addr;
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} else if (direction == DMA_FROM_DEVICE) {
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txd->cctl = plchan->src_cctl;
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txd->src_addr = plchan->src_addr;
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txd->dst_addr = sgl->dma_address;
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slave_addr = plchan->src_addr;
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} else {
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pl08x_free_txd(pl08x, txd);
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dev_err(&pl08x->adev->dev,
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"%s direction unsupported\n", __func__);
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return NULL;
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txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT;
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for_each_sg(sgl, sg, sg_len, tmp) {
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dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
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if (!dsg) {
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pl08x_free_txd(pl08x, txd);
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dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n",
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__func__);
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return NULL;
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}
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list_add_tail(&dsg->node, &txd->dsg_list);
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dsg->len = sg_dma_len(sg);
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if (direction == DMA_TO_DEVICE) {
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dsg->src_addr = sg_phys(sg);
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dsg->dst_addr = slave_addr;
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} else {
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dsg->src_addr = slave_addr;
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dsg->dst_addr = sg_phys(sg);
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}
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}
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ret = pl08x_prep_channel_resources(plchan, txd);
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if (ret)
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return NULL;
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@ -1452,21 +1498,27 @@ static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
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static void pl08x_unmap_buffers(struct pl08x_txd *txd)
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{
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struct device *dev = txd->tx.chan->device->dev;
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struct pl08x_sg *dsg;
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if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
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if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
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dma_unmap_single(dev, txd->src_addr, txd->len,
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list_for_each_entry(dsg, &txd->dsg_list, node)
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dma_unmap_single(dev, dsg->src_addr, dsg->len,
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DMA_TO_DEVICE);
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else
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dma_unmap_page(dev, txd->src_addr, txd->len,
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else {
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list_for_each_entry(dsg, &txd->dsg_list, node)
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dma_unmap_page(dev, dsg->src_addr, dsg->len,
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DMA_TO_DEVICE);
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}
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}
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if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
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if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
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dma_unmap_single(dev, txd->dst_addr, txd->len,
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list_for_each_entry(dsg, &txd->dsg_list, node)
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dma_unmap_single(dev, dsg->dst_addr, dsg->len,
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DMA_FROM_DEVICE);
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else
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dma_unmap_page(dev, txd->dst_addr, txd->len,
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list_for_each_entry(dsg, &txd->dsg_list, node)
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dma_unmap_page(dev, dsg->dst_addr, dsg->len,
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DMA_FROM_DEVICE);
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}
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}
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@ -105,13 +105,25 @@ struct pl08x_phy_chan {
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struct pl08x_dma_chan *serving;
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};
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/**
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* struct pl08x_sg - structure containing data per sg
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* @src_addr: src address of sg
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* @dst_addr: dst address of sg
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* @len: transfer len in bytes
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* @node: node for txd's dsg_list
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*/
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struct pl08x_sg {
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dma_addr_t src_addr;
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dma_addr_t dst_addr;
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size_t len;
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struct list_head node;
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};
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/**
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* struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
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* @tx: async tx descriptor
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* @node: node for txd list for channels
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* @src_addr: src address of txd
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* @dst_addr: dst address of txd
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* @len: transfer len in bytes
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* @dsg_list: list of children sg's
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* @direction: direction of transfer
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* @llis_bus: DMA memory address (physical) start for the LLIs
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* @llis_va: virtual memory address start for the LLIs
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struct pl08x_txd {
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struct dma_async_tx_descriptor tx;
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struct list_head node;
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struct list_head dsg_list;
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enum dma_data_direction direction;
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dma_addr_t src_addr;
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dma_addr_t dst_addr;
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size_t len;
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dma_addr_t llis_bus;
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struct pl08x_lli *llis_va;
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/* Default cctl value for LLIs */
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