MIPS: Alchemy: Fix AU1100 interrupt numbers off-by-one
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -715,7 +715,7 @@ enum soc_au1500_ints {
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#ifdef CONFIG_SOC_AU1100
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enum soc_au1100_ints {
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AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
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AU1100_UART0_INT,
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AU1100_UART0_INT = AU1100_FIRST_INT,
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AU1100_UART1_INT,
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AU1100_SD_INT,
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AU1100_UART3_INT,
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