Core changes:
- Add support for a bunch of SPI NOR chips - Clear EAR reg when switching to 3-byte addressing mode on Winbond chips SPI NOR controller driver changes: - cadence: Add DMA support for direct mode reads - hisi: Prefix a few functions with hisi_ - intel: * Mark the driver as "dangerous" in Kconfig * Fix atomic sequence handling * Pass a 40us delay (instead of 0us) to readl_poll_timeout() - fsl: * fix a typo in a function name * add support for IP variants embedded in the ls2080a and ls1080a SoCs - stm32: request exclusive control of the reset line -----BEGIN PGP SIGNATURE----- iQI5BAABCAAjBQJbFQHqHBxib3Jpcy5icmV6aWxsb25AYm9vdGxpbi5jb20ACgkQ Ze02AX4ItwAIyBAAw1y6oLc4WcA6//0+sxB9RaYxpng+8n2ExTxcvfc1jd23e5te BRc74YJtbBBe27kkfuhrDLHoTzHMYicB4KA7E4o8JIvIKxfUlY8nP508JAexGEpK wcSNzqjk8zvAZrZ3Uc3xk1wZcYlc4uYAI2XuOjRrW7JFDdKDqSV0NbdjI0V0YFUk n/UQ+m5U1xUilp1IszkU/OdJ7ho1qcxWOC0sqCBXIJ2RrOMQzz3kYF/M9CNZzpth C7zXBVZtJVoy4K6Ibzoudvqcl4TiVu1eMjLPO3FPT3wf73OBPoo9gHvDaw8MqAJw 6Zeu1qbIwEXyR5K3/jlRN2CPkl1tNXqkrZ2CqK6OvLHI1cP99IBQFTbN4aWDm86v tf3Gam7zthWALIkqiAug1tZA4TdFI0ZN6MCBYsfGeeZKF+T22LkkyLseCrVYR28i W2UQDohKyvVE8OVimFdPtjvH9KKJE03hbseTU8D0kOGViptqmidb0Bci6hWqNzxg 0FRWu+LVVd6fDdovKTpuEMS5PJJ5jgjpy/Ch9rRvbqVPC7ZTMwOI5i9sjLcrZ8/v 6InJcBkg+HG5fedzBi15hRtm/XRwJgoI4jJbAgmu3F/92nmMP2lO4ACRUqhgEDN/ gi+UnVA8+aDMJt22c1FHveKVtheTiZNkMFtY16qYYJFmnOuS4jWyTWinihQ= =eIAQ -----END PGP SIGNATURE----- Merge tag 'spi-nor/for-4.18' of git://git.infradead.org/linux-mtd into mtd/next Core changes: - Add support for a bunch of SPI NOR chips - Clear EAR reg when switching to 3-byte addressing mode on Winbond chips SPI NOR controller driver changes: - cadence: Add DMA support for direct mode reads - hisi: Prefix a few functions with hisi_ - intel: * Mark the driver as "dangerous" in Kconfig * Fix atomic sequence handling * Pass a 40us delay (instead of 0us) to readl_poll_timeout() - fsl: * fix a typo in a function name * add support for IP variants embedded in the ls2080a and ls1080a SoCs - stm32: request exclusive control of the reset line
This commit is contained in:
commit
b771327a45
8 changed files with 221 additions and 25 deletions
drivers/mtd/spi-nor
include/linux/mtd
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@ -90,7 +90,7 @@ config SPI_INTEL_SPI
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tristate
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config SPI_INTEL_SPI_PCI
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tristate "Intel PCH/PCU SPI flash PCI driver"
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tristate "Intel PCH/PCU SPI flash PCI driver (DANGEROUS)"
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depends on X86 && PCI
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select SPI_INTEL_SPI
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help
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@ -106,7 +106,7 @@ config SPI_INTEL_SPI_PCI
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will be called intel-spi-pci.
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config SPI_INTEL_SPI_PLATFORM
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tristate "Intel PCH/PCU SPI flash platform driver"
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tristate "Intel PCH/PCU SPI flash platform driver (DANGEROUS)"
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depends on X86
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select SPI_INTEL_SPI
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help
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@ -18,6 +18,8 @@
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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@ -73,6 +75,10 @@ struct cqspi_st {
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struct completion transfer_complete;
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struct mutex bus_mutex;
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struct dma_chan *rx_chan;
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struct completion rx_dma_complete;
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dma_addr_t mmap_phys_base;
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int current_cs;
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int current_page_size;
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int current_erase_size;
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@ -915,11 +921,75 @@ static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
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return len;
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}
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static void cqspi_rx_dma_callback(void *param)
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{
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struct cqspi_st *cqspi = param;
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complete(&cqspi->rx_dma_complete);
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}
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static int cqspi_direct_read_execute(struct spi_nor *nor, u_char *buf,
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loff_t from, size_t len)
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{
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struct cqspi_flash_pdata *f_pdata = nor->priv;
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struct cqspi_st *cqspi = f_pdata->cqspi;
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enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
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dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
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int ret = 0;
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struct dma_async_tx_descriptor *tx;
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dma_cookie_t cookie;
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dma_addr_t dma_dst;
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if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
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memcpy_fromio(buf, cqspi->ahb_base + from, len);
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return 0;
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}
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dma_dst = dma_map_single(nor->dev, buf, len, DMA_DEV_TO_MEM);
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if (dma_mapping_error(nor->dev, dma_dst)) {
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dev_err(nor->dev, "dma mapping failed\n");
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return -ENOMEM;
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}
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tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
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len, flags);
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if (!tx) {
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dev_err(nor->dev, "device_prep_dma_memcpy error\n");
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ret = -EIO;
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goto err_unmap;
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}
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tx->callback = cqspi_rx_dma_callback;
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tx->callback_param = cqspi;
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cookie = tx->tx_submit(tx);
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reinit_completion(&cqspi->rx_dma_complete);
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ret = dma_submit_error(cookie);
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if (ret) {
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dev_err(nor->dev, "dma_submit_error %d\n", cookie);
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ret = -EIO;
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goto err_unmap;
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}
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dma_async_issue_pending(cqspi->rx_chan);
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ret = wait_for_completion_timeout(&cqspi->rx_dma_complete,
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msecs_to_jiffies(len));
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if (ret <= 0) {
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dmaengine_terminate_sync(cqspi->rx_chan);
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dev_err(nor->dev, "DMA wait_for_completion_timeout\n");
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ret = -ETIMEDOUT;
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goto err_unmap;
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}
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err_unmap:
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dma_unmap_single(nor->dev, dma_dst, len, DMA_DEV_TO_MEM);
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return 0;
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}
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static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
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size_t len, u_char *buf)
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{
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struct cqspi_flash_pdata *f_pdata = nor->priv;
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struct cqspi_st *cqspi = f_pdata->cqspi;
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int ret;
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ret = cqspi_set_protocol(nor, 1);
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@ -931,7 +1001,7 @@ static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
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return ret;
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if (f_pdata->use_direct_mode)
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memcpy_fromio(buf, cqspi->ahb_base + from, len);
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ret = cqspi_direct_read_execute(nor, buf, from, len);
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else
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ret = cqspi_indirect_read_execute(nor, buf, from, len);
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if (ret)
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@ -1100,6 +1170,21 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
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cqspi_controller_enable(cqspi, 1);
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}
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static void cqspi_request_mmap_dma(struct cqspi_st *cqspi)
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{
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dma_cap_mask_t mask;
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dma_cap_zero(mask);
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dma_cap_set(DMA_MEMCPY, mask);
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cqspi->rx_chan = dma_request_chan_by_mask(&mask);
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if (IS_ERR(cqspi->rx_chan)) {
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dev_err(&cqspi->pdev->dev, "No Rx DMA available\n");
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cqspi->rx_chan = NULL;
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}
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init_completion(&cqspi->rx_dma_complete);
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}
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static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
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{
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const struct spi_nor_hwcaps hwcaps = {
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@ -1177,6 +1262,9 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
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f_pdata->use_direct_mode = true;
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dev_dbg(nor->dev, "using direct mode for %s\n",
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mtd->name);
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if (!cqspi->rx_chan)
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cqspi_request_mmap_dma(cqspi);
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}
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}
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@ -1237,6 +1325,7 @@ static int cqspi_probe(struct platform_device *pdev)
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dev_err(dev, "Cannot remap AHB address.\n");
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return PTR_ERR(cqspi->ahb_base);
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}
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cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
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cqspi->ahb_size = resource_size(res_ahb);
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init_completion(&cqspi->transfer_complete);
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@ -1307,6 +1396,9 @@ static int cqspi_remove(struct platform_device *pdev)
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cqspi_controller_enable(cqspi, 0);
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if (cqspi->rx_chan)
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dma_release_channel(cqspi->rx_chan);
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clk_disable_unprepare(cqspi->clk);
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pm_runtime_put_sync(&pdev->dev);
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@ -214,6 +214,7 @@ enum fsl_qspi_devtype {
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FSL_QUADSPI_IMX7D,
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FSL_QUADSPI_IMX6UL,
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FSL_QUADSPI_LS1021A,
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FSL_QUADSPI_LS2080A,
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};
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struct fsl_qspi_devtype_data {
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@ -267,6 +268,15 @@ static struct fsl_qspi_devtype_data ls1021a_data = {
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.driver_data = 0,
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};
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static const struct fsl_qspi_devtype_data ls2080a_data = {
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.devtype = FSL_QUADSPI_LS2080A,
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.rxfifo = 128,
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.txfifo = 64,
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.ahb_buf_size = 1024,
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.driver_data = QUADSPI_QUIRK_TKT253890,
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};
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#define FSL_QSPI_MAX_CHIP 4
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struct fsl_qspi {
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struct spi_nor nor[FSL_QSPI_MAX_CHIP];
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@ -661,7 +671,7 @@ static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
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* causes the controller to clear the buffer, and use the sequence pointed
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* by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
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*/
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static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
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static void fsl_qspi_init_ahb_read(struct fsl_qspi *q)
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{
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void __iomem *base = q->iobase;
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int seqid;
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@ -795,7 +805,7 @@ static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
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fsl_qspi_init_lut(q);
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/* Init for AHB read */
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fsl_qspi_init_abh_read(q);
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fsl_qspi_init_ahb_read(q);
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return 0;
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}
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@ -806,6 +816,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = {
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{ .compatible = "fsl,imx7d-qspi", .data = &imx7d_data, },
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{ .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, },
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{ .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
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{ .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
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@ -112,7 +112,7 @@ struct hifmc_host {
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u32 num_chip;
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};
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static inline int wait_op_finish(struct hifmc_host *host)
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static inline int hisi_spi_nor_wait_op_finish(struct hifmc_host *host)
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{
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u32 reg;
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@ -120,7 +120,7 @@ static inline int wait_op_finish(struct hifmc_host *host)
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(reg & FMC_INT_OP_DONE), 0, FMC_WAIT_TIMEOUT);
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}
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static int get_if_type(enum spi_nor_protocol proto)
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static int hisi_spi_nor_get_if_type(enum spi_nor_protocol proto)
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{
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enum hifmc_iftype if_type;
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@ -208,7 +208,7 @@ static int hisi_spi_nor_op_reg(struct spi_nor *nor,
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reg = FMC_OP_CMD1_EN | FMC_OP_REG_OP_START | optype;
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writel(reg, host->regbase + FMC_OP);
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return wait_op_finish(host);
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return hisi_spi_nor_wait_op_finish(host);
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}
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static int hisi_spi_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
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@ -259,9 +259,9 @@ static int hisi_spi_nor_dma_transfer(struct spi_nor *nor, loff_t start_off,
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reg = OP_CFG_FM_CS(priv->chipselect);
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if (op_type == FMC_OP_READ)
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if_type = get_if_type(nor->read_proto);
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if_type = hisi_spi_nor_get_if_type(nor->read_proto);
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else
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if_type = get_if_type(nor->write_proto);
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if_type = hisi_spi_nor_get_if_type(nor->write_proto);
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reg |= OP_CFG_MEM_IF_TYPE(if_type);
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if (op_type == FMC_OP_READ)
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reg |= OP_CFG_DUMMY_NUM(nor->read_dummy >> 3);
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@ -274,7 +274,7 @@ static int hisi_spi_nor_dma_transfer(struct spi_nor *nor, loff_t start_off,
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: OP_CTRL_WR_OPCODE(nor->program_opcode);
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writel(reg, host->regbase + FMC_OP_DMA);
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return wait_op_finish(host);
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return hisi_spi_nor_wait_op_finish(host);
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}
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static ssize_t hisi_spi_nor_read(struct spi_nor *nor, loff_t from, size_t len,
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|
|
|
@ -136,6 +136,7 @@
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* @swseq_reg: Use SW sequencer in register reads/writes
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* @swseq_erase: Use SW sequencer in erase operation
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* @erase_64k: 64k erase supported
|
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* @atomic_preopcode: Holds preopcode when atomic sequence is requested
|
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* @opcodes: Opcodes which are supported. This are programmed by BIOS
|
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* before it locks down the controller.
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*/
|
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|
@ -153,6 +154,7 @@ struct intel_spi {
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bool swseq_reg;
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bool swseq_erase;
|
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bool erase_64k;
|
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u8 atomic_preopcode;
|
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u8 opcodes[8];
|
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};
|
||||
|
||||
|
@ -285,7 +287,7 @@ static int intel_spi_wait_hw_busy(struct intel_spi *ispi)
|
|||
u32 val;
|
||||
|
||||
return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,
|
||||
!(val & HSFSTS_CTL_SCIP), 0,
|
||||
!(val & HSFSTS_CTL_SCIP), 40,
|
||||
INTEL_SPI_TIMEOUT * 1000);
|
||||
}
|
||||
|
||||
|
@ -294,7 +296,7 @@ static int intel_spi_wait_sw_busy(struct intel_spi *ispi)
|
|||
u32 val;
|
||||
|
||||
return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,
|
||||
!(val & SSFSTS_CTL_SCIP), 0,
|
||||
!(val & SSFSTS_CTL_SCIP), 40,
|
||||
INTEL_SPI_TIMEOUT * 1000);
|
||||
}
|
||||
|
||||
|
@ -474,7 +476,7 @@ static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, int len,
|
|||
int optype)
|
||||
{
|
||||
u32 val = 0, status;
|
||||
u16 preop;
|
||||
u8 atomic_preopcode;
|
||||
int ret;
|
||||
|
||||
ret = intel_spi_opcode_index(ispi, opcode, optype);
|
||||
|
@ -484,17 +486,42 @@ static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, int len,
|
|||
if (len > INTEL_SPI_FIFO_SZ)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* Always clear it after each SW sequencer operation regardless
|
||||
* of whether it is successful or not.
|
||||
*/
|
||||
atomic_preopcode = ispi->atomic_preopcode;
|
||||
ispi->atomic_preopcode = 0;
|
||||
|
||||
/* Only mark 'Data Cycle' bit when there is data to be transferred */
|
||||
if (len > 0)
|
||||
val = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS;
|
||||
val |= ret << SSFSTS_CTL_COP_SHIFT;
|
||||
val |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE;
|
||||
val |= SSFSTS_CTL_SCGO;
|
||||
preop = readw(ispi->sregs + PREOP_OPTYPE);
|
||||
if (preop) {
|
||||
val |= SSFSTS_CTL_ACS;
|
||||
if (preop >> 8)
|
||||
val |= SSFSTS_CTL_SPOP;
|
||||
if (atomic_preopcode) {
|
||||
u16 preop;
|
||||
|
||||
switch (optype) {
|
||||
case OPTYPE_WRITE_NO_ADDR:
|
||||
case OPTYPE_WRITE_WITH_ADDR:
|
||||
/* Pick matching preopcode for the atomic sequence */
|
||||
preop = readw(ispi->sregs + PREOP_OPTYPE);
|
||||
if ((preop & 0xff) == atomic_preopcode)
|
||||
; /* Do nothing */
|
||||
else if ((preop >> 8) == atomic_preopcode)
|
||||
val |= SSFSTS_CTL_SPOP;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
/* Enable atomic sequence */
|
||||
val |= SSFSTS_CTL_ACS;
|
||||
break;
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
}
|
||||
writel(val, ispi->sregs + SSFSTS_CTL);
|
||||
|
||||
|
@ -538,13 +565,31 @@ static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
|
|||
|
||||
/*
|
||||
* This is handled with atomic operation and preop code in Intel
|
||||
* controller so skip it here now. If the controller is not locked,
|
||||
* program the opcode to the PREOP register for later use.
|
||||
* controller so we only verify that it is available. If the
|
||||
* controller is not locked, program the opcode to the PREOP
|
||||
* register for later use.
|
||||
*
|
||||
* When hardware sequencer is used there is no need to program
|
||||
* any opcodes (it handles them automatically as part of a command).
|
||||
*/
|
||||
if (opcode == SPINOR_OP_WREN) {
|
||||
if (!ispi->locked)
|
||||
writel(opcode, ispi->sregs + PREOP_OPTYPE);
|
||||
u16 preop;
|
||||
|
||||
if (!ispi->swseq_reg)
|
||||
return 0;
|
||||
|
||||
preop = readw(ispi->sregs + PREOP_OPTYPE);
|
||||
if ((preop & 0xff) != opcode && (preop >> 8) != opcode) {
|
||||
if (ispi->locked)
|
||||
return -EINVAL;
|
||||
writel(opcode, ispi->sregs + PREOP_OPTYPE);
|
||||
}
|
||||
|
||||
/*
|
||||
* This enables atomic sequence on next SW sycle. Will
|
||||
* be cleared after next operation.
|
||||
*/
|
||||
ispi->atomic_preopcode = opcode;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -569,6 +614,13 @@ static ssize_t intel_spi_read(struct spi_nor *nor, loff_t from, size_t len,
|
|||
u32 val, status;
|
||||
ssize_t ret;
|
||||
|
||||
/*
|
||||
* Atomic sequence is not expected with HW sequencer reads. Make
|
||||
* sure it is cleared regardless.
|
||||
*/
|
||||
if (WARN_ON_ONCE(ispi->atomic_preopcode))
|
||||
ispi->atomic_preopcode = 0;
|
||||
|
||||
switch (nor->read_opcode) {
|
||||
case SPINOR_OP_READ:
|
||||
case SPINOR_OP_READ_FAST:
|
||||
|
@ -627,6 +679,9 @@ static ssize_t intel_spi_write(struct spi_nor *nor, loff_t to, size_t len,
|
|||
u32 val, status;
|
||||
ssize_t ret;
|
||||
|
||||
/* Not needed with HW sequencer write, make sure it is cleared */
|
||||
ispi->atomic_preopcode = 0;
|
||||
|
||||
while (len > 0) {
|
||||
block_size = min_t(size_t, len, INTEL_SPI_FIFO_SZ);
|
||||
|
||||
|
@ -707,6 +762,9 @@ static int intel_spi_erase(struct spi_nor *nor, loff_t offs)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* Not needed with HW sequencer erase, make sure it is cleared */
|
||||
ispi->atomic_preopcode = 0;
|
||||
|
||||
while (len > 0) {
|
||||
writel(offs, ispi->base + FADDR);
|
||||
|
||||
|
|
|
@ -284,6 +284,20 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
|
|||
if (need_wren)
|
||||
write_disable(nor);
|
||||
|
||||
if (!status && !enable &&
|
||||
JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
|
||||
/*
|
||||
* On Winbond W25Q256FV, leaving 4byte mode causes
|
||||
* the Extended Address Register to be set to 1, so all
|
||||
* 3-byte-address reads come from the second 16M.
|
||||
* We must clear the register to enable normal behavior.
|
||||
*/
|
||||
write_enable(nor);
|
||||
nor->cmd_buf[0] = 0;
|
||||
nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
|
||||
write_disable(nor);
|
||||
}
|
||||
|
||||
return status;
|
||||
default:
|
||||
/* Spansion style */
|
||||
|
@ -980,6 +994,7 @@ static const struct flash_info spi_nor_ids[] = {
|
|||
{ "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
|
||||
{ "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
|
||||
{ "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
|
||||
{ "en25qh32", INFO(0x1c7016, 0, 64 * 1024, 64, 0) },
|
||||
{ "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
|
||||
{ "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
|
||||
{ "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
|
||||
|
@ -1049,6 +1064,14 @@ static const struct flash_info spi_nor_ids[] = {
|
|||
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
{ "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256,
|
||||
SECT_4K | SPI_NOR_DUAL_READ) },
|
||||
{ "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512,
|
||||
SECT_4K | SPI_NOR_DUAL_READ) },
|
||||
{ "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64,
|
||||
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
{ "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128,
|
||||
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
{ "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
|
||||
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
|
||||
/* Macronix */
|
||||
{ "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
|
||||
|
@ -1087,6 +1110,7 @@ static const struct flash_info spi_nor_ids[] = {
|
|||
{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
|
||||
{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
|
||||
{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
|
||||
{ "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
|
||||
|
||||
/* PMC */
|
||||
{ "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
|
||||
|
@ -1198,6 +1222,11 @@ static const struct flash_info spi_nor_ids[] = {
|
|||
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
||||
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
|
||||
},
|
||||
{
|
||||
"w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64,
|
||||
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
||||
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
|
||||
},
|
||||
{ "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
|
||||
{ "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
|
||||
{
|
||||
|
@ -1230,6 +1259,10 @@ static const struct flash_info spi_nor_ids[] = {
|
|||
{ "3S400AN", S3AN_INFO(0x1f2400, 256, 264) },
|
||||
{ "3S700AN", S3AN_INFO(0x1f2500, 512, 264) },
|
||||
{ "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) },
|
||||
|
||||
/* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
|
||||
{ "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
{ "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
|
||||
{ },
|
||||
};
|
||||
|
||||
|
|
|
@ -656,7 +656,7 @@ static int stm32_qspi_probe(struct platform_device *pdev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
rstc = devm_reset_control_get(dev, NULL);
|
||||
rstc = devm_reset_control_get_exclusive(dev, NULL);
|
||||
if (!IS_ERR(rstc)) {
|
||||
reset_control_assert(rstc);
|
||||
udelay(2);
|
||||
|
|
|
@ -62,6 +62,8 @@
|
|||
#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
|
||||
#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
|
||||
#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
|
||||
#define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
|
||||
#define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
|
||||
|
||||
/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
|
||||
#define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
|
||||
|
|
Loading…
Add table
Reference in a new issue