From 2f98ca895198c1c6f5c9f418e1bbf84660d9ba4f Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Fri, 14 Dec 2012 11:36:40 +0100 Subject: [PATCH 01/11] ARM: OMAP: gpmc: don't create devices from initcall on DT On DT driven boards, the gpmc node will match the driver. Hence, there's no need to do that unconditionally from the initcall. Signed-off-by: Daniel Mack Acked-by: Grant Likely Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 8033cb747c86..1f0ec79aabf1 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -1214,6 +1214,13 @@ static int __init omap_gpmc_init(void) struct platform_device *pdev; char *oh_name = "gpmc"; + /* + * if the board boots up with a populated DT, do not + * manually add the device from this initcall + */ + if (of_have_populated_dt()) + return -ENODEV; + oh = omap_hwmod_lookup(oh_name); if (!oh) { pr_err("Could not look up %s\n", oh_name); From ccf04c51004d0b973a688a91c879e2d91780d03c Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Fri, 14 Dec 2012 11:36:41 +0100 Subject: [PATCH 02/11] mtd: omap-nand: pass device_node in platform data Pass an optional device_node pointer in the platform data, which in turn will be put into a mtd_part_parser_data. This way, code that sets up the platform devices can pass along the node from DT so that the partitions can be parsed. For non-DT boards, this change has no effect. Signed-off-by: Daniel Mack Acked-by: Grant Likely Acked-by: Artem Bityutskiy Signed-off-by: Tony Lindgren --- drivers/mtd/nand/omap2.c | 4 +++- include/linux/platform_data/mtd-nand-omap2.h | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 0002d5e94f0d..1d333497cfcb 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -1332,6 +1332,7 @@ static int omap_nand_probe(struct platform_device *pdev) dma_cap_mask_t mask; unsigned sig; struct resource *res; + struct mtd_part_parser_data ppdata = {}; pdata = pdev->dev.platform_data; if (pdata == NULL) { @@ -1557,7 +1558,8 @@ static int omap_nand_probe(struct platform_device *pdev) goto out_release_mem_region; } - mtd_device_parse_register(&info->mtd, NULL, NULL, pdata->parts, + ppdata.of_node = pdata->of_node; + mtd_device_parse_register(&info->mtd, NULL, &ppdata, pdata->parts, pdata->nr_parts); platform_set_drvdata(pdev, &info->mtd); diff --git a/include/linux/platform_data/mtd-nand-omap2.h b/include/linux/platform_data/mtd-nand-omap2.h index 24d32ca34bef..6bf9ef43ddb1 100644 --- a/include/linux/platform_data/mtd-nand-omap2.h +++ b/include/linux/platform_data/mtd-nand-omap2.h @@ -60,6 +60,8 @@ struct omap_nand_platform_data { int devsize; enum omap_ecc ecc_opt; struct gpmc_nand_regs reg; -}; + /* for passing the partitions */ + struct device_node *of_node; +}; #endif From 504f3c6d73650d2afeabb86e29bfeb465f2b15df Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Fri, 14 Dec 2012 11:36:42 +0100 Subject: [PATCH 03/11] ARM: OMAP: gpmc-nand: drop __init annotation gpmc_nand_init() will be called from another driver's probe() function, so the easiest way to prevent section mismatches is to drop the annotation here. Signed-off-by: Daniel Mack Acked-by: Grant Likely Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc-nand.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index db969a5c4998..3059f5e8ee85 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -89,7 +89,7 @@ static int omap2_nand_gpmc_retime( return 0; } -static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) +static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) { /* support only OMAP3 class */ if (!cpu_is_omap34xx()) { @@ -110,8 +110,8 @@ static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) return 1; } -int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, - struct gpmc_timings *gpmc_t) +int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, + struct gpmc_timings *gpmc_t) { int err = 0; struct device *dev = &gpmc_nand_device.dev; From f50a0380897d2a5e61b251b07c50ee48fa298cfd Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Fri, 14 Dec 2012 11:36:43 +0100 Subject: [PATCH 04/11] ARM: OMAP: gpmc: enable hwecc for AM33xx SoCs The am33xx is capable of handling bch error correction modes, so enable that feature in the driver. Signed-off-by: Daniel Mack Acked-by: Grant Likely Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc-nand.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 3059f5e8ee85..afc1e8c32d6c 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -92,17 +92,18 @@ static int omap2_nand_gpmc_retime( static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) { /* support only OMAP3 class */ - if (!cpu_is_omap34xx()) { + if (!cpu_is_omap34xx() && !soc_is_am33xx()) { pr_err("BCH ecc is not supported on this CPU\n"); return 0; } /* - * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1. - * Other chips may be added if confirmed to work. + * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1 + * and AM33xx derivates. Other chips may be added if confirmed to work. */ if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) && - (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) { + (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) && + (!soc_is_am33xx())) { pr_err("BCH 4-bit mode is not supported on this CPU\n"); return 0; } From bc6b1e7b86f5d8e4a6fc1c0189e64bba4077efe0 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Fri, 14 Dec 2012 11:36:44 +0100 Subject: [PATCH 05/11] ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND This patch adds basic DT bindings for OMAP GPMC. The actual peripherals are instantiated from child nodes within the GPMC node, and the only type of device that is currently supported is NAND. Code was added to parse the generic GPMC timing parameters and some documentation with examples on how to use them. Successfully tested on an AM33xx board. Signed-off-by: Daniel Mack Acked-by: Grant Likely [tony@atomide.com: updated to apply] Signed-off-by: Tony Lindgren --- .../devicetree/bindings/bus/ti-gpmc.txt | 84 +++++++++ .../devicetree/bindings/mtd/gpmc-nand.txt | 76 ++++++++ arch/arm/mach-omap2/gpmc.c | 173 ++++++++++++++++++ 3 files changed, 333 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/ti-gpmc.txt create mode 100644 Documentation/devicetree/bindings/mtd/gpmc-nand.txt diff --git a/Documentation/devicetree/bindings/bus/ti-gpmc.txt b/Documentation/devicetree/bindings/bus/ti-gpmc.txt new file mode 100644 index 000000000000..5ddb2e9efaaa --- /dev/null +++ b/Documentation/devicetree/bindings/bus/ti-gpmc.txt @@ -0,0 +1,84 @@ +Device tree bindings for OMAP general purpose memory controllers (GPMC) + +The actual devices are instantiated from the child nodes of a GPMC node. + +Required properties: + + - compatible: Should be set to one of the following: + + ti,omap2420-gpmc (omap2420) + ti,omap2430-gpmc (omap2430) + ti,omap3430-gpmc (omap3430 & omap3630) + ti,omap4430-gpmc (omap4430 & omap4460 & omap543x) + ti,am3352-gpmc (am335x devices) + + - reg: A resource specifier for the register space + (see the example below) + - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is + completed. + - #address-cells: Must be set to 2 to allow memory address translation + - #size-cells: Must be set to 1 to allow CS address passing + - gpmc,num-cs: The maximum number of chip-select lines that controller + can support. + - gpmc,num-waitpins: The maximum number of wait pins that controller can + support. + - ranges: Must be set up to reflect the memory layout with four + integer values for each chip-select line in use: + + 0 + + Currently, calculated values derived from the contents + of the per-CS register GPMC_CONFIG7 (as set up by the + bootloader) are used for the physical address decoding. + As this will change in the future, filling correct + values here is a requirement. + +Timing properties for child nodes. All are optional and default to 0. + + - gpmc,sync-clk: Minimum clock period for synchronous mode, in picoseconds + + Chip-select signal timings corresponding to GPMC_CONFIG2: + - gpmc,cs-on: Assertion time + - gpmc,cs-rd-off: Read deassertion time + - gpmc,cs-wr-off: Write deassertion time + + ADV signal timings corresponding to GPMC_CONFIG3: + - gpmc,adv-on: Assertion time + - gpmc,adv-rd-off: Read deassertion time + - gpmc,adv-wr-off: Write deassertion time + + WE signals timings corresponding to GPMC_CONFIG4: + - gpmc,we-on: Assertion time + - gpmc,we-off: Deassertion time + + OE signals timings corresponding to GPMC_CONFIG4: + - gpmc,oe-on: Assertion time + - gpmc,oe-off: Deassertion time + + Access time and cycle time timings corresponding to GPMC_CONFIG5: + - gpmc,page-burst-access: Multiple access word delay + - gpmc,access: Start-cycle to first data valid delay + - gpmc,rd-cycle: Total read cycle time + - gpmc,wr-cycle: Total write cycle time + +The following are only applicable to OMAP3+ and AM335x: + - gpmc,wr-access + - gpmc,wr-data-mux-bus + + +Example for an AM33xx board: + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x50000000 0x2000>; + interrupts = <100>; + + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */ + + /* child nodes go here */ + }; diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt new file mode 100644 index 000000000000..9f464f906ffb --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt @@ -0,0 +1,76 @@ +Device tree bindings for GPMC connected NANDs + +GPMC connected NAND (found on OMAP boards) are represented as child nodes of +the GPMC controller with a name of "nand". + +All timing relevant properties as well as generic gpmc child properties are +explained in a separate documents - please refer to +Documentation/devicetree/bindings/bus/ti-gpmc.txt + +For NAND specific properties such as ECC modes or bus width, please refer to +Documentation/devicetree/bindings/mtd/nand.txt + + +Required properties: + + - reg: The CS line the peripheral is connected to + +Optional properties: + + - nand-bus-width: Set this numeric value to 16 if the hardware + is wired that way. If not specified, a bus + width of 8 is assumed. + + - ti,nand-ecc-opt: A string setting the ECC layout to use. One of: + + "sw" Software method (default) + "hw" Hardware method + "hw-romcode" gpmc hamming mode method & romcode layout + "bch4" 4-bit BCH ecc code + "bch8" 8-bit BCH ecc code + +For inline partiton table parsing (optional): + + - #address-cells: should be set to 1 + - #size-cells: should be set to 1 + +Example for an AM33xx board: + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x50000000 0x1000000>; + interrupts = <100>; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x2000>; /* CS0: NAND */ + + nand@0,0 { + reg = <0 0 0>; /* CS0, offset 0 */ + nand-bus-width = <16>; + ti,nand-ecc-opt = "bch8"; + + gpmc,sync-clk = <0>; + gpmc,cs-on = <0>; + gpmc,cs-rd-off = <44>; + gpmc,cs-wr-off = <44>; + gpmc,adv-on = <6>; + gpmc,adv-rd-off = <34>; + gpmc,adv-wr-off = <44>; + gpmc,we-off = <40>; + gpmc,oe-off = <54>; + gpmc,access = <64>; + gpmc,rd-cycle = <82>; + gpmc,wr-cycle = <82>; + gpmc,wr-access = <40>; + gpmc,wr-data-mux-bus = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + /* partitions go here */ + }; + }; + diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 1f0ec79aabf1..01ce462e265d 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -25,6 +25,10 @@ #include #include #include +#include +#include +#include +#include #include @@ -34,6 +38,7 @@ #include "common.h" #include "omap_device.h" #include "gpmc.h" +#include "gpmc-nand.h" #define DEVICE_NAME "omap-gpmc" @@ -1121,6 +1126,165 @@ int gpmc_calc_timings(struct gpmc_timings *gpmc_t, return 0; } +#ifdef CONFIG_OF +static struct of_device_id gpmc_dt_ids[] = { + { .compatible = "ti,omap2420-gpmc" }, + { .compatible = "ti,omap2430-gpmc" }, + { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */ + { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */ + { .compatible = "ti,am3352-gpmc" }, /* am335x devices */ + { } +}; +MODULE_DEVICE_TABLE(of, gpmc_dt_ids); + +static void __maybe_unused gpmc_read_timings_dt(struct device_node *np, + struct gpmc_timings *gpmc_t) +{ + u32 val; + + memset(gpmc_t, 0, sizeof(*gpmc_t)); + + /* minimum clock period for syncronous mode */ + if (!of_property_read_u32(np, "gpmc,sync-clk", &val)) + gpmc_t->sync_clk = val; + + /* chip select timtings */ + if (!of_property_read_u32(np, "gpmc,cs-on", &val)) + gpmc_t->cs_on = val; + + if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val)) + gpmc_t->cs_rd_off = val; + + if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val)) + gpmc_t->cs_wr_off = val; + + /* ADV signal timings */ + if (!of_property_read_u32(np, "gpmc,adv-on", &val)) + gpmc_t->adv_on = val; + + if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val)) + gpmc_t->adv_rd_off = val; + + if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val)) + gpmc_t->adv_wr_off = val; + + /* WE signal timings */ + if (!of_property_read_u32(np, "gpmc,we-on", &val)) + gpmc_t->we_on = val; + + if (!of_property_read_u32(np, "gpmc,we-off", &val)) + gpmc_t->we_off = val; + + /* OE signal timings */ + if (!of_property_read_u32(np, "gpmc,oe-on", &val)) + gpmc_t->oe_on = val; + + if (!of_property_read_u32(np, "gpmc,oe-off", &val)) + gpmc_t->oe_off = val; + + /* access and cycle timings */ + if (!of_property_read_u32(np, "gpmc,page-burst-access", &val)) + gpmc_t->page_burst_access = val; + + if (!of_property_read_u32(np, "gpmc,access", &val)) + gpmc_t->access = val; + + if (!of_property_read_u32(np, "gpmc,rd-cycle", &val)) + gpmc_t->rd_cycle = val; + + if (!of_property_read_u32(np, "gpmc,wr-cycle", &val)) + gpmc_t->wr_cycle = val; + + /* only for OMAP3430 */ + if (!of_property_read_u32(np, "gpmc,wr-access", &val)) + gpmc_t->wr_access = val; + + if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val)) + gpmc_t->wr_data_mux_bus = val; +} + +#ifdef CONFIG_MTD_NAND + +static const char * const nand_ecc_opts[] = { + [OMAP_ECC_HAMMING_CODE_DEFAULT] = "sw", + [OMAP_ECC_HAMMING_CODE_HW] = "hw", + [OMAP_ECC_HAMMING_CODE_HW_ROMCODE] = "hw-romcode", + [OMAP_ECC_BCH4_CODE_HW] = "bch4", + [OMAP_ECC_BCH8_CODE_HW] = "bch8", +}; + +static int gpmc_probe_nand_child(struct platform_device *pdev, + struct device_node *child) +{ + u32 val; + const char *s; + struct gpmc_timings gpmc_t; + struct omap_nand_platform_data *gpmc_nand_data; + + if (of_property_read_u32(child, "reg", &val) < 0) { + dev_err(&pdev->dev, "%s has no 'reg' property\n", + child->full_name); + return -ENODEV; + } + + gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data), + GFP_KERNEL); + if (!gpmc_nand_data) + return -ENOMEM; + + gpmc_nand_data->cs = val; + gpmc_nand_data->of_node = child; + + if (!of_property_read_string(child, "ti,nand-ecc-opt", &s)) + for (val = 0; val < ARRAY_SIZE(nand_ecc_opts); val++) + if (!strcasecmp(s, nand_ecc_opts[val])) { + gpmc_nand_data->ecc_opt = val; + break; + } + + val = of_get_nand_bus_width(child); + if (val == 16) + gpmc_nand_data->devsize = NAND_BUSWIDTH_16; + + gpmc_read_timings_dt(child, &gpmc_t); + gpmc_nand_init(gpmc_nand_data, &gpmc_t); + + return 0; +} +#else +static int gpmc_probe_nand_child(struct platform_device *pdev, + struct device_node *child) +{ + return 0; +} +#endif + +static int gpmc_probe_dt(struct platform_device *pdev) +{ + int ret; + struct device_node *child; + const struct of_device_id *of_id = + of_match_device(gpmc_dt_ids, &pdev->dev); + + if (!of_id) + return 0; + + for_each_node_by_name(child, "nand") { + ret = gpmc_probe_nand_child(pdev, child); + of_node_put(child); + if (ret < 0) + return ret; + } + + return 0; +} +#else +static int gpmc_probe_dt(struct platform_device *pdev) +{ + return 0; +} +#endif + static int gpmc_probe(struct platform_device *pdev) { int rc; @@ -1174,6 +1338,14 @@ static int gpmc_probe(struct platform_device *pdev) if (IS_ERR_VALUE(gpmc_setup_irq())) dev_warn(gpmc_dev, "gpmc_setup_irq failed\n"); + rc = gpmc_probe_dt(pdev); + if (rc < 0) { + clk_disable_unprepare(gpmc_l3_clk); + clk_put(gpmc_l3_clk); + dev_err(gpmc_dev, "failed to probe DT parameters\n"); + return rc; + } + return 0; } @@ -1191,6 +1363,7 @@ static struct platform_driver gpmc_driver = { .driver = { .name = DEVICE_NAME, .owner = THIS_MODULE, + .of_match_table = of_match_ptr(gpmc_dt_ids), }, }; From a16723709cff6d69567024c28d32d1344f08cecf Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 25 Jan 2013 09:19:47 -0300 Subject: [PATCH 06/11] ARM: OMAP2+: gpmc: Remove unneeded of_node_put() for_each_node_by_name() automatically calls of_node_put() on each node passed; so don't do it explicitly unless there's an error. Reported-by: Mark Rutland Signed-off-by: Ezequiel Garcia Acked-by: Jon Hunter Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 01ce462e265d..c6255f788ab2 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -1271,9 +1271,10 @@ static int gpmc_probe_dt(struct platform_device *pdev) for_each_node_by_name(child, "nand") { ret = gpmc_probe_nand_child(pdev, child); - of_node_put(child); - if (ret < 0) + if (ret < 0) { + of_node_put(child); return ret; + } } return 0; From 6797b4fe0e554ce71f47038fd929c9ca929a9f3c Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Fri, 1 Feb 2013 10:38:45 -0600 Subject: [PATCH 07/11] ARM: OMAP2+: Prevent potential crash if GPMC probe fails If the GPMC probe fails, devices that use the GPMC (such as ethernet chips, flash memories, etc) can still allocate a GPMC chip-select and register the device. On the OMAP2420 H4 board, this was causing the kernel to crash after the gpmc probe failed and the board attempted to start networking. Prevent this by marking all the chip-selects as reserved by default and only make them available for devices to request if the GPMC probe succeeds. Signed-off-by: Jon Hunter Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index c6255f788ab2..0cf239231d36 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -150,7 +150,8 @@ static unsigned gpmc_irq_start; static struct resource gpmc_mem_root; static struct resource gpmc_cs_mem[GPMC_CS_NUM]; static DEFINE_SPINLOCK(gpmc_mem_lock); -static unsigned int gpmc_cs_map; /* flag for cs which are initialized */ +/* Define chip-selects as reserved by default until probe completes */ +static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1); static struct device *gpmc_dev; static int gpmc_irq; static resource_size_t phys_base, mem_size; @@ -1123,6 +1124,9 @@ int gpmc_calc_timings(struct gpmc_timings *gpmc_t, /* TODO: remove, see function definition */ gpmc_convert_ps_to_ns(gpmc_t); + /* Now the GPMC is initialised, unreserve the chip-selects */ + gpmc_cs_map = 0; + return 0; } From dc75eb36c3233409728e88acfd6b45a223856289 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 25 Jan 2013 09:23:09 -0300 Subject: [PATCH 08/11] mtd: omap-onenand: pass device_node in platform data Pass an optional device_node pointer in the platform data, which in turn will be put into a mtd_part_parser_data. This way, code that sets up the platform devices can pass along the node from DT so that the partitions can be parsed. For non-DT boards, this change has no effect. Acked-by: Artem Bityutskiy Signed-off-by: Ezequiel Garcia Signed-off-by: Tony Lindgren --- drivers/mtd/onenand/omap2.c | 4 +++- include/linux/platform_data/mtd-onenand-omap2.h | 3 +++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c index 065f3fe02a2f..eec2aedb4ab8 100644 --- a/drivers/mtd/onenand/omap2.c +++ b/drivers/mtd/onenand/omap2.c @@ -637,6 +637,7 @@ static int omap2_onenand_probe(struct platform_device *pdev) struct onenand_chip *this; int r; struct resource *res; + struct mtd_part_parser_data ppdata = {}; pdata = pdev->dev.platform_data; if (pdata == NULL) { @@ -767,7 +768,8 @@ static int omap2_onenand_probe(struct platform_device *pdev) if ((r = onenand_scan(&c->mtd, 1)) < 0) goto err_release_regulator; - r = mtd_device_parse_register(&c->mtd, NULL, NULL, + ppdata.of_node = pdata->of_node; + r = mtd_device_parse_register(&c->mtd, NULL, &ppdata, pdata ? pdata->parts : NULL, pdata ? pdata->nr_parts : 0); if (r) diff --git a/include/linux/platform_data/mtd-onenand-omap2.h b/include/linux/platform_data/mtd-onenand-omap2.h index 685af7e8b120..e9a9fb188f97 100644 --- a/include/linux/platform_data/mtd-onenand-omap2.h +++ b/include/linux/platform_data/mtd-onenand-omap2.h @@ -29,5 +29,8 @@ struct omap_onenand_platform_data { u8 flags; u8 regulator_can_sleep; u8 skip_initial_unlocking; + + /* for passing the partitions */ + struct device_node *of_node; }; #endif From faf5d2ff82154b3e2d30c9bfdab2ea4e089b24d5 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 25 Jan 2013 09:23:10 -0300 Subject: [PATCH 09/11] ARM: OMAP2+: gpmc-onenand: drop __init annotation gpmc_onenand_init() will be called from another driver's probe() function, so drop the __init annotation, in order to prevent section mismatches. Signed-off-by: Ezequiel Garcia Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc-onenand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index 94a349e4dc96..fadd87435cd0 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c @@ -356,7 +356,7 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr) return ret; } -void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) +void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) { int err; From 75d3625e0e86b2d8d77b4e9c6f685fd7ea0d5a96 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 25 Jan 2013 09:23:11 -0300 Subject: [PATCH 10/11] ARM: OMAP2+: gpmc: add DT bindings for OneNAND This patch adds device tree bindings for OMAP OneNAND devices. Tested on an OMAP3 3430 IGEPv2 board. Signed-off-by: Ezequiel Garcia Signed-off-by: Tony Lindgren --- .../devicetree/bindings/mtd/gpmc-onenand.txt | 43 ++++++++++++++++++ arch/arm/mach-omap2/gpmc.c | 45 +++++++++++++++++++ 2 files changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/gpmc-onenand.txt diff --git a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt new file mode 100644 index 000000000000..deec9da224a2 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt @@ -0,0 +1,43 @@ +Device tree bindings for GPMC connected OneNANDs + +GPMC connected OneNAND (found on OMAP boards) are represented as child nodes of +the GPMC controller with a name of "onenand". + +All timing relevant properties as well as generic gpmc child properties are +explained in a separate documents - please refer to +Documentation/devicetree/bindings/bus/ti-gpmc.txt + +Required properties: + + - reg: The CS line the peripheral is connected to + +Optional properties: + + - dma-channel: DMA Channel index + +For inline partiton table parsing (optional): + + - #address-cells: should be set to 1 + - #size-cells: should be set to 1 + +Example for an OMAP3430 board: + + gpmc: gpmc@6e000000 { + compatible = "ti,omap3430-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x6e000000 0x1000000>; + interrupts = <20>; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <4>; + #address-cells = <2>; + #size-cells = <1>; + + onenand@0 { + reg = <0 0 0>; /* CS0, offset 0 */ + + #address-cells = <1>; + #size-cells = <1>; + + /* partitions go here */ + }; + }; diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 0cf239231d36..1adb2d4496f6 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -39,6 +39,7 @@ #include "omap_device.h" #include "gpmc.h" #include "gpmc-nand.h" +#include "gpmc-onenand.h" #define DEVICE_NAME "omap-gpmc" @@ -1263,6 +1264,43 @@ static int gpmc_probe_nand_child(struct platform_device *pdev, } #endif +#ifdef CONFIG_MTD_ONENAND +static int gpmc_probe_onenand_child(struct platform_device *pdev, + struct device_node *child) +{ + u32 val; + struct omap_onenand_platform_data *gpmc_onenand_data; + + if (of_property_read_u32(child, "reg", &val) < 0) { + dev_err(&pdev->dev, "%s has no 'reg' property\n", + child->full_name); + return -ENODEV; + } + + gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data), + GFP_KERNEL); + if (!gpmc_onenand_data) + return -ENOMEM; + + gpmc_onenand_data->cs = val; + gpmc_onenand_data->of_node = child; + gpmc_onenand_data->dma_channel = -1; + + if (!of_property_read_u32(child, "dma-channel", &val)) + gpmc_onenand_data->dma_channel = val; + + gpmc_onenand_init(gpmc_onenand_data); + + return 0; +} +#else +static int gpmc_probe_onenand_child(struct platform_device *pdev, + struct device_node *child) +{ + return 0; +} +#endif + static int gpmc_probe_dt(struct platform_device *pdev) { int ret; @@ -1281,6 +1319,13 @@ static int gpmc_probe_dt(struct platform_device *pdev) } } + for_each_node_by_name(child, "onenand") { + ret = gpmc_probe_onenand_child(pdev, child); + if (ret < 0) { + of_node_put(child); + return ret; + } + } return 0; } #else From 97c794a1e37b1ca128ef38f17c069186bfa5fb1b Mon Sep 17 00:00:00 2001 From: Philip Avinash Date: Fri, 18 Jan 2013 10:27:46 +0530 Subject: [PATCH 11/11] ARM: OMAP2+: gpmc: Add device tree documentation for elm handle In case ELM module available, omap2 NAND driver can opt for hardware correction method for bit flip errors in NAND flash with BCH. Hence the detection of ELM module is done through devicetree population of elm_id. This patch update device tree documentation for gpmc-nand for elm-id data population. Signed-off-by: Philip Avinash Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt index 9f464f906ffb..e7f8d7ed47eb 100644 --- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt +++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt @@ -29,6 +29,9 @@ Optional properties: "bch4" 4-bit BCH ecc code "bch8" 8-bit BCH ecc code + - elm_id: Specifies elm device node. This is required to support BCH + error correction using ELM module. + For inline partiton table parsing (optional): - #address-cells: should be set to 1 @@ -46,6 +49,7 @@ Example for an AM33xx board: #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0x08000000 0x2000>; /* CS0: NAND */ + elm_id = <&elm>; nand@0,0 { reg = <0 0 0>; /* CS0, offset 0 */