MIPS: cps-vec: Use macros for various arithmetics and memory operations
Replace lw/sw and various arithmetic instructions with macros so the code can work on 64-bit kernels as well. Cc: <stable@vger.kernel.org> # 3.16+ Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10591/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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1 changed files with 16 additions and 16 deletions
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@ -108,9 +108,9 @@ not_nmi:
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mul t1, t1, t2
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li a0, CKSEG0
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add a1, a0, t1
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PTR_ADD a1, a0, t1
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1: cache Index_Store_Tag_I, 0(a0)
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add a0, a0, t0
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PTR_ADD a0, a0, t0
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bne a0, a1, 1b
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nop
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icache_done:
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@ -135,11 +135,11 @@ icache_done:
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mul t1, t1, t2
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li a0, CKSEG0
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addu a1, a0, t1
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subu a1, a1, t0
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PTR_ADDU a1, a0, t1
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PTR_SUBU a1, a1, t0
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1: cache Index_Store_Tag_D, 0(a0)
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bne a0, a1, 1b
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add a0, a0, t0
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PTR_ADD a0, a0, t0
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dcache_done:
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/* Set Kseg0 CCA to that in s0 */
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@ -152,7 +152,7 @@ dcache_done:
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/* Enter the coherent domain */
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li t0, 0xff
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sw t0, GCR_CL_COHERENCE_OFS(v1)
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PTR_S t0, GCR_CL_COHERENCE_OFS(v1)
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ehb
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/* Jump to kseg0 */
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@ -178,9 +178,9 @@ dcache_done:
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nop
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/* Off we go! */
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lw t1, VPEBOOTCFG_PC(v0)
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lw gp, VPEBOOTCFG_GP(v0)
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lw sp, VPEBOOTCFG_SP(v0)
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PTR_L t1, VPEBOOTCFG_PC(v0)
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PTR_L gp, VPEBOOTCFG_GP(v0)
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PTR_L sp, VPEBOOTCFG_SP(v0)
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jr t1
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nop
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END(mips_cps_core_entry)
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@ -299,15 +299,15 @@ LEAF(mips_cps_core_init)
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LEAF(mips_cps_boot_vpes)
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/* Retrieve CM base address */
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PTR_LA t0, mips_cm_base
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lw t0, 0(t0)
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PTR_L t0, 0(t0)
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/* Calculate a pointer to this cores struct core_boot_config */
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lw t0, GCR_CL_ID_OFS(t0)
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PTR_L t0, GCR_CL_ID_OFS(t0)
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li t1, COREBOOTCFG_SIZE
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mul t0, t0, t1
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PTR_LA t1, mips_cps_core_bootcfg
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lw t1, 0(t1)
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addu t0, t0, t1
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PTR_L t1, 0(t1)
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PTR_ADDU t0, t0, t1
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/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
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has_mt ta2, 1f
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@ -334,8 +334,8 @@ LEAF(mips_cps_boot_vpes)
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1: /* Calculate a pointer to this VPEs struct vpe_boot_config */
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li t1, VPEBOOTCFG_SIZE
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mul v0, t9, t1
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lw ta3, COREBOOTCFG_VPECONFIG(t0)
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addu v0, v0, ta3
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PTR_L ta3, COREBOOTCFG_VPECONFIG(t0)
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PTR_ADDU v0, v0, ta3
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#ifdef CONFIG_MIPS_MT
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@ -360,7 +360,7 @@ LEAF(mips_cps_boot_vpes)
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ehb
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/* Loop through each VPE */
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lw ta2, COREBOOTCFG_VPEMASK(t0)
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PTR_L ta2, COREBOOTCFG_VPEMASK(t0)
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move t8, ta2
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li ta1, 0
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