perf/x86/intel: Enforce HT bug workaround with PEBS for SNB/IVB/HSW
This patch modifies the PEBS constraint tables for SNB/IVB/HSW such that corrupting events supporting PEBS activate the HT workaround. Signed-off-by: Maria Dimakopoulou <maria.n.dimakopoulou@gmail.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Stephane Eranian <eranian@google.com> Cc: bp@alien8.de Cc: jolsa@redhat.com Cc: kan.liang@intel.com Link: http://lkml.kernel.org/r/1416251225-17721-9-git-send-email-eranian@google.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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2 changed files with 37 additions and 11 deletions
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@ -330,18 +330,36 @@ struct cpu_hw_events {
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ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
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HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
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#define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \
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__EVENT_CONSTRAINT(code, n, \
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ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
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HWEIGHT(n), 0, \
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PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
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/* Check flags and event code/umask, and set the HSW store flag */
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#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \
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__EVENT_CONSTRAINT(code, n, \
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INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
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HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
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#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \
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__EVENT_CONSTRAINT(code, n, \
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INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
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HWEIGHT(n), 0, \
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PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL)
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/* Check flags and event code/umask, and set the HSW load flag */
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#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \
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__EVENT_CONSTRAINT(code, n, \
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INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
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HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
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#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \
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__EVENT_CONSTRAINT(code, n, \
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INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
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HWEIGHT(n), 0, \
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PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
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/* Check flags and event code/umask, and set the HSW N/A flag */
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#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
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__EVENT_CONSTRAINT(code, n, \
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@ -612,6 +612,10 @@ struct event_constraint intel_snb_pebs_event_constraints[] = {
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INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
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/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
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INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
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INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
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INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
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INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
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INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
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/* Allow all events as PEBS with no flags */
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INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
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EVENT_CONSTRAINT_END
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@ -623,6 +627,10 @@ struct event_constraint intel_ivb_pebs_event_constraints[] = {
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INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
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/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
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INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
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INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
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INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
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INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
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INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
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/* Allow all events as PEBS with no flags */
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INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
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EVENT_CONSTRAINT_END
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@ -634,16 +642,16 @@ struct event_constraint intel_hsw_pebs_event_constraints[] = {
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/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
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INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
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INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
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INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
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INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
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INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
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INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
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INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
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INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
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/* Allow all events as PEBS with no flags */
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INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
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EVENT_CONSTRAINT_END
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