tilegx: Add tty serial support for TILE-Gx on-chip UART
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Chris Metcalf
parent
6ec006ede5
commit
b5c6c1a72a
5 changed files with 722 additions and 0 deletions
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@ -8293,6 +8293,7 @@ F: drivers/edac/tile_edac.c
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F: drivers/net/ethernet/tile/
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F: drivers/rtc/rtc-tile.c
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F: drivers/tty/hvc/hvc_tile.c
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F: drivers/tty/serial/tilegx.c
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F: drivers/usb/host/*-tilegx.c
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F: include/linux/usb/tilegx.h
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@ -1436,6 +1436,15 @@ config SERIAL_EFM32_UART_CONSOLE
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depends on SERIAL_EFM32_UART=y
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select SERIAL_CORE_CONSOLE
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config SERIAL_TILEGX
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tristate "TILE-Gx on-chip serial port support"
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depends on TILEGX
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select TILE_GXIO_UART
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select SERIAL_CORE
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---help---
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This device provides access to the on-chip UARTs on the TILE-Gx
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processor.
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config SERIAL_ARC
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tristate "ARC UART driver support"
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select SERIAL_CORE
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@ -65,6 +65,7 @@ obj-$(CONFIG_SERIAL_KGDB_NMI) += kgdb_nmi.o
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obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
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obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o
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obj-$(CONFIG_SERIAL_ALTERA_UART) += altera_uart.o
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obj-$(CONFIG_SERIAL_TILEGX) += tilegx.o
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obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o
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obj-$(CONFIG_SERIAL_QE) += ucc_uart.o
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obj-$(CONFIG_SERIAL_TIMBERDALE) += timbuart.o
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708
drivers/tty/serial/tilegx.c
Normal file
708
drivers/tty/serial/tilegx.c
Normal file
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@ -0,0 +1,708 @@
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/*
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* Copyright 2013 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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* TILEGx UART driver.
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/serial_core.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <gxio/common.h>
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#include <gxio/iorpc_globals.h>
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#include <gxio/iorpc_uart.h>
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#include <gxio/kiorpc.h>
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#include <hv/drv_uart_intf.h>
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/*
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* Use device name ttyS, major 4, minor 64-65.
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* This is the usual serial port name, 8250 conventional range.
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*/
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#define TILEGX_UART_MAJOR TTY_MAJOR
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#define TILEGX_UART_MINOR 64
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#define TILEGX_UART_NAME "ttyS"
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#define DRIVER_NAME_STRING "TILEGx_Serial"
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#define TILEGX_UART_REF_CLK 125000000; /* REF_CLK is always 125 MHz. */
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struct tile_uart_port {
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/* UART port. */
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struct uart_port uart;
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/* GXIO device context. */
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gxio_uart_context_t context;
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/* UART access mutex. */
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struct mutex mutex;
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/* CPU receiving interrupts. */
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int irq_cpu;
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};
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static struct tile_uart_port tile_uart_ports[TILEGX_UART_NR];
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static struct uart_driver tilegx_uart_driver;
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/*
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* Read UART rx fifo, and insert the chars into tty buffer.
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*/
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static void receive_chars(struct tile_uart_port *tile_uart,
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struct tty_struct *tty)
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{
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int i;
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char c;
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UART_FIFO_COUNT_t count;
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gxio_uart_context_t *context = &tile_uart->context;
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struct tty_port *port = tty->port;
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count.word = gxio_uart_read(context, UART_FIFO_COUNT);
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for (i = 0; i < count.rfifo_count; i++) {
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c = (char)gxio_uart_read(context, UART_RECEIVE_DATA);
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tty_insert_flip_char(port, c, TTY_NORMAL);
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}
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}
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/*
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* Drain the Rx FIFO, called by interrupt handler.
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*/
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static void handle_receive(struct tile_uart_port *tile_uart)
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{
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struct tty_port *port = &tile_uart->uart.state->port;
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struct tty_struct *tty = tty_port_tty_get(port);
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gxio_uart_context_t *context = &tile_uart->context;
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if (!tty)
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return;
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/* First read UART rx fifo. */
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receive_chars(tile_uart, tty);
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/* Reset RFIFO_WE interrupt. */
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gxio_uart_write(context, UART_INTERRUPT_STATUS,
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UART_INTERRUPT_MASK__RFIFO_WE_MASK);
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/* Final read, if any chars comes between the first read and
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* the interrupt reset.
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*/
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receive_chars(tile_uart, tty);
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spin_unlock(&tile_uart->uart.lock);
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tty_flip_buffer_push(port);
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spin_lock(&tile_uart->uart.lock);
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tty_kref_put(tty);
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}
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/*
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* Push one char to UART Write FIFO.
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* Return 0 on success, -1 if write filo is full.
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*/
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static int tilegx_putchar(gxio_uart_context_t *context, char c)
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{
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UART_FLAG_t flag;
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flag.word = gxio_uart_read(context, UART_FLAG);
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if (flag.wfifo_full)
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return -1;
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gxio_uart_write(context, UART_TRANSMIT_DATA, (unsigned long)c);
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return 0;
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}
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/*
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* Send chars to UART Write FIFO; called by interrupt handler.
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*/
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static void handle_transmit(struct tile_uart_port *tile_uart)
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{
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unsigned char ch;
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struct uart_port *port;
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struct circ_buf *xmit;
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gxio_uart_context_t *context = &tile_uart->context;
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/* First reset WFIFO_RE interrupt. */
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gxio_uart_write(context, UART_INTERRUPT_STATUS,
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UART_INTERRUPT_MASK__WFIFO_RE_MASK);
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port = &tile_uart->uart;
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xmit = &port->state->xmit;
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if (port->x_char) {
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if (tilegx_putchar(context, port->x_char))
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return;
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port->x_char = 0;
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port->icount.tx++;
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}
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if (uart_circ_empty(xmit) || uart_tx_stopped(port))
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return;
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while (!uart_circ_empty(xmit)) {
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ch = xmit->buf[xmit->tail];
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if (tilegx_putchar(context, ch))
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break;
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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}
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/* Reset WFIFO_RE interrupt. */
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gxio_uart_write(context, UART_INTERRUPT_STATUS,
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UART_INTERRUPT_MASK__WFIFO_RE_MASK);
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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}
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/*
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* UART Interrupt handler.
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*/
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static irqreturn_t tilegx_interrupt(int irq, void *dev_id)
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{
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unsigned long flags;
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UART_INTERRUPT_STATUS_t intr_stat;
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struct tile_uart_port *tile_uart;
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gxio_uart_context_t *context;
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struct uart_port *port = dev_id;
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irqreturn_t ret = IRQ_NONE;
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spin_lock_irqsave(&port->lock, flags);
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tile_uart = container_of(port, struct tile_uart_port, uart);
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context = &tile_uart->context;
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intr_stat.word = gxio_uart_read(context, UART_INTERRUPT_STATUS);
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if (intr_stat.rfifo_we) {
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handle_receive(tile_uart);
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ret = IRQ_HANDLED;
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}
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if (intr_stat.wfifo_re) {
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handle_transmit(tile_uart);
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ret = IRQ_HANDLED;
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}
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spin_unlock_irqrestore(&port->lock, flags);
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return ret;
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}
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/*
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* Return TIOCSER_TEMT when transmitter FIFO is empty.
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*/
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static u_int tilegx_tx_empty(struct uart_port *port)
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{
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int ret;
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UART_FLAG_t flag;
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struct tile_uart_port *tile_uart;
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gxio_uart_context_t *context;
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tile_uart = container_of(port, struct tile_uart_port, uart);
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if (!mutex_trylock(&tile_uart->mutex))
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return 0;
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context = &tile_uart->context;
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flag.word = gxio_uart_read(context, UART_FLAG);
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ret = (flag.wfifo_empty) ? TIOCSER_TEMT : 0;
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mutex_unlock(&tile_uart->mutex);
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return ret;
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}
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/*
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* Set state of the modem control output lines.
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*/
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static void tilegx_set_mctrl(struct uart_port *port, u_int mctrl)
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{
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/* N/A */
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}
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/*
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* Get state of the modem control input lines.
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*/
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static u_int tilegx_get_mctrl(struct uart_port *port)
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{
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return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
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}
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/*
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* Stop transmitting.
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*/
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static void tilegx_stop_tx(struct uart_port *port)
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{
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/* N/A */
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}
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/*
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* Start transmitting.
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*/
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static void tilegx_start_tx(struct uart_port *port)
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{
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unsigned char ch;
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struct circ_buf *xmit;
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struct tile_uart_port *tile_uart;
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gxio_uart_context_t *context;
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tile_uart = container_of(port, struct tile_uart_port, uart);
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if (!mutex_trylock(&tile_uart->mutex))
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return;
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context = &tile_uart->context;
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xmit = &port->state->xmit;
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if (port->x_char) {
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if (tilegx_putchar(context, port->x_char))
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return;
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port->x_char = 0;
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port->icount.tx++;
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}
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if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
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mutex_unlock(&tile_uart->mutex);
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return;
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}
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while (!uart_circ_empty(xmit)) {
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ch = xmit->buf[xmit->tail];
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if (tilegx_putchar(context, ch))
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break;
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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}
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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mutex_unlock(&tile_uart->mutex);
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}
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/*
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* Stop receiving - port is in process of being closed.
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*/
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static void tilegx_stop_rx(struct uart_port *port)
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{
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int err;
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struct tile_uart_port *tile_uart;
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gxio_uart_context_t *context;
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int cpu;
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tile_uart = container_of(port, struct tile_uart_port, uart);
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if (!mutex_trylock(&tile_uart->mutex))
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return;
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context = &tile_uart->context;
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cpu = tile_uart->irq_cpu;
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err = gxio_uart_cfg_interrupt(context, cpu_x(cpu), cpu_y(cpu),
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KERNEL_PL, -1);
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mutex_unlock(&tile_uart->mutex);
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}
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/*
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* Enable modem status interrupts.
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*/
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static void tilegx_enable_ms(struct uart_port *port)
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{
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/* N/A */
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}
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/*
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* Control the transmission of a break signal.
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*/
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static void tilegx_break_ctl(struct uart_port *port, int break_state)
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{
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/* N/A */
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}
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/*
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* Perform initialization and enable port for reception.
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*/
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static int tilegx_startup(struct uart_port *port)
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{
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struct tile_uart_port *tile_uart;
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gxio_uart_context_t *context;
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int ret = 0;
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int cpu = raw_smp_processor_id(); /* pick an arbitrary cpu */
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tile_uart = container_of(port, struct tile_uart_port, uart);
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if (mutex_lock_interruptible(&tile_uart->mutex))
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return -EBUSY;
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context = &tile_uart->context;
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/* Now open the hypervisor device if we haven't already. */
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if (context->fd < 0) {
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UART_INTERRUPT_MASK_t intr_mask;
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/* Initialize UART device. */
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ret = gxio_uart_init(context, port->line);
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if (ret) {
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ret = -ENXIO;
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goto err;
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}
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/* Create our IRQs. */
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port->irq = create_irq();
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if (port->irq < 0)
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goto err_uart_dest;
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tile_irq_activate(port->irq, TILE_IRQ_PERCPU);
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/* Register our IRQs. */
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ret = request_irq(port->irq, tilegx_interrupt, 0,
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tilegx_uart_driver.driver_name, port);
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if (ret)
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goto err_dest_irq;
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/* Request that the hardware start sending us interrupts. */
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tile_uart->irq_cpu = cpu;
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ret = gxio_uart_cfg_interrupt(context, cpu_x(cpu), cpu_y(cpu),
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KERNEL_PL, port->irq);
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if (ret)
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goto err_free_irq;
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/* Enable UART Tx/Rx Interrupt. */
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intr_mask.word = gxio_uart_read(context, UART_INTERRUPT_MASK);
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intr_mask.wfifo_re = 0;
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intr_mask.rfifo_we = 0;
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gxio_uart_write(context, UART_INTERRUPT_MASK, intr_mask.word);
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/* Reset the Tx/Rx interrupt in case it's set. */
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gxio_uart_write(context, UART_INTERRUPT_STATUS,
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UART_INTERRUPT_MASK__WFIFO_RE_MASK |
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UART_INTERRUPT_MASK__RFIFO_WE_MASK);
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}
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mutex_unlock(&tile_uart->mutex);
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return ret;
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err_free_irq:
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free_irq(port->irq, port);
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err_dest_irq:
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destroy_irq(port->irq);
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err_uart_dest:
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gxio_uart_destroy(context);
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ret = -ENXIO;
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err:
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mutex_unlock(&tile_uart->mutex);
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return ret;
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}
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/*
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* Release kernel resources if it is the last close, disable the port,
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* free IRQ and close the port.
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*/
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static void tilegx_shutdown(struct uart_port *port)
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{
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int err;
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UART_INTERRUPT_MASK_t intr_mask;
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struct tile_uart_port *tile_uart;
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gxio_uart_context_t *context;
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int cpu;
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tile_uart = container_of(port, struct tile_uart_port, uart);
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if (mutex_lock_interruptible(&tile_uart->mutex))
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return;
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context = &tile_uart->context;
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/* Disable UART Tx/Rx Interrupt. */
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intr_mask.word = gxio_uart_read(context, UART_INTERRUPT_MASK);
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intr_mask.wfifo_re = 1;
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intr_mask.rfifo_we = 1;
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gxio_uart_write(context, UART_INTERRUPT_MASK, intr_mask.word);
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/* Request that the hardware stop sending us interrupts. */
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cpu = tile_uart->irq_cpu;
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err = gxio_uart_cfg_interrupt(context, cpu_x(cpu), cpu_y(cpu),
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KERNEL_PL, -1);
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if (port->irq > 0) {
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free_irq(port->irq, port);
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destroy_irq(port->irq);
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port->irq = 0;
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}
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gxio_uart_destroy(context);
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mutex_unlock(&tile_uart->mutex);
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}
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/*
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||||
* Flush the buffer.
|
||||
*/
|
||||
static void tilegx_flush_buffer(struct uart_port *port)
|
||||
{
|
||||
/* N/A */
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Change the port parameters.
|
||||
*/
|
||||
static void tilegx_set_termios(struct uart_port *port,
|
||||
struct ktermios *termios, struct ktermios *old)
|
||||
{
|
||||
int err;
|
||||
UART_DIVISOR_t divisor;
|
||||
UART_TYPE_t type;
|
||||
unsigned int baud;
|
||||
struct tile_uart_port *tile_uart;
|
||||
gxio_uart_context_t *context;
|
||||
|
||||
tile_uart = container_of(port, struct tile_uart_port, uart);
|
||||
if (!mutex_trylock(&tile_uart->mutex))
|
||||
return;
|
||||
context = &tile_uart->context;
|
||||
|
||||
/* Open the hypervisor device if we haven't already. */
|
||||
if (context->fd < 0) {
|
||||
err = gxio_uart_init(context, port->line);
|
||||
if (err) {
|
||||
mutex_unlock(&tile_uart->mutex);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
divisor.word = gxio_uart_read(context, UART_DIVISOR);
|
||||
type.word = gxio_uart_read(context, UART_TYPE);
|
||||
|
||||
/* Divisor. */
|
||||
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
|
||||
divisor.divisor = uart_get_divisor(port, baud);
|
||||
|
||||
/* Byte size. */
|
||||
if ((termios->c_cflag & CSIZE) == CS7)
|
||||
type.dbits = UART_TYPE__DBITS_VAL_SEVEN_DBITS;
|
||||
else
|
||||
type.dbits = UART_TYPE__DBITS_VAL_EIGHT_DBITS;
|
||||
|
||||
/* Parity. */
|
||||
if (termios->c_cflag & PARENB) {
|
||||
/* Mark or Space parity. */
|
||||
if (termios->c_cflag & CMSPAR)
|
||||
if (termios->c_cflag & PARODD)
|
||||
type.ptype = UART_TYPE__PTYPE_VAL_MARK;
|
||||
else
|
||||
type.ptype = UART_TYPE__PTYPE_VAL_SPACE;
|
||||
else if (termios->c_cflag & PARODD)
|
||||
type.ptype = UART_TYPE__PTYPE_VAL_ODD;
|
||||
else
|
||||
type.ptype = UART_TYPE__PTYPE_VAL_EVEN;
|
||||
} else
|
||||
type.ptype = UART_TYPE__PTYPE_VAL_NONE;
|
||||
|
||||
/* Stop bits. */
|
||||
if (termios->c_cflag & CSTOPB)
|
||||
type.sbits = UART_TYPE__SBITS_VAL_TWO_SBITS;
|
||||
else
|
||||
type.sbits = UART_TYPE__SBITS_VAL_ONE_SBITS;
|
||||
|
||||
/* Set the uart paramters. */
|
||||
gxio_uart_write(context, UART_DIVISOR, divisor.word);
|
||||
gxio_uart_write(context, UART_TYPE, type.word);
|
||||
|
||||
mutex_unlock(&tile_uart->mutex);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Return string describing the specified port.
|
||||
*/
|
||||
static const char *tilegx_type(struct uart_port *port)
|
||||
{
|
||||
return port->type == PORT_TILEGX ? DRIVER_NAME_STRING : NULL;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Release the resources being used by 'port'.
|
||||
*/
|
||||
static void tilegx_release_port(struct uart_port *port)
|
||||
{
|
||||
/* Nothing to release. */
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Request the resources being used by 'port'.
|
||||
*/
|
||||
static int tilegx_request_port(struct uart_port *port)
|
||||
{
|
||||
/* Always present. */
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Configure/autoconfigure the port.
|
||||
*/
|
||||
static void tilegx_config_port(struct uart_port *port, int flags)
|
||||
{
|
||||
if (flags & UART_CONFIG_TYPE)
|
||||
port->type = PORT_TILEGX;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Verify the new serial_struct (for TIOCSSERIAL).
|
||||
*/
|
||||
static int tilegx_verify_port(struct uart_port *port,
|
||||
struct serial_struct *ser)
|
||||
{
|
||||
if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_TILEGX))
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CONSOLE_POLL
|
||||
|
||||
/*
|
||||
* Console polling routines for writing and reading from the uart while
|
||||
* in an interrupt or debug context.
|
||||
*/
|
||||
|
||||
static int tilegx_poll_get_char(struct uart_port *port)
|
||||
{
|
||||
UART_FIFO_COUNT_t count;
|
||||
gxio_uart_context_t *context;
|
||||
struct tile_uart_port *tile_uart;
|
||||
|
||||
tile_uart = container_of(port, struct tile_uart_port, uart);
|
||||
context = &tile_uart->context;
|
||||
count.word = gxio_uart_read(context, UART_FIFO_COUNT);
|
||||
if (count.rfifo_count == 0)
|
||||
return NO_POLL_CHAR;
|
||||
return (char)gxio_uart_read(context, UART_RECEIVE_DATA);
|
||||
}
|
||||
|
||||
static void tilegx_poll_put_char(struct uart_port *port, unsigned char c)
|
||||
{
|
||||
gxio_uart_context_t *context;
|
||||
struct tile_uart_port *tile_uart;
|
||||
|
||||
tile_uart = container_of(port, struct tile_uart_port, uart);
|
||||
context = &tile_uart->context;
|
||||
gxio_uart_write(context, UART_TRANSMIT_DATA, (unsigned long)c);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_CONSOLE_POLL */
|
||||
|
||||
|
||||
static const struct uart_ops tilegx_ops = {
|
||||
.tx_empty = tilegx_tx_empty,
|
||||
.set_mctrl = tilegx_set_mctrl,
|
||||
.get_mctrl = tilegx_get_mctrl,
|
||||
.stop_tx = tilegx_stop_tx,
|
||||
.start_tx = tilegx_start_tx,
|
||||
.stop_rx = tilegx_stop_rx,
|
||||
.enable_ms = tilegx_enable_ms,
|
||||
.break_ctl = tilegx_break_ctl,
|
||||
.startup = tilegx_startup,
|
||||
.shutdown = tilegx_shutdown,
|
||||
.flush_buffer = tilegx_flush_buffer,
|
||||
.set_termios = tilegx_set_termios,
|
||||
.type = tilegx_type,
|
||||
.release_port = tilegx_release_port,
|
||||
.request_port = tilegx_request_port,
|
||||
.config_port = tilegx_config_port,
|
||||
.verify_port = tilegx_verify_port,
|
||||
#ifdef CONFIG_CONSOLE_POLL
|
||||
.poll_get_char = tilegx_poll_get_char,
|
||||
.poll_put_char = tilegx_poll_put_char,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
static void tilegx_init_ports(void)
|
||||
{
|
||||
int i;
|
||||
struct uart_port *port;
|
||||
|
||||
for (i = 0; i < TILEGX_UART_NR; i++) {
|
||||
port = &tile_uart_ports[i].uart;
|
||||
port->ops = &tilegx_ops;
|
||||
port->line = i;
|
||||
port->type = PORT_TILEGX;
|
||||
port->uartclk = TILEGX_UART_REF_CLK;
|
||||
port->flags = UPF_BOOT_AUTOCONF;
|
||||
|
||||
tile_uart_ports[i].context.fd = -1;
|
||||
mutex_init(&tile_uart_ports[i].mutex);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static struct uart_driver tilegx_uart_driver = {
|
||||
.owner = THIS_MODULE,
|
||||
.driver_name = DRIVER_NAME_STRING,
|
||||
.dev_name = TILEGX_UART_NAME,
|
||||
.major = TILEGX_UART_MAJOR,
|
||||
.minor = TILEGX_UART_MINOR,
|
||||
.nr = TILEGX_UART_NR,
|
||||
};
|
||||
|
||||
|
||||
static int __init tilegx_init(void)
|
||||
{
|
||||
int i;
|
||||
int ret;
|
||||
struct tty_driver *tty_drv;
|
||||
|
||||
ret = uart_register_driver(&tilegx_uart_driver);
|
||||
if (ret)
|
||||
return ret;
|
||||
tty_drv = tilegx_uart_driver.tty_driver;
|
||||
tty_drv->init_termios.c_cflag = B115200 | CS8 | CREAD | HUPCL | CLOCAL;
|
||||
tty_drv->init_termios.c_ispeed = 115200;
|
||||
tty_drv->init_termios.c_ospeed = 115200;
|
||||
|
||||
tilegx_init_ports();
|
||||
|
||||
for (i = 0; i < TILEGX_UART_NR; i++) {
|
||||
struct uart_port *port = &tile_uart_ports[i].uart;
|
||||
ret = uart_add_one_port(&tilegx_uart_driver, port);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static void __exit tilegx_exit(void)
|
||||
{
|
||||
int i;
|
||||
struct uart_port *port;
|
||||
|
||||
for (i = 0; i < TILEGX_UART_NR; i++) {
|
||||
port = &tile_uart_ports[i].uart;
|
||||
uart_remove_one_port(&tilegx_uart_driver, port);
|
||||
}
|
||||
|
||||
uart_unregister_driver(&tilegx_uart_driver);
|
||||
}
|
||||
|
||||
|
||||
module_init(tilegx_init);
|
||||
module_exit(tilegx_exit);
|
||||
|
||||
MODULE_AUTHOR("Tilera Corporation");
|
||||
MODULE_DESCRIPTION("TILEGx serial port driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -232,4 +232,7 @@
|
|||
/* SH-SCI */
|
||||
#define PORT_HSCIF 104
|
||||
|
||||
/* Tilera TILE-Gx UART */
|
||||
#define PORT_TILEGX 105
|
||||
|
||||
#endif /* _UAPILINUX_SERIAL_CORE_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue