Second Round of Renesas ARM Based SoC Updates for v4.19
* Always enable ARCH_TIMER on SoCs with A7 or A15 All such SoCs have ARCH_TIMER so there is no need for it to be optional. This allows clean-up which is included in this change. * Do not compile r8a7779_platform_cpu_kill when it is unused This avoids a warning by shuffling code into an existing #ifdef r8a7779 is the R-Car H1 SoC * Add SMP enabler driver for the RZ/N1D (r9a06g032) SoC This is to allow SMP to be enabled via DT on the r9a06g032 * Stop compiling headsmp-apmu for non-SMP configs This is a minor clean-up allowing removal of an #ifdef -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAltRyyUACgkQ189kaWo3 T77hvA//Uw5GUKUsK+ues2P/GlfpDBupmZwg49lU4SzzNh0yUqglAwxha8hkq2/X JrWzLcOC+4X7vTPpd46Y88G7YjOmcCbExIKFBpicJfPCKRkTe/RguZDp5anS9qGe oZ/xz3q28pAYxlbfIUXqRmCd15E2gkmku9kYvo0dcFuWziEP9P9CYgRimD0xpXPY wTGNq0yahOJ7BkxXMXcvpWgIbtRsI5raiSxJiNLver2mTc7O5dxQC3945FlrBdU3 hPlvkvUCHSzN/+G5kIP/gtKPGJ6RgPv5WD+i36qfcpcEJpvWz+Hz74dULzBeCw3H 8p+64xgcmBzPsZcmFRLInFtWFWFjWzTSTYkfSBomwyYlPmq3pq3Ch3tr7epofBF6 S3Oa2iQXhIVkfSwy/qqkYRvgZLsjS+0QfsPuChhIaf4RC1DgTVwlpTk+SPc6gQ3j nrKsz/rTWFmqYvlZ99JLXM4v16UDEKUE/SgibY7Pk/gM/BhrJbjkPMsNX7P3qHdL mZmsQSIMspzZP57ShHz04GO2u9XchxagHBrUZ3NXOshNw745N9Wd1bzqvom8nGlR 6sf/MOXsQGS0fTskar5Mm+S7UGBYc0qAEw0SIK4VBq3ruibK5cK7rKxeTKbIuAmD 2b5y0fdqjRGGoOJjp4KBAB5ZZuDpV6PkR3TnBlqSd/ipShC0krs= =LXu6 -----END PGP SIGNATURE----- Merge tag 'renesas-arm-soc2-for-v4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Second Round of Renesas ARM Based SoC Updates for v4.19 * Always enable ARCH_TIMER on SoCs with A7 or A15 All such SoCs have ARCH_TIMER so there is no need for it to be optional. This allows clean-up which is included in this change. * Do not compile r8a7779_platform_cpu_kill when it is unused This avoids a warning by shuffling code into an existing #ifdef r8a7779 is the R-Car H1 SoC * Add SMP enabler driver for the RZ/N1D (r9a06g032) SoC This is to allow SMP to be enabled via DT on the r9a06g032 * Stop compiling headsmp-apmu for non-SMP configs This is a minor clean-up allowing removal of an #ifdef * tag 'renesas-arm-soc2-for-v4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: Always enable ARCH_TIMER on SoCs with A7 and/or A15 ARM: shmobile: r8a7779: hide unused r8a7779_platform_cpu_kill soc: r9a06g032: don't build SMP files for non-SMP config ARM: shmobile: Add the R9A06G032 SMP enabler driver ARM: shmobile: rcar-gen2: Stop compiling headsmp-apmu on !SMP Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
b598b3aaf9
9 changed files with 113 additions and 27 deletions
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@ -15,6 +15,7 @@ config ARCH_RCAR_GEN1
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config ARCH_RCAR_GEN2
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bool
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select HAVE_ARM_ARCH_TIMER
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select PM
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select PM_GENERIC_DOMAINS
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select RENESAS_IRQC
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@ -58,6 +59,7 @@ config ARCH_R8A73A4
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bool "R-Mobile APE6 (R8A73A40)"
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select ARCH_RMOBILE
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select ARM_ERRATA_798181 if SMP
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select HAVE_ARM_ARCH_TIMER
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select RENESAS_IRQC
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config ARCH_R8A7740
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@ -21,13 +21,13 @@ cpu-y := platsmp.o headsmp.o
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# Shared SoC family objects
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obj-$(CONFIG_ARCH_RCAR_GEN2) += setup-rcar-gen2.o platsmp-apmu.o $(cpu-y)
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CFLAGS_setup-rcar-gen2.o += -march=armv7-a
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obj-$(CONFIG_ARCH_RCAR_GEN2) += headsmp-apmu.o
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obj-$(CONFIG_ARCH_R8A7790) += regulator-quirk-rcar-gen2.o
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obj-$(CONFIG_ARCH_R8A7791) += regulator-quirk-rcar-gen2.o
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obj-$(CONFIG_ARCH_R8A7793) += regulator-quirk-rcar-gen2.o
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# SMP objects
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smp-y := $(cpu-y)
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smp-$(CONFIG_ARCH_RCAR_GEN2) += headsmp-apmu.o
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smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o platsmp-scu.o
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smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o platsmp-scu.o
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smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o platsmp-scu.o
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@ -8,9 +8,7 @@
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#ifdef CONFIG_SMP
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ENTRY(shmobile_boot_apmu)
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bl secure_cntvoff_init
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b secondary_startup
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ENDPROC(shmobile_boot_apmu)
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#endif
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@ -18,7 +18,6 @@ static const char *const r8a73a4_boards_compat_dt[] __initconst = {
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};
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DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
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.init_early = shmobile_init_delay,
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.init_late = shmobile_init_late,
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.dt_compat = r8a73a4_boards_compat_dt,
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MACHINE_END
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@ -59,7 +59,6 @@ static unsigned int __init get_extal_freq(void)
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void __init rcar_gen2_timer_init(void)
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{
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#ifdef CONFIG_ARM_ARCH_TIMER
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void __iomem *base;
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u32 freq;
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@ -101,7 +100,6 @@ void __init rcar_gen2_timer_init(void)
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}
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iounmap(base);
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#endif /* CONFIG_ARM_ARCH_TIMER */
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of_clk_init(NULL);
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timer_probe();
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@ -187,7 +185,6 @@ static const char * const rcar_gen2_boards_compat_dt[] __initconst = {
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};
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DT_MACHINE_START(RCAR_GEN2_DT, "Generic R-Car Gen2 (Flattened Device Tree)")
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.init_early = shmobile_init_delay,
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.init_late = shmobile_init_late,
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.init_time = rcar_gen2_timer_init,
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.reserve = rcar_gen2_reserve,
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@ -202,7 +199,6 @@ static const char * const rz_g1_boards_compat_dt[] __initconst = {
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};
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DT_MACHINE_START(RZ_G1_DT, "Generic RZ/G1 (Flattened Device Tree)")
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.init_early = shmobile_init_delay,
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.init_late = shmobile_init_late,
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.init_time = rcar_gen2_timer_init,
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.reserve = rcar_gen2_reserve,
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@ -23,17 +23,6 @@
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#define AVECR IOMEM(0xfe700040)
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#define R8A7779_SCU_BASE 0xf0000000
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static int r8a7779_platform_cpu_kill(unsigned int cpu)
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{
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int ret = -EIO;
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cpu = cpu_logical_map(cpu);
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if (cpu)
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ret = rcar_sysc_power_down_cpu(cpu);
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return ret ? ret : 1;
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}
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static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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int ret = -EIO;
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@ -55,6 +44,17 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static int r8a7779_platform_cpu_kill(unsigned int cpu)
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{
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int ret = -EIO;
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cpu = cpu_logical_map(cpu);
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if (cpu)
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ret = rcar_sysc_power_down_cpu(cpu);
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return ret ? ret : 1;
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}
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static int r8a7779_cpu_kill(unsigned int cpu)
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{
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if (shmobile_smp_scu_cpu_kill(cpu))
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@ -32,14 +32,6 @@ void __init shmobile_init_delay(void)
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for_each_child_of_node(cpus, np) {
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u32 freq;
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if (IS_ENABLED(CONFIG_ARM_ARCH_TIMER) &&
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(of_device_is_compatible(np, "arm,cortex-a7") ||
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of_device_is_compatible(np, "arm,cortex-a15"))) {
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of_node_put(np);
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of_node_put(cpus);
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return;
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}
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if (!of_property_read_u32(np, "clock-frequency", &freq))
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max_freq = max(max_freq, freq);
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}
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@ -18,6 +18,9 @@ obj-$(CONFIG_SYSC_R8A77970) += r8a77970-sysc.o
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obj-$(CONFIG_SYSC_R8A77980) += r8a77980-sysc.o
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obj-$(CONFIG_SYSC_R8A77990) += r8a77990-sysc.o
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obj-$(CONFIG_SYSC_R8A77995) += r8a77995-sysc.o
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ifdef CONFIG_SMP
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obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o
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endif
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# Family
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obj-$(CONFIG_RST_RCAR) += rcar-rst.o
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96
drivers/soc/renesas/r9a06g032-smp.c
Normal file
96
drivers/soc/renesas/r9a06g032-smp.c
Normal file
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@ -0,0 +1,96 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* R9A06G032 Second CA7 enabler.
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*
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* Copyright (C) 2018 Renesas Electronics Europe Limited
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*
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* Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
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* Derived from actions,s500-smp
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*/
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/smp.h>
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/*
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* The second CPU is parked in ROM at boot time. It requires waking it after
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* writing an address into the BOOTADDR register of sysctrl.
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*
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* So the default value of the "cpu-release-addr" corresponds to BOOTADDR...
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*
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* *However* the BOOTADDR register is not available when the kernel
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* starts in NONSEC mode.
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*
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* So for NONSEC mode, the bootloader re-parks the second CPU into a pen
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* in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address,
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* which is not restricted.
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*/
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static void __iomem *cpu_bootaddr;
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static DEFINE_SPINLOCK(cpu_lock);
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static int
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r9a06g032_smp_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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{
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if (!cpu_bootaddr)
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return -ENODEV;
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spin_lock(&cpu_lock);
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writel(__pa_symbol(secondary_startup), cpu_bootaddr);
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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spin_unlock(&cpu_lock);
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return 0;
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}
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static void __init r9a06g032_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *dn;
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int ret = -EINVAL, dns;
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u32 bootaddr;
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dn = of_get_cpu_node(1, NULL);
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if (!dn) {
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pr_err("CPU#1: missing device tree node\n");
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return;
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}
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/*
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* Determine the address from which the CPU is polling.
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* The bootloader *does* change this property.
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* Note: The property can be either 64 or 32 bits, so handle both cases
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*/
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if (of_find_property(dn, "cpu-release-addr", &dns)) {
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if (dns == sizeof(u64)) {
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u64 temp;
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ret = of_property_read_u64(dn,
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"cpu-release-addr", &temp);
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bootaddr = temp;
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} else {
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ret = of_property_read_u32(dn,
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"cpu-release-addr",
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&bootaddr);
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}
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}
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of_node_put(dn);
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if (ret) {
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pr_err("CPU#1: invalid cpu-release-addr property\n");
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return;
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}
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pr_info("CPU#1: cpu-release-addr %08x\n", bootaddr);
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cpu_bootaddr = ioremap(bootaddr, sizeof(bootaddr));
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}
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static const struct smp_operations r9a06g032_smp_ops __initconst = {
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.smp_prepare_cpus = r9a06g032_smp_prepare_cpus,
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.smp_boot_secondary = r9a06g032_smp_boot_secondary,
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};
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CPU_METHOD_OF_DECLARE(r9a06g032_smp,
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"renesas,r9a06g032-smp", &r9a06g032_smp_ops);
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