tree-wide: fix comment/printk typos
"gadget", "through", "command", "maintain", "maintain", "controller", "address", "between", "initiali[zs]e", "instead", "function", "select", "already", "equal", "access", "management", "hierarchy", "registration", "interest", "relative", "memory", "offset", "already", Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
This commit is contained in:
Uwe Kleine-König
Jiri Kosina
parent
6aaccece1c
commit
b595076a18
207 changed files with 261 additions and 261 deletions
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@ -250,7 +250,7 @@ static void board_hwcontrol(struct mtd_info *mtd, int cmd)
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<title>Device ready function</title>
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<para>
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If the hardware interface has the ready busy pin of the NAND chip connected to a
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GPIO or other accesible I/O pin, this function is used to read back the state of the
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GPIO or other accessible I/O pin, this function is used to read back the state of the
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pin. The function has no arguments and should return 0, if the device is busy (R/B pin
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is low) and 1, if the device is ready (R/B pin is high).
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If the hardware interface does not give access to the ready busy pin, then
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@ -91,7 +91,7 @@ int main(int argc, char **argv)
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if (ret == -1) {
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perror("cgroup.event_control "
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"is not accessable any more");
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"is not accessible any more");
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break;
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}
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@ -398,7 +398,7 @@ Under below explanation, we assume CONFIG_MEM_RES_CTRL_SWAP=y.
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written to move_charge_at_immigrate.
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9.10 Memory thresholds
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Memory controler implements memory thresholds using cgroups notification
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Memory controller implements memory thresholds using cgroups notification
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API. You can use Documentation/cgroups/cgroup_event_listener.c to test
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it.
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@ -598,7 +598,7 @@ a 5-byte jump instruction. So there are several limitations.
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a) The instructions in DCR must be relocatable.
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b) The instructions in DCR must not include a call instruction.
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c) JTPR must not be targeted by any jump or call instruction.
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d) DCR must not straddle the border betweeen functions.
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d) DCR must not straddle the border between functions.
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Anyway, these limitations are checked by the in-kernel instruction
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decoder, so you don't need to worry about that.
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@ -874,7 +874,7 @@ Possible values are:
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- KVM_MP_STATE_HALTED: the vcpu has executed a HLT instruction and
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is waiting for an interrupt
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- KVM_MP_STATE_SIPI_RECEIVED: the vcpu has just received a SIPI (vector
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accesible via KVM_GET_VCPU_EVENTS)
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accessible via KVM_GET_VCPU_EVENTS)
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This ioctl is only useful after KVM_CREATE_IRQCHIP. Without an in-kernel
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irqchip, the multiprocessing state must be maintained by userspace.
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@ -32,7 +32,7 @@ the physical hardware, both with regard to SPI and to GPIOs.
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This function is called by the CAIF SPI interface to give
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you a chance to set up your hardware to be ready to receive
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a stream of data from the master. The xfer structure contains
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both physical and logical adresses, as well as the total length
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both physical and logical addresses, as well as the total length
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of the transfer in both directions.The dev parameter can be used
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to map to different CAIF SPI slave devices.
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@ -1098,7 +1098,7 @@ supported currently at the toplevel.
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* an arbitrary array of bytes
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*/
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childnode@addresss { /* define a child node named "childnode"
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childnode@address { /* define a child node named "childnode"
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* whose unit name is "childnode at
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* address"
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*/
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@ -573,7 +573,7 @@ Changes from 20041018 to 20041123
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* Backround nodev_timeout processing to DPC This enables us to
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unblock (stop dev_loss_tmo) when appopriate.
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* Fix array discovery with multiple luns. The max_luns was 0 at
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the time the host structure was intialized. lpfc_cfg_params
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the time the host structure was initialized. lpfc_cfg_params
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then set the max_luns to the correct value afterwards.
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* Remove unused define LPFC_MAX_LUN and set the default value of
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lpfc_max_lun parameter to 512.
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@ -19,7 +19,7 @@ Linux system over a sample period:
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- the pid of the task(process) which initialized the timer
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- the name of the process which initialized the timer
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- the function where the timer was intialized
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- the function where the timer was initialized
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- the callback function which is associated to the timer
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- the number of events (callbacks)
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@ -236,7 +236,7 @@ static struct resource it8152_mem = {
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/*
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* The following functions are needed for DMA bouncing.
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* ITE8152 chip can addrees up to 64MByte, so all the devices
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* ITE8152 chip can address up to 64MByte, so all the devices
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* connected to ITE8152 (PCI and USB) should have limited DMA window
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*/
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@ -70,7 +70,7 @@ static inline struct vic_device *to_vic(struct sys_device *sys)
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* vic_init2 - common initialisation code
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* @base: Base of the VIC.
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*
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* Common initialisation code for registeration
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* Common initialisation code for registration
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* and resume.
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*/
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static void vic_init2(void __iomem *base)
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@ -128,17 +128,17 @@ static struct spi_board_info __initdata ecb_at91spi_devices[] = {
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.platform_data = &my_flash0_platform,
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#endif
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},
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{ /* User accessable spi - cs1 (250KHz) */
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{ /* User accessible spi - cs1 (250KHz) */
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.modalias = "spi-cs1",
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.chip_select = 1,
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.max_speed_hz = 250 * 1000,
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},
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{ /* User accessable spi - cs2 (1MHz) */
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{ /* User accessible spi - cs2 (1MHz) */
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.modalias = "spi-cs2",
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.chip_select = 2,
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.max_speed_hz = 1 * 1000 * 1000,
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},
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{ /* User accessable spi - cs3 (10MHz) */
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{ /* User accessible spi - cs3 (10MHz) */
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.modalias = "spi-cs3",
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.chip_select = 3,
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.max_speed_hz = 10 * 1000 * 1000,
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@ -757,7 +757,7 @@ static int chipcHw_divide(int num, int denom)
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t = t << 1;
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}
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/* Intialize the result */
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/* Initialize the result */
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r = 0;
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do {
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@ -893,7 +893,7 @@ int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration
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*/
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/****************************************************************************/
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uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
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dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controler attribute of type dmacHw_CONTROLLER_ATTRIB_e */
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dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controller attribute of type dmacHw_CONTROLLER_ATTRIB_e */
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) {
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dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
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@ -316,7 +316,7 @@ static void DisplayDescRing(void *pDescriptor, /* [ IN ] Descriptor buffer */
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/**
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* @brief Check if DMA channel is the flow controller
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*
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* @return 1 : If DMA is a flow controler
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* @return 1 : If DMA is a flow controller
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* 0 : Peripheral is the flow controller
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*
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* @note
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@ -558,7 +558,7 @@ static int tmrHw_divide(int num, int denom)
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t = t << 1;
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}
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/* Intialize the result */
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/* Initialize the result */
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r = 0;
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do {
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@ -671,7 +671,7 @@ static int ConfigChannel(DMA_Handle_t handle)
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/****************************************************************************/
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/**
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* Intializes all of the data structures associated with the DMA.
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* Initializes all of the data structures associated with the DMA.
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* @return
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* >= 0 - Initialization was successfull.
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*
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@ -590,7 +590,7 @@ void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle
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*/
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/****************************************************************************/
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uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
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dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controler attribute of type dmacHw_CONTROLLER_ATTRIB_e */
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dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controller attribute of type dmacHw_CONTROLLER_ATTRIB_e */
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);
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#endif /* _DMACHW_H */
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@ -28,7 +28,7 @@
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/* Data type for DMA Link List Item */
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typedef struct {
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uint32_t sar; /* Source Adress Register.
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uint32_t sar; /* Source Address Register.
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Address must be aligned to CTLx.SRC_TR_WIDTH. */
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uint32_t dar; /* Destination Address Register.
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Address must be aligned to CTLx.DST_TR_WIDTH. */
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@ -35,7 +35,7 @@ typedef struct {
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/* Data type representing DMA channel registers */
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typedef struct {
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dmacHw_REG64_t ChannelSar; /* Source Adress Register. 64 bits (upper 32 bits are reserved)
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dmacHw_REG64_t ChannelSar; /* Source Address Register. 64 bits (upper 32 bits are reserved)
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Address must be aligned to CTLx.SRC_TR_WIDTH.
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*/
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dmacHw_REG64_t ChannelDar; /* Destination Address Register.64 bits (upper 32 bits are reserved)
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@ -33,7 +33,7 @@
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#define GEMINI_LPC_HOST_BASE 0x47000000
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#define GEMINI_LPC_IO_BASE 0x47800000
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#define GEMINI_INTERRUPT_BASE 0x48000000
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/* TODO: Different interrupt controlers when SMP
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/* TODO: Different interrupt controllers when SMP
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* #define GEMINI_INTERRUPT0_BASE 0x48000000
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* #define GEMINI_INTERRUPT1_BASE 0x49000000
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*/
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@ -153,7 +153,7 @@ __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
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{
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if (mtype == MT_DEVICE) {
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/* The peripherals in the 88000000 - D0000000 range
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* are only accessable by type MT_DEVICE_NONSHARED.
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* are only accessible by type MT_DEVICE_NONSHARED.
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* Adjust mtype as necessary to make this "just work."
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*/
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if ((phys_addr >= 0x88000000) && (phys_addr < 0xD0000000))
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@ -252,7 +252,7 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
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* FIXME: we currently manage device-specific idle states
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* for PER and CORE in combination with CPU-specific
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* idle states. This is wrong, and device-specific
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* idle managment needs to be separated out into
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* idle management needs to be separated out into
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* its own code.
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*/
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@ -843,7 +843,7 @@ void __init omap_serial_init_port(int port)
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}
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/**
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* omap_serial_init() - intialize all supported serial ports
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* omap_serial_init() - initialize all supported serial ports
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*
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* Initializes all available UARTs as serial ports. Platforms
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* can call this function when they want to have default behaviour
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@ -337,7 +337,7 @@ void __init mxm_8x10_mmc_init(void)
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}
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#endif
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/* USB Open Host Controler Interface */
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/* USB Open Host Controller Interface */
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static struct pxaohci_platform_data mxm_8x10_ohci_platform_data = {
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.port_mode = PMM_NPS_MODE,
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.flags = ENABLE_PORT_ALL
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@ -740,7 +740,7 @@ static int __init s3c64xx_dma_init(void)
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/* Set all DMA configuration to be DMA, not SDMA */
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writel(0xffffff, S3C_SYSREG(0x110));
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/* Register standard DMA controlers */
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/* Register standard DMA controllers */
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s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000);
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s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_DMA1, 0x75100000);
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@ -371,7 +371,7 @@ struct pmx_driver pmx_driver = {
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};
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/* Add spear300 specific devices here */
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/* arm gpio1 device registeration */
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/* arm gpio1 device registration */
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static struct pl061_platform_data gpio1_plat_data = {
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.gpio_base = 8,
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.irq_base = SPEAR_GPIO1_INT_BASE,
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@ -451,7 +451,7 @@ void __init spear300_init(void)
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/* call spear3xx family common init function */
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spear3xx_init();
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/* shared irq registeration */
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/* shared irq registration */
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shirq_ras1.regs.base =
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ioremap(SPEAR300_TELECOM_BASE, SPEAR300_TELECOM_REG_SIZE);
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if (shirq_ras1.regs.base) {
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@ -266,7 +266,7 @@ void __init spear310_init(void)
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/* call spear3xx family common init function */
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spear3xx_init();
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/* shared irq registeration */
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/* shared irq registration */
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base = ioremap(SPEAR310_SOC_CONFIG_BASE, SPEAR310_SOC_CONFIG_SIZE);
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if (base) {
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/* shirq 1 */
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@ -519,7 +519,7 @@ void __init spear320_init(void)
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/* call spear3xx family common init function */
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spear3xx_init();
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/* shared irq registeration */
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/* shared irq registration */
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base = ioremap(SPEAR320_SOC_CONFIG_BASE, SPEAR320_SOC_CONFIG_SIZE);
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if (base) {
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/* shirq 1 */
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@ -22,7 +22,7 @@
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#include <mach/spear.h>
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/* Add spear3xx machines common devices here */
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/* gpio device registeration */
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/* gpio device registration */
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static struct pl061_platform_data gpio_plat_data = {
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.gpio_base = 0,
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.irq_base = SPEAR_GPIO_INT_BASE,
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@ -41,7 +41,7 @@ struct amba_device gpio_device = {
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.irq = {IRQ_BASIC_GPIO, NO_IRQ},
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};
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/* uart device registeration */
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/* uart device registration */
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struct amba_device uart_device = {
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.dev = {
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.init_name = "uart",
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@ -543,6 +543,6 @@ void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size)
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pmx_fail:
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if (ret)
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printk(KERN_ERR "padmux: registeration failed. err no: %d\n",
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printk(KERN_ERR "padmux: registration failed. err no: %d\n",
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ret);
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}
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@ -23,7 +23,7 @@
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#include <mach/spear.h>
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/* Add spear6xx machines common devices here */
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/* uart device registeration */
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/* uart device registration */
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struct amba_device uart_device[] = {
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{
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.dev = {
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@ -50,7 +50,7 @@ struct amba_device uart_device[] = {
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}
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};
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/* gpio device registeration */
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/* gpio device registration */
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static struct pl061_platform_data gpio_plat_data[] = {
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{
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.gpio_base = 0,
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@ -64,7 +64,7 @@ config MACH_U300_DUAL_RAM
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bool "Dual RAM"
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help
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Select this if you want support for Dual RAM phones.
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This is two RAM memorys on different EMIFs.
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This is two RAM memories on different EMIFs.
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endchoice
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config U300_DEBUG
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@ -24,7 +24,7 @@
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* @src_addr: transfer source address
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* @dst_addr: transfer destination address
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* @link_addr: physical address to next lli
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* @virt_link_addr: virtual addres of next lli (only used by pool_free)
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* @virt_link_addr: virtual address of next lli (only used by pool_free)
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* @phy_this: physical address of current lli (only used by pool_free)
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*/
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struct coh901318_lli {
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@ -90,7 +90,7 @@ struct powersave {
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* struct coh901318_platform - platform arch structure
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* @chans_slave: specifying dma slave channels
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* @chans_memcpy: specifying dma memcpy channels
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* @access_memory_state: requesting DMA memeory access (on / off)
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* @access_memory_state: requesting DMA memory access (on / off)
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* @chan_conf: dma channel configurations
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* @max_channels: max number of dma chanenls
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*/
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@ -66,7 +66,7 @@ extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
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/* all normal IRQs can be FIQs */
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#define FIQ_START 0
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/* switch betwean IRQ and FIQ */
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/* switch between IRQ and FIQ */
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extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type);
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#endif /* __ASM_ARCH_MXC_IRQS_H__ */
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@ -339,7 +339,7 @@ struct omap_hwmod_omap2_prcm {
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/**
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* struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
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* @clkctrl_reg: PRCM address of the clock control register
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* @rstctrl_reg: adress of the XXX_RSTCTRL register located in the PRM
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* @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM
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* @submodule_wkdep_bit: bit shift of the WKDEP range
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*/
|
||||
struct omap_hwmod_omap4_prcm {
|
||||
|
|
|
|||
|
|
@ -1197,7 +1197,7 @@
|
|||
#define SADD_LEN 0x0002 /* Slave Address Length */
|
||||
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
|
||||
#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
|
||||
#define GEN 0x0010 /* General Call Adrress Matching Enabled */
|
||||
#define GEN 0x0010 /* General Call Address Matching Enabled */
|
||||
|
||||
/* TWI_SLAVE_STAT Masks */
|
||||
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
|
||||
|
|
|
|||
|
|
@ -1206,7 +1206,7 @@
|
|||
#define SADD_LEN 0x0002 /* Slave Address Length */
|
||||
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
|
||||
#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
|
||||
#define GEN 0x0010 /* General Call Adrress Matching Enabled */
|
||||
#define GEN 0x0010 /* General Call Address Matching Enabled */
|
||||
|
||||
/* TWI_SLAVE_STAT Masks */
|
||||
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
|
||||
|
|
|
|||
|
|
@ -1523,7 +1523,7 @@
|
|||
#define SADD_LEN 0x0002 /* Slave Address Length */
|
||||
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
|
||||
#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
|
||||
#define GEN 0x0010 /* General Call Adrress Matching Enabled */
|
||||
#define GEN 0x0010 /* General Call Address Matching Enabled */
|
||||
|
||||
/* TWI_SLAVE_STAT Masks */
|
||||
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
|
||||
|
|
|
|||
|
|
@ -2185,7 +2185,7 @@
|
|||
#define SADD_LEN 0x0002 /* Slave Address Length */
|
||||
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
|
||||
#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
|
||||
#define GEN 0x0010 /* General Call Adrress Matching Enabled */
|
||||
#define GEN 0x0010 /* General Call Address Matching Enabled */
|
||||
|
||||
/* TWIx_SLAVE_STAT Masks */
|
||||
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
|
||||
|
|
|
|||
|
|
@ -139,7 +139,7 @@ copy_nand_to_ram:
|
|||
lsrq 8, $r4
|
||||
move.b $r4, [$r1] ; Row address
|
||||
lsrq 8, $r4
|
||||
move.b $r4, [$r1] ; Row adddress
|
||||
move.b $r4, [$r1] ; Row address
|
||||
moveq 20, $r4
|
||||
2: bne 2b
|
||||
subq 1, $r4
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* The following devices are accessable using this driver using
|
||||
* The following devices are accessible using this driver using
|
||||
* GPIO_MAJOR (120) and a couple of minor numbers.
|
||||
*
|
||||
* For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10):
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ config DEFAULT_CMDLINE
|
|||
builtin kernel commandline enabled.
|
||||
|
||||
config KERNEL_COMMAND
|
||||
string "Buildin commmand string"
|
||||
string "Buildin command string"
|
||||
depends on DEFAULT_CMDLINE
|
||||
help
|
||||
builtin kernel commandline strings.
|
||||
|
|
|
|||
|
|
@ -130,7 +130,7 @@ static void mmio_access(struct kvm_vcpu *vcpu, u64 src_pa, u64 *dest,
|
|||
|
||||
local_irq_save(psr);
|
||||
|
||||
/*Intercept the acces for PIB range*/
|
||||
/*Intercept the access for PIB range*/
|
||||
if (iot == GPFN_PIB) {
|
||||
if (!dir)
|
||||
lsapic_write(vcpu, src_pa, s, *dest);
|
||||
|
|
|
|||
|
|
@ -130,7 +130,7 @@ static void restore_core_regs(void)
|
|||
au_writel(sleep_usb[1], USBD_ENABLE);
|
||||
au_sync();
|
||||
#else
|
||||
/* enable accces to OTG memory */
|
||||
/* enable access to OTG memory */
|
||||
au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
|
||||
au_sync();
|
||||
|
||||
|
|
|
|||
|
|
@ -88,7 +88,7 @@ static inline dma_addr_t _dma_to_phys_offset_raw(dma_addr_t dma)
|
|||
}
|
||||
|
||||
/* These are not portable and should not be used in drivers. Drivers should
|
||||
* be using ioremap() and friends to map physical addreses to virtual
|
||||
* be using ioremap() and friends to map physical addresses to virtual
|
||||
* addresses and dma_map*() and friends to map virtual addresses into DMA
|
||||
* addresses and back.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ static struct nand_ecclayout qi_lb60_ecclayout_1gb = {
|
|||
|
||||
/* Early prototypes of the QI LB60 had only 1GB of NAND.
|
||||
* In order to support these devices aswell the partition and ecc layout is
|
||||
* initalized depending on the NAND size */
|
||||
* initialized depending on the NAND size */
|
||||
static struct mtd_partition qi_lb60_partitions_1gb[] = {
|
||||
{
|
||||
.name = "NAND BOOT partition",
|
||||
|
|
@ -464,7 +464,7 @@ static int __init qi_lb60_board_setup(void)
|
|||
board_gpio_setup();
|
||||
|
||||
if (qi_lb60_init_platform_devices())
|
||||
panic("Failed to initalize platform devices\n");
|
||||
panic("Failed to initialize platform devices\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -546,7 +546,7 @@ static int __init jz4740_gpio_init(void)
|
|||
for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
|
||||
jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
|
||||
|
||||
printk(KERN_INFO "JZ4740 GPIO initalized\n");
|
||||
printk(KERN_INFO "JZ4740 GPIO initialized\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ static struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
|
|||
static char *mtypes[3] = {
|
||||
"Dont use memory",
|
||||
"YAMON PROM memory",
|
||||
"Free memmory",
|
||||
"Free memory",
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -900,7 +900,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
|
|||
mem_access_subid.s.ror = 0;
|
||||
/* Disable Relaxed Ordering for Writes. */
|
||||
mem_access_subid.s.row = 0;
|
||||
/* PCIe Adddress Bits <63:34>. */
|
||||
/* PCIe Address Bits <63:34>. */
|
||||
mem_access_subid.s.ba = 0;
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@
|
|||
unsigned long ptv_memsize;
|
||||
|
||||
/*
|
||||
* struct low_mem_reserved - Items in low memmory that are reserved
|
||||
* struct low_mem_reserved - Items in low memory that are reserved
|
||||
* @start: Physical address of item
|
||||
* @size: Size, in bytes, of this item
|
||||
* @is_aliased: True if this is RAM aliased from another location. If false,
|
||||
|
|
|
|||
|
|
@ -107,7 +107,7 @@ int txx9_pci_mem_high __initdata;
|
|||
|
||||
/*
|
||||
* allocate pci_controller and resources.
|
||||
* mem_base, io_base: physical addresss. 0 for auto assignment.
|
||||
* mem_base, io_base: physical address. 0 for auto assignment.
|
||||
* mem_size and io_size means max size on auto assignment.
|
||||
* pcic must be &txx9_primary_pcic or NULL.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -93,7 +93,7 @@ typedef struct mem_ctlr {
|
|||
} memctl8xx_t;
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BR - Memory Controler: Base Register 16-9
|
||||
* BR - Memory Controller: Base Register 16-9
|
||||
*/
|
||||
#define BR_BA_MSK 0xffff8000 /* Base Address Mask */
|
||||
#define BR_AT_MSK 0x00007000 /* Address Type Mask */
|
||||
|
|
@ -110,7 +110,7 @@ typedef struct mem_ctlr {
|
|||
#define BR_V 0x00000001 /* Bank Valid */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* OR - Memory Controler: Option Register 16-11
|
||||
* OR - Memory Controller: Option Register 16-11
|
||||
*/
|
||||
#define OR_AM_MSK 0xffff8000 /* Address Mask Mask */
|
||||
#define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */
|
||||
|
|
|
|||
|
|
@ -1469,7 +1469,7 @@ static int cell_global_start(struct op_counter_config *ctr)
|
|||
* The pm_interval register is setup to write the SPU PC value into the
|
||||
* trace buffer at the maximum rate possible. The trace buffer is configured
|
||||
* to store the PCs, wrapping when it is full. The performance counter is
|
||||
* intialized to the max hardware count minus the number of events, N, between
|
||||
* initialized to the max hardware count minus the number of events, N, between
|
||||
* samples. Once the N events have occured, a HW counter overflow occurs
|
||||
* causing the generation of a HW counter interrupt which also stops the
|
||||
* writing of the SPU PC values to the trace buffer. Hence the last PC
|
||||
|
|
|
|||
|
|
@ -231,7 +231,7 @@ _GLOBAL(mpc83xx_enter_deep_sleep)
|
|||
ori r4, r4, 0x002a
|
||||
mtspr SPRN_DBAT0L, r4
|
||||
lis r8, TMP_VIRT_IMMR@h
|
||||
ori r4, r8, 0x001e /* 1 MByte accessable from Kernel Space only */
|
||||
ori r4, r8, 0x001e /* 1 MByte accessible from Kernel Space only */
|
||||
mtspr SPRN_DBAT0U, r4
|
||||
isync
|
||||
|
||||
|
|
@ -241,7 +241,7 @@ _GLOBAL(mpc83xx_enter_deep_sleep)
|
|||
ori r4, r4, 0x002a
|
||||
mtspr SPRN_DBAT1L, r4
|
||||
lis r9, (TMP_VIRT_IMMR + 0x01000000)@h
|
||||
ori r4, r9, 0x001e /* 1 MByte accessable from Kernel Space only */
|
||||
ori r4, r9, 0x001e /* 1 MByte accessible from Kernel Space only */
|
||||
mtspr SPRN_DBAT1U, r4
|
||||
isync
|
||||
|
||||
|
|
@ -253,7 +253,7 @@ _GLOBAL(mpc83xx_enter_deep_sleep)
|
|||
li r4, 0x0002
|
||||
mtspr SPRN_DBAT2L, r4
|
||||
lis r4, KERNELBASE@h
|
||||
ori r4, r4, 0x001e /* 1 MByte accessable from Kernel Space only */
|
||||
ori r4, r4, 0x001e /* 1 MByte accessible from Kernel Space only */
|
||||
mtspr SPRN_DBAT2U, r4
|
||||
isync
|
||||
|
||||
|
|
|
|||
|
|
@ -566,10 +566,10 @@ static int ps3_setup_dynamic_device(const struct ps3_repository_device *repo)
|
|||
case PS3_DEV_TYPE_STOR_DISK:
|
||||
result = ps3_setup_storage_dev(repo, PS3_MATCH_ID_STOR_DISK);
|
||||
|
||||
/* Some devices are not accessable from the Other OS lpar. */
|
||||
/* Some devices are not accessible from the Other OS lpar. */
|
||||
if (result == -ENODEV) {
|
||||
result = 0;
|
||||
pr_debug("%s:%u: not accessable\n", __func__,
|
||||
pr_debug("%s:%u: not accessible\n", __func__,
|
||||
__LINE__);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@
|
|||
* @lock:
|
||||
* @ipi_debug_brk_mask:
|
||||
*
|
||||
* The HV mantains per SMT thread mappings of HV outlet to HV plug on
|
||||
* The HV maintains per SMT thread mappings of HV outlet to HV plug on
|
||||
* behalf of the guest. These mappings are implemented as 256 bit guest
|
||||
* supplied bitmaps indexed by plug number. The addresses of the bitmaps
|
||||
* are registered with the HV through lv1_configure_irq_state_bitmap().
|
||||
|
|
|
|||
|
|
@ -568,7 +568,7 @@ static void sh5_flush_dcache_page(void *page)
|
|||
}
|
||||
|
||||
/*
|
||||
* Flush the range [start,end] of kernel virtual adddress space from
|
||||
* Flush the range [start,end] of kernel virtual address space from
|
||||
* the I-cache. The corresponding range must be purged from the
|
||||
* D-cache also because the SH-5 doesn't have cache snooping between
|
||||
* the caches. The addresses will be visible through the superpage
|
||||
|
|
|
|||
|
|
@ -622,7 +622,7 @@ static const char CHAFSR_PERR_msg[] =
|
|||
static const char CHAFSR_IERR_msg[] =
|
||||
"Internal processor error";
|
||||
static const char CHAFSR_ISAP_msg[] =
|
||||
"System request parity error on incoming addresss";
|
||||
"System request parity error on incoming address";
|
||||
static const char CHAFSR_UCU_msg[] =
|
||||
"Uncorrectable E-cache ECC error for ifetch/data";
|
||||
static const char CHAFSR_UCC_msg[] =
|
||||
|
|
|
|||
|
|
@ -92,7 +92,7 @@ static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
|
|||
extern void ___pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd);
|
||||
|
||||
static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd,
|
||||
unsigned long adddress)
|
||||
unsigned long address)
|
||||
{
|
||||
___pmd_free_tlb(tlb, pmd);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -902,7 +902,7 @@ extern unsigned long thread_saved_pc(struct task_struct *tsk);
|
|||
/*
|
||||
* The below -8 is to reserve 8 bytes on top of the ring0 stack.
|
||||
* This is necessary to guarantee that the entire "struct pt_regs"
|
||||
* is accessable even if the CPU haven't stored the SS/ESP registers
|
||||
* is accessible even if the CPU haven't stored the SS/ESP registers
|
||||
* on the stack (interrupt gate does not save these registers
|
||||
* when switching to the same priv ring).
|
||||
* Therefore beware: accessing the ss/esp fields of the
|
||||
|
|
|
|||
|
|
@ -1086,7 +1086,7 @@ static int alloc_new_range(struct dma_ops_domain *dma_dom,
|
|||
|
||||
dma_dom->aperture_size += APERTURE_RANGE_SIZE;
|
||||
|
||||
/* Intialize the exclusion range if necessary */
|
||||
/* Initialize the exclusion range if necessary */
|
||||
for_each_iommu(iommu) {
|
||||
if (iommu->exclusion_start &&
|
||||
iommu->exclusion_start >= dma_dom->aperture[index]->offset
|
||||
|
|
@ -1353,7 +1353,7 @@ static void dma_ops_domain_free(struct dma_ops_domain *dom)
|
|||
|
||||
/*
|
||||
* Allocates a new protection domain usable for the dma_ops functions.
|
||||
* It also intializes the page table and the address allocator data
|
||||
* It also initializes the page table and the address allocator data
|
||||
* structures required for the dma_ops interface
|
||||
*/
|
||||
static struct dma_ops_domain *dma_ops_domain_alloc(void)
|
||||
|
|
|
|||
|
|
@ -103,7 +103,7 @@ struct dw_spi_reg {
|
|||
static unsigned long mrst_spi_paddr = MRST_REGBASE_SPI0;
|
||||
|
||||
static u32 *pclk_spi0;
|
||||
/* Always contains an accessable address, start with 0 */
|
||||
/* Always contains an accessible address, start with 0 */
|
||||
static struct dw_spi_reg *pspi;
|
||||
|
||||
static struct kmsg_dumper dw_dumper;
|
||||
|
|
|
|||
|
|
@ -124,7 +124,7 @@ ENTRY(startup_32)
|
|||
movsl
|
||||
movl pa(boot_params) + NEW_CL_POINTER,%esi
|
||||
andl %esi,%esi
|
||||
jz 1f # No comand line
|
||||
jz 1f # No command line
|
||||
movl $pa(boot_command_line),%edi
|
||||
movl $(COMMAND_LINE_SIZE/4),%ecx
|
||||
rep
|
||||
|
|
|
|||
|
|
@ -1030,7 +1030,7 @@ cfq_find_alloc_cfqg(struct cfq_data *cfqd, struct cgroup *cgroup, int create)
|
|||
|
||||
/*
|
||||
* Add group onto cgroup list. It might happen that bdi->dev is
|
||||
* not initiliazed yet. Initialize this new group without major
|
||||
* not initialized yet. Initialize this new group without major
|
||||
* and minor info and this info will be filled in once a new thread
|
||||
* comes for IO. See code above.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -93,7 +93,7 @@
|
|||
|
||||
#define AOPOBJ_AML_CONSTANT 0x01 /* Integer is an AML constant */
|
||||
#define AOPOBJ_STATIC_POINTER 0x02 /* Data is part of an ACPI table, don't delete */
|
||||
#define AOPOBJ_DATA_VALID 0x04 /* Object is intialized and data is valid */
|
||||
#define AOPOBJ_DATA_VALID 0x04 /* Object is initialized and data is valid */
|
||||
#define AOPOBJ_OBJECT_INITIALIZED 0x08 /* Region is initialized, _REG was run */
|
||||
#define AOPOBJ_SETUP_COMPLETE 0x10 /* Region setup is complete */
|
||||
#define AOPOBJ_INVALID 0x20 /* Host OS won't allow a Region address */
|
||||
|
|
|
|||
|
|
@ -2240,7 +2240,7 @@ int ata_dev_configure(struct ata_device *dev)
|
|||
if (id[ATA_ID_CFA_KEY_MGMT] & 1)
|
||||
ata_dev_printk(dev, KERN_WARNING,
|
||||
"supports DRM functions and may "
|
||||
"not be fully accessable.\n");
|
||||
"not be fully accessible.\n");
|
||||
snprintf(revbuf, 7, "CFA");
|
||||
} else {
|
||||
snprintf(revbuf, 7, "ATA-%d", ata_id_major_version(id));
|
||||
|
|
@ -2248,7 +2248,7 @@ int ata_dev_configure(struct ata_device *dev)
|
|||
if (ata_id_has_tpm(id))
|
||||
ata_dev_printk(dev, KERN_WARNING,
|
||||
"supports DRM functions and may "
|
||||
"not be fully accessable.\n");
|
||||
"not be fully accessible.\n");
|
||||
}
|
||||
|
||||
dev->n_sectors = ata_id_n_sectors(id);
|
||||
|
|
|
|||
|
|
@ -370,7 +370,7 @@ static int __devinit vsc_sata_init_one(struct pci_dev *pdev,
|
|||
if (pci_resource_len(pdev, 0) == 0)
|
||||
return -ENODEV;
|
||||
|
||||
/* map IO regions and intialize host accordingly */
|
||||
/* map IO regions and initialize host accordingly */
|
||||
rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
|
||||
if (rc == -EBUSY)
|
||||
pcim_pin_device(pdev);
|
||||
|
|
|
|||
|
|
@ -572,7 +572,7 @@ struct idt77252_dev
|
|||
#define SAR_STAT_TSQF 0x00001000 /* Transmit Status Queue full */
|
||||
#define SAR_STAT_TMROF 0x00000800 /* Timer overflow */
|
||||
#define SAR_STAT_PHYI 0x00000400 /* PHY device Interrupt flag */
|
||||
#define SAR_STAT_CMDBZ 0x00000200 /* ABR SAR Comand Busy Flag */
|
||||
#define SAR_STAT_CMDBZ 0x00000200 /* ABR SAR Command Busy Flag */
|
||||
#define SAR_STAT_FBQ3A 0x00000100 /* Free Buffer Queue 3 Attention */
|
||||
#define SAR_STAT_FBQ2A 0x00000080 /* Free Buffer Queue 2 Attention */
|
||||
#define SAR_STAT_RSQF 0x00000040 /* Receive Status Queue full */
|
||||
|
|
|
|||
|
|
@ -2089,7 +2089,7 @@ static int tx_init(struct atm_dev *dev)
|
|||
- ABR Table size is 2K
|
||||
- ABR wait queue is 2K
|
||||
since the table and wait queues are contiguous, all the bytes
|
||||
can be intialized by one memeset.
|
||||
can be initialized by one memeset.
|
||||
*/
|
||||
i = ABR_SCHED_TABLE * iadev->memSize;
|
||||
writew((i >> 11) & 0xffff, iadev->seg_reg+ABR_SBPTR_BASE);
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
*
|
||||
*
|
||||
* The driver model core calls device_pm_add() when a device is registered.
|
||||
* This will intialize the embedded device_pm_info object in the device
|
||||
* This will initialize the embedded device_pm_info object in the device
|
||||
* and add it to the list of power-controlled devices. sysfs entries for
|
||||
* controlling device power management will also be added.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -1060,8 +1060,8 @@ static irqreturn_t intel_mid_dma_interrupt2(int irq, void *data)
|
|||
* mid_setup_dma - Setup the DMA controller
|
||||
* @pdev: Controller PCI device structure
|
||||
*
|
||||
* Initilize the DMA controller, channels, registers with DMA engine,
|
||||
* ISR. Initilize DMA controller channels.
|
||||
* Initialize the DMA controller, channels, registers with DMA engine,
|
||||
* ISR. Initialize DMA controller channels.
|
||||
*/
|
||||
static int mid_setup_dma(struct pci_dev *pdev)
|
||||
{
|
||||
|
|
@ -1219,7 +1219,7 @@ static void middma_shutdown(struct pci_dev *pdev)
|
|||
* @pdev: Controller PCI device structure
|
||||
* @id: pci device id structure
|
||||
*
|
||||
* Initilize the PCI device, map BARs, query driver data.
|
||||
* Initialize the PCI device, map BARs, query driver data.
|
||||
* Call setup_dma to complete contoller and chan initilzation
|
||||
*/
|
||||
static int __devinit intel_mid_dma_probe(struct pci_dev *pdev,
|
||||
|
|
|
|||
|
|
@ -99,7 +99,7 @@ struct amd8131_dev_info {
|
|||
|
||||
/*
|
||||
* AMD8131 chipset has two pairs of PCIX Bridge and related IOAPIC
|
||||
* Controler, and ATCA-6101 has two AMD8131 chipsets, so there are
|
||||
* Controller, and ATCA-6101 has two AMD8131 chipsets, so there are
|
||||
* four PCIX Bridges on ATCA-6101 altogether.
|
||||
*
|
||||
* These PCIX Bridges share the same PCI Device ID and are all of
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ static void cell_edac_count_ce(struct mem_ctl_info *mci, int chan, u64 ar)
|
|||
offset = address & ~PAGE_MASK;
|
||||
syndrome = (ar & 0x000000001fe00000ul) >> 21;
|
||||
|
||||
/* TODO: Decoding of the error addresss */
|
||||
/* TODO: Decoding of the error address */
|
||||
edac_mc_handle_ce(mci, csrow->first_page + pfn, offset,
|
||||
syndrome, 0, chan, "");
|
||||
}
|
||||
|
|
@ -68,7 +68,7 @@ static void cell_edac_count_ue(struct mem_ctl_info *mci, int chan, u64 ar)
|
|||
pfn = address >> PAGE_SHIFT;
|
||||
offset = address & ~PAGE_MASK;
|
||||
|
||||
/* TODO: Decoding of the error addresss */
|
||||
/* TODO: Decoding of the error address */
|
||||
edac_mc_handle_ue(mci, csrow->first_page + pfn, offset, 0, "");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -258,7 +258,7 @@ enum scrub_type {
|
|||
* for single channel are 64 bits, for dual channel 128
|
||||
* bits.
|
||||
*
|
||||
* Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
|
||||
* Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
|
||||
* Motherboards commonly drive two chip-select pins to
|
||||
* a memory stick. A single-ranked stick, will occupy
|
||||
* only one of those rows. The other will be unused.
|
||||
|
|
|
|||
|
|
@ -873,7 +873,7 @@ ppc4xx_edac_get_mtype(u32 mcopt1)
|
|||
}
|
||||
|
||||
/**
|
||||
* ppc4xx_edac_init_csrows - intialize driver instance rows
|
||||
* ppc4xx_edac_init_csrows - initialize driver instance rows
|
||||
* @mci: A pointer to the EDAC memory controller instance
|
||||
* associated with the ibm,sdram-4xx-ddr2 controller for which
|
||||
* the csrows (i.e. banks/ranks) are being initialized.
|
||||
|
|
@ -881,7 +881,7 @@ ppc4xx_edac_get_mtype(u32 mcopt1)
|
|||
* currently set for the controller, from which bank width
|
||||
* and memory typ information is derived.
|
||||
*
|
||||
* This routine intializes the virtual "chip select rows" associated
|
||||
* This routine initializes the virtual "chip select rows" associated
|
||||
* with the EDAC memory controller instance. An ibm,sdram-4xx-ddr2
|
||||
* controller bank/rank is mapped to a row.
|
||||
*
|
||||
|
|
@ -992,7 +992,7 @@ ppc4xx_edac_init_csrows(struct mem_ctl_info *mci, u32 mcopt1)
|
|||
}
|
||||
|
||||
/**
|
||||
* ppc4xx_edac_mc_init - intialize driver instance
|
||||
* ppc4xx_edac_mc_init - initialize driver instance
|
||||
* @mci: A pointer to the EDAC memory controller instance being
|
||||
* initialized.
|
||||
* @op: A pointer to the OpenFirmware device tree node associated
|
||||
|
|
|
|||
|
|
@ -1314,7 +1314,7 @@ typedef struct _GET_ENGINE_CLOCK_PARAMETERS
|
|||
typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
|
||||
{
|
||||
USHORT usPrescale; //Ratio between Engine clock and I2C clock
|
||||
USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID
|
||||
USHORT usVRAMAddress; //Address in Frame Buffer where to pace raw EDID
|
||||
USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status
|
||||
//WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte
|
||||
UCHAR ucSlaveAddr; //Read from which slave
|
||||
|
|
|
|||
|
|
@ -434,7 +434,7 @@ static int read_i2c(struct nmk_i2c_dev *dev)
|
|||
}
|
||||
|
||||
if (timeout == 0) {
|
||||
/* controler has timedout, re-init the h/w */
|
||||
/* controller has timedout, re-init the h/w */
|
||||
dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
|
||||
(void) init_hw(dev);
|
||||
status = -ETIMEDOUT;
|
||||
|
|
@ -498,7 +498,7 @@ static int write_i2c(struct nmk_i2c_dev *dev)
|
|||
}
|
||||
|
||||
if (timeout == 0) {
|
||||
/* controler has timedout, re-init the h/w */
|
||||
/* controller has timedout, re-init the h/w */
|
||||
dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
|
||||
(void) init_hw(dev);
|
||||
status = -ETIMEDOUT;
|
||||
|
|
|
|||
|
|
@ -689,7 +689,7 @@ struct t3_swrq {
|
|||
* A T3 WQ implements both the SQ and RQ.
|
||||
*/
|
||||
struct t3_wq {
|
||||
union t3_wr *queue; /* DMA accessable memory */
|
||||
union t3_wr *queue; /* DMA accessible memory */
|
||||
dma_addr_t dma_addr; /* DMA address for HW */
|
||||
DEFINE_DMA_UNMAP_ADDR(mapping); /* unmap kruft */
|
||||
u32 error; /* 1 once we go to ERROR */
|
||||
|
|
|
|||
|
|
@ -314,7 +314,7 @@ MODULE_PARM_DESC(txselect, \
|
|||
#define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl)
|
||||
|
||||
/*
|
||||
* Per-context kernel registers. Acess only with qib_read_kreg_ctxt()
|
||||
* Per-context kernel registers. Access only with qib_read_kreg_ctxt()
|
||||
* or qib_write_kreg_ctxt()
|
||||
*/
|
||||
#define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0)
|
||||
|
|
|
|||
|
|
@ -610,7 +610,7 @@ config TOUCHSCREEN_USB_ZYTRONIC
|
|||
|
||||
config TOUCHSCREEN_USB_ETT_TC45USB
|
||||
default y
|
||||
bool "ET&T USB series TC4UM/TC5UH touchscreen controler support" if EMBEDDED
|
||||
bool "ET&T USB series TC4UM/TC5UH touchscreen controller support" if EMBEDDED
|
||||
depends on TOUCHSCREEN_USB_COMPOSITE
|
||||
|
||||
config TOUCHSCREEN_USB_NEXIO
|
||||
|
|
|
|||
|
|
@ -2318,7 +2318,7 @@ static int gigaset_probe(struct usb_interface *interface,
|
|||
__func__, le16_to_cpu(udev->descriptor.idVendor),
|
||||
le16_to_cpu(udev->descriptor.idProduct));
|
||||
|
||||
/* allocate memory for our device state and intialize it */
|
||||
/* allocate memory for our device state and initialize it */
|
||||
cs = gigaset_initcs(driver, BAS_CHANNELS, 0, 0, cidmode,
|
||||
GIGASET_MODULENAME);
|
||||
if (!cs)
|
||||
|
|
@ -2576,7 +2576,7 @@ static int __init bas_gigaset_init(void)
|
|||
{
|
||||
int result;
|
||||
|
||||
/* allocate memory for our driver state and intialize it */
|
||||
/* allocate memory for our driver state and initialize it */
|
||||
driver = gigaset_initdriver(GIGASET_MINOR, GIGASET_MINORS,
|
||||
GIGASET_MODULENAME, GIGASET_DEVNAME,
|
||||
&gigops, THIS_MODULE);
|
||||
|
|
|
|||
|
|
@ -513,7 +513,7 @@ gigaset_tty_open(struct tty_struct *tty)
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* allocate memory for our device state and intialize it */
|
||||
/* allocate memory for our device state and initialize it */
|
||||
cs = gigaset_initcs(driver, 1, 1, 0, cidmode, GIGASET_MODULENAME);
|
||||
if (!cs)
|
||||
goto error;
|
||||
|
|
@ -771,7 +771,7 @@ static int __init ser_gigaset_init(void)
|
|||
return rc;
|
||||
}
|
||||
|
||||
/* allocate memory for our driver state and intialize it */
|
||||
/* allocate memory for our driver state and initialize it */
|
||||
driver = gigaset_initdriver(GIGASET_MINOR, GIGASET_MINORS,
|
||||
GIGASET_MODULENAME, GIGASET_DEVNAME,
|
||||
&ops, THIS_MODULE);
|
||||
|
|
|
|||
|
|
@ -695,7 +695,7 @@ static int gigaset_probe(struct usb_interface *interface,
|
|||
|
||||
dev_info(&udev->dev, "%s: Device matched ... !\n", __func__);
|
||||
|
||||
/* allocate memory for our device state and intialize it */
|
||||
/* allocate memory for our device state and initialize it */
|
||||
cs = gigaset_initcs(driver, 1, 1, 0, cidmode, GIGASET_MODULENAME);
|
||||
if (!cs)
|
||||
return -ENODEV;
|
||||
|
|
@ -894,7 +894,7 @@ static int __init usb_gigaset_init(void)
|
|||
{
|
||||
int result;
|
||||
|
||||
/* allocate memory for our driver state and intialize it */
|
||||
/* allocate memory for our driver state and initialize it */
|
||||
driver = gigaset_initdriver(GIGASET_MINOR, GIGASET_MINORS,
|
||||
GIGASET_MODULENAME, GIGASET_DEVNAME,
|
||||
&ops, THIS_MODULE);
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ struct isac_hw {
|
|||
u32 type;
|
||||
u32 off; /* offset to isac regs */
|
||||
char *name;
|
||||
spinlock_t *hwlock; /* lock HW acccess */
|
||||
spinlock_t *hwlock; /* lock HW access */
|
||||
read_reg_func *read_reg;
|
||||
write_reg_func *write_reg;
|
||||
fifo_func *read_fifo;
|
||||
|
|
@ -70,7 +70,7 @@ struct ipac_hw {
|
|||
struct hscx_hw hscx[2];
|
||||
char *name;
|
||||
void *hw;
|
||||
spinlock_t *hwlock; /* lock HW acccess */
|
||||
spinlock_t *hwlock; /* lock HW access */
|
||||
struct module *owner;
|
||||
u32 type;
|
||||
read_reg_func *read_reg;
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ struct isar_ch {
|
|||
struct isar_hw {
|
||||
struct isar_ch ch[2];
|
||||
void *hw;
|
||||
spinlock_t *hwlock; /* lock HW acccess */
|
||||
spinlock_t *hwlock; /* lock HW access */
|
||||
char *name;
|
||||
struct module *owner;
|
||||
read_reg_func *read_reg;
|
||||
|
|
|
|||
|
|
@ -1427,8 +1427,8 @@ modeisar(struct BCState *bcs, int mode, int bc)
|
|||
&bcs->hw.isar.reg->Flags))
|
||||
bcs->hw.isar.dpath = 1;
|
||||
else {
|
||||
printk(KERN_WARNING"isar modeisar analog funktions only with DP1\n");
|
||||
debugl1(cs, "isar modeisar analog funktions only with DP1");
|
||||
printk(KERN_WARNING"isar modeisar analog functions only with DP1\n");
|
||||
debugl1(cs, "isar modeisar analog functions only with DP1");
|
||||
return(1);
|
||||
}
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -261,7 +261,7 @@ static u16 ns_to_pulse_width_count(u32 ns, u16 divider)
|
|||
u32 rem;
|
||||
|
||||
/*
|
||||
* The 2 lsb's of the pulse width timer count are not accessable, hence
|
||||
* The 2 lsb's of the pulse width timer count are not accessible, hence
|
||||
* the (1 << 2)
|
||||
*/
|
||||
n = ((u64) ns) * CX25840_IR_REFCLK_FREQ / 1000000; /* millicycles */
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ extern spinlock_t vpif_lock;
|
|||
#define regr(reg) readl((reg) + vpif_base)
|
||||
#define regw(value, reg) writel(value, (reg + vpif_base))
|
||||
|
||||
/* Register Addresss Offsets */
|
||||
/* Register Address Offsets */
|
||||
#define VPIF_PID (0x0000)
|
||||
#define VPIF_CH0_CTRL (0x0004)
|
||||
#define VPIF_CH1_CTRL (0x0008)
|
||||
|
|
|
|||
|
|
@ -85,7 +85,7 @@ enum vpss_platform_type {
|
|||
/*
|
||||
* vpss operations. Depends on platform. Not all functions are available
|
||||
* on all platforms. The api, first check if a functio is available before
|
||||
* invoking it. In the probe, the function ptrs are intialized based on
|
||||
* invoking it. In the probe, the function ptrs are initialized based on
|
||||
* vpss name. vpss name can be "dm355_vpss", "dm644x_vpss" etc.
|
||||
*/
|
||||
struct vpss_hw_ops {
|
||||
|
|
|
|||
|
|
@ -1286,7 +1286,7 @@ static int omap_vout_release(struct file *file)
|
|||
videobuf_mmap_free(q);
|
||||
|
||||
/* Even if apply changes fails we should continue
|
||||
freeing allocated memeory */
|
||||
freeing allocated memory */
|
||||
if (vout->streaming) {
|
||||
u32 mask = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -653,8 +653,8 @@ static irqreturn_t saa7164_irq(int irq, void *dev_id)
|
|||
goto out;
|
||||
}
|
||||
|
||||
/* Check that the hardware is accessable. If the status bytes are
|
||||
* 0xFF then the device is not accessable, the the IRQ belongs
|
||||
/* Check that the hardware is accessible. If the status bytes are
|
||||
* 0xFF then the device is not accessible, the the IRQ belongs
|
||||
* to another driver.
|
||||
* 4 x u32 interrupt registers.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -147,7 +147,7 @@ enum sn9c102_i2c_interface {
|
|||
|
||||
struct sn9c102_sensor {
|
||||
char name[32], /* sensor name */
|
||||
maintainer[64]; /* name of the mantainer <email> */
|
||||
maintainer[64]; /* name of the maintainer <email> */
|
||||
|
||||
enum sn9c102_bridge supported_bridge; /* supported SN9C1xx bridges */
|
||||
|
||||
|
|
|
|||
|
|
@ -95,7 +95,7 @@ struct zoran_params {
|
|||
|
||||
int quality; /* Measure for quality of compressed images.
|
||||
* Scales linearly with the size of the compressed images.
|
||||
* Must be beetween 0 and 100, 100 is a compression
|
||||
* Must be between 0 and 100, 100 is a compression
|
||||
* ratio of 1:4 */
|
||||
|
||||
int odd_even; /* Which field should come first ??? */
|
||||
|
|
|
|||
|
|
@ -268,7 +268,7 @@
|
|||
|
||||
/* Compatibility Error : IR Disabled */
|
||||
#define IR_LOGINFO_COMPAT_ERROR_RAID_DISABLED (0x00010030)
|
||||
/* Compatibility Error : Inquiry Comand failed */
|
||||
/* Compatibility Error : Inquiry Command failed */
|
||||
#define IR_LOGINFO_COMPAT_ERROR_INQUIRY_FAILED (0x00010031)
|
||||
/* Compatibility Error : Device not direct access device */
|
||||
#define IR_LOGINFO_COMPAT_ERROR_NOT_DIRECT_ACCESS (0x00010032)
|
||||
|
|
|
|||
|
|
@ -7977,7 +7977,7 @@ mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info)
|
|||
NULL, /* 2Eh */
|
||||
NULL, /* 2Fh */
|
||||
"Compatibility Error: IR Disabled", /* 30h */
|
||||
"Compatibility Error: Inquiry Comand Failed", /* 31h */
|
||||
"Compatibility Error: Inquiry Command Failed", /* 31h */
|
||||
"Compatibility Error: Device not Direct Access "
|
||||
"Device ", /* 32h */
|
||||
"Compatibility Error: Removable Device Found", /* 33h */
|
||||
|
|
|
|||
|
|
@ -1146,7 +1146,7 @@ mptsas_target_reset_queue(MPT_ADAPTER *ioc,
|
|||
*
|
||||
* This function will delete scheduled target reset from the list and
|
||||
* try to send next target reset. This will be called from completion
|
||||
* context of any Task managment command.
|
||||
* context of any Task management command.
|
||||
*/
|
||||
|
||||
void
|
||||
|
|
|
|||
|
|
@ -309,7 +309,7 @@ static inline void i2o_block_request_free(struct i2o_block_request *ireq)
|
|||
* @ireq: I2O block request
|
||||
* @mptr: message body pointer
|
||||
*
|
||||
* Builds the SG list and map it to be accessable by the controller.
|
||||
* Builds the SG list and map it to be accessible by the controller.
|
||||
*
|
||||
* Returns 0 on failure or 1 on success.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -313,7 +313,7 @@ static int __init charlcd_probe(struct platform_device *pdev)
|
|||
INIT_DELAYED_WORK(&lcd->init_work, charlcd_init_work);
|
||||
schedule_delayed_work(&lcd->init_work, 0);
|
||||
|
||||
dev_info(&pdev->dev, "initalized ARM character LCD at %08x\n",
|
||||
dev_info(&pdev->dev, "initialized ARM character LCD at %08x\n",
|
||||
lcd->phybase);
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -257,7 +257,7 @@ static u32 get_card_status(struct mmc_card *card, struct request *req)
|
|||
cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
|
||||
err = mmc_wait_for_cmd(card->host, &cmd, 0);
|
||||
if (err)
|
||||
printk(KERN_ERR "%s: error %d sending status comand",
|
||||
printk(KERN_ERR "%s: error %d sending status command",
|
||||
req->rq_disk->disk_name, err);
|
||||
return cmd.resp[0];
|
||||
}
|
||||
|
|
|
|||
|
|
@ -462,7 +462,7 @@ config MMC_SH_MMCIF
|
|||
tristate "SuperH Internal MMCIF support"
|
||||
depends on MMC_BLOCK && (SUPERH || ARCH_SHMOBILE)
|
||||
help
|
||||
This selects the MMC Host Interface controler (MMCIF).
|
||||
This selects the MMC Host Interface controller (MMCIF).
|
||||
|
||||
This driver supports MMCIF in sh7724/sh7757/sh7372.
|
||||
|
||||
|
|
|
|||
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Reference in a new issue