Patches for MSM core
These patches are changes to the MSM timer code that will be for upcoming targets, including a generalization of the binding and preventing a missing timer interrupt. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAABAgAGBQJRaInuAAoJEOa6n1xeVN+CP5oP/3HMkT/Ihqcm85H9SXSG9M9d 1LY2Nu6wWoSZk5qbBc8zAEFaoP3WDOJ/zgonXRFxOa59x5ZopEyw2xzQ5HO7+vHe umH9uGA644rrTysSsx1Zox1H6AskxKTzPXTrDeTXH1W4s3Rmsqzg+08Ie72WTKJn UROFI/zv1HS6G8Eq33fpbsq4juZtbqTJLiIDICDB3x1pEXh96MZTgC6LXuU6RTHh ORN7QNf8LjaNU1lZdRdYXsdO8CIb51Ur2OKNG8G+L711Khr4fdwIEEFQUH4CS9Mq RXPY47h+rwc4q7KHzEpF3rRITDDJnq5nbazEpSMFKq8ACr6fH6u5zUr0nknIWAL+ cYZMu6axuYLCMe4QCEf2xuASdggsHiXnq8MWJCsrx4h4VWKq9TcsfZkytdZu5epi M9RY2c1VfcCFEIsBhb/s00ZRZkZaQq8S9wvbt431bSHBlvsGp9Ofqxj2siYcmMC+ ozE6ClI4IQMB+iBdk3MNV0sK8Boj0ywo/2KgnfCGJ+f+LcuAhQMScvOY4JPjMxpZ 8RcfZzg49mbN7hV4+IHJWW9Nfo6mPlw4k3vavx6kcChYQeQiGANO0kg+2ldagDIE blxh0PxXSgpkB91Epova/tGPXncGPgG2k9eOrZ3pmZtmBL4215Axlx2zjc8elFeG /pEkYdZqddjwVm8ryHWQ =SbqQ -----END PGP SIGNATURE----- Merge tag 'msm-core-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm into next/soc From David Brown: Patches for MSM core These patches are changes to the MSM timer code that will be for upcoming targets, including a generalization of the binding and preventing a missing timer interrupt. * tag 'msm-core-3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm: ARM: msm: Wait for timer clear to complete ARM: msm: Rework timer binding to be more general Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
b56a7f9206
4 changed files with 86 additions and 107 deletions
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@ -3,36 +3,35 @@
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Properties:
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- compatible : Should at least contain "qcom,msm-timer". More specific
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properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general
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purpose timer and a debug timer respectively.
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properties specify which subsystem the timers are paired with.
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- interrupts : Interrupt indicating a match event.
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"qcom,kpss-timer" - krait subsystem
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"qcom,scss-timer" - scorpion subsystem
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- reg : Specifies the base address of the timer registers. The second region
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specifies an optional register used to configure the clock divider.
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- interrupts : Interrupts for the the debug timer, the first general purpose
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timer, and optionally a second general purpose timer in that
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order.
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- clock-frequency : The frequency of the timer in Hz.
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- reg : Specifies the base address of the timer registers.
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- clock-frequency : The frequency of the debug timer and the general purpose
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timer(s) in Hz in that order.
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Optional:
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- cpu-offset : per-cpu offset used when the timer is accessed without the
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CPU remapping facilities. The offset is cpu-offset * cpu-nr.
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CPU remapping facilities. The offset is
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cpu-offset + (0x10000 * cpu-nr).
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Example:
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timer@200a004 {
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compatible = "qcom,msm-gpt", "qcom,msm-timer";
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interrupts = <1 2 0x301>;
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reg = <0x0200a004 0x10>;
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clock-frequency = <32768>;
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cpu-offset = <0x40000>;
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};
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timer@200a024 {
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compatible = "qcom,msm-dgt", "qcom,msm-timer";
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interrupts = <1 3 0x301>;
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reg = <0x0200a024 0x10>,
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<0x0200a034 0x4>;
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clock-frequency = <6750000>;
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timer@200a000 {
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compatible = "qcom,scss-timer", "qcom,msm-timer";
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interrupts = <1 1 0x301>,
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<1 2 0x301>,
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<1 3 0x301>;
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reg = <0x0200a000 0x100>;
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clock-frequency = <19200000>,
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<32768>;
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cpu-offset = <0x40000>;
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};
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@ -16,19 +16,13 @@
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};
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timer@2000004 {
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compatible = "qcom,msm-gpt", "qcom,msm-timer";
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interrupts = <1 1 0x301>;
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reg = <0x02000004 0x10>;
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clock-frequency = <32768>;
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cpu-offset = <0x40000>;
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};
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timer@2000024 {
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compatible = "qcom,msm-dgt", "qcom,msm-timer";
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interrupts = <1 0 0x301>;
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reg = <0x02000024 0x10>,
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<0x02000034 0x4>;
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clock-frequency = <6750000>;
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compatible = "qcom,scss-timer", "qcom,msm-timer";
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interrupts = <1 0 0x301>,
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<1 1 0x301>,
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<1 2 0x301>;
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reg = <0x02000000 0x100>;
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clock-frequency = <27000000>,
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<32768>;
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cpu-offset = <0x40000>;
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};
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@ -15,20 +15,14 @@
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< 0x02002000 0x1000 >;
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};
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timer@200a004 {
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compatible = "qcom,msm-gpt", "qcom,msm-timer";
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interrupts = <1 2 0x301>;
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reg = <0x0200a004 0x10>;
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clock-frequency = <32768>;
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cpu-offset = <0x80000>;
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};
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timer@200a024 {
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compatible = "qcom,msm-dgt", "qcom,msm-timer";
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interrupts = <1 1 0x301>;
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reg = <0x0200a024 0x10>,
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<0x0200a034 0x4>;
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clock-frequency = <6750000>;
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timer@200a000 {
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compatible = "qcom,kpss-timer", "qcom,msm-timer";
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interrupts = <1 1 0x301>,
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<1 2 0x301>,
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<1 3 0x301>;
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reg = <0x0200a000 0x100>;
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clock-frequency = <27000000>,
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<32768>;
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cpu-offset = <0x80000>;
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};
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@ -30,19 +30,22 @@
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#include "common.h"
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#define TIMER_MATCH_VAL 0x0000
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#define TIMER_COUNT_VAL 0x0004
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#define TIMER_ENABLE 0x0008
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#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
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#define TIMER_ENABLE_EN BIT(0)
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#define TIMER_CLEAR 0x000C
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#define DGT_CLK_CTL_DIV_4 0x3
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#define TIMER_MATCH_VAL 0x0000
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#define TIMER_COUNT_VAL 0x0004
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#define TIMER_ENABLE 0x0008
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#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
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#define TIMER_ENABLE_EN BIT(0)
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#define TIMER_CLEAR 0x000C
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#define DGT_CLK_CTL 0x10
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#define DGT_CLK_CTL_DIV_4 0x3
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#define TIMER_STS_GPT0_CLR_PEND BIT(10)
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#define GPT_HZ 32768
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#define MSM_DGT_SHIFT 5
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static void __iomem *event_base;
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static void __iomem *sts_base;
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static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
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{
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@ -67,6 +70,11 @@ static int msm_timer_set_next_event(unsigned long cycles,
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writel_relaxed(ctrl, event_base + TIMER_CLEAR);
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writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
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if (sts_base)
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while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
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cpu_relax();
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writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
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return 0;
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}
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@ -137,9 +145,6 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
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if (!smp_processor_id())
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return 0;
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writel_relaxed(0, event_base + TIMER_ENABLE);
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writel_relaxed(0, event_base + TIMER_CLEAR);
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writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
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evt->irq = msm_clockevent.irq;
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evt->name = "local_timer";
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evt->features = msm_clockevent.features;
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@ -177,9 +182,6 @@ static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
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struct clocksource *cs = &msm_clocksource;
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int res;
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writel_relaxed(0, event_base + TIMER_ENABLE);
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writel_relaxed(0, event_base + TIMER_CLEAR);
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writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
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ce->cpumask = cpumask_of(0);
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ce->irq = irq;
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@ -217,13 +219,9 @@ static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
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}
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#ifdef CONFIG_OF
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static const struct of_device_id msm_dgt_match[] __initconst = {
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{ .compatible = "qcom,msm-dgt" },
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{ },
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};
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static const struct of_device_id msm_gpt_match[] __initconst = {
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{ .compatible = "qcom,msm-gpt" },
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static const struct of_device_id msm_timer_match[] __initconst = {
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{ .compatible = "qcom,kpss-timer" },
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{ .compatible = "qcom,scss-timer" },
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{ },
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};
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@ -234,33 +232,29 @@ void __init msm_dt_timer_init(void)
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int irq;
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struct resource res;
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u32 percpu_offset;
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void __iomem *dgt_clk_ctl;
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void __iomem *base;
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void __iomem *cpu0_base;
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np = of_find_matching_node(NULL, msm_gpt_match);
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np = of_find_matching_node(NULL, msm_timer_match);
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if (!np) {
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pr_err("Can't find GPT DT node\n");
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pr_err("Can't find msm timer DT node\n");
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return;
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}
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event_base = of_iomap(np, 0);
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if (!event_base) {
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base = of_iomap(np, 0);
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if (!base) {
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pr_err("Failed to map event base\n");
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return;
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}
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irq = irq_of_parse_and_map(np, 0);
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/* We use GPT0 for the clockevent */
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irq = irq_of_parse_and_map(np, 1);
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if (irq <= 0) {
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pr_err("Can't get irq\n");
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return;
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}
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of_node_put(np);
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np = of_find_matching_node(NULL, msm_dgt_match);
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if (!np) {
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pr_err("Can't find DGT DT node\n");
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return;
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}
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/* We use CPU0's DGT for the clocksource */
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if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
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percpu_offset = 0;
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@ -269,45 +263,43 @@ void __init msm_dt_timer_init(void)
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return;
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}
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source_base = ioremap(res.start + percpu_offset, resource_size(&res));
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if (!source_base) {
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cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
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if (!cpu0_base) {
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pr_err("Failed to map source base\n");
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return;
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}
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if (!of_address_to_resource(np, 1, &res)) {
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dgt_clk_ctl = ioremap(res.start + percpu_offset,
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resource_size(&res));
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if (!dgt_clk_ctl) {
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pr_err("Failed to map DGT control base\n");
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return;
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}
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writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl);
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iounmap(dgt_clk_ctl);
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}
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if (of_property_read_u32(np, "clock-frequency", &freq)) {
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pr_err("Unknown frequency\n");
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return;
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}
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of_node_put(np);
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event_base = base + 0x4;
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sts_base = base + 0x88;
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source_base = cpu0_base + 0x24;
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freq /= 4;
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writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
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msm_timer_init(freq, 32, irq, !!percpu_offset);
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}
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#endif
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static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
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static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
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u32 sts)
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{
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event_base = ioremap(event, SZ_64);
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if (!event_base) {
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pr_err("Failed to map event base\n");
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return 1;
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}
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source_base = ioremap(source, SZ_64);
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if (!source_base) {
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pr_err("Failed to map source base\n");
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return 1;
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void __iomem *base;
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base = ioremap(addr, SZ_256);
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if (!base) {
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pr_err("Failed to map timer base\n");
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return -ENOMEM;
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}
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event_base = base + event;
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source_base = base + source;
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if (sts)
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sts_base = base + sts;
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return 0;
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}
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@ -315,7 +307,7 @@ void __init msm7x01_timer_init(void)
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{
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struct clocksource *cs = &msm_clocksource;
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if (msm_timer_map(0xc0100000, 0xc0100010))
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if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
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return;
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cs->read = msm_read_timer_count_shift;
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cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
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@ -326,14 +318,14 @@ void __init msm7x01_timer_init(void)
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void __init msm7x30_timer_init(void)
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{
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if (msm_timer_map(0xc0100004, 0xc0100024))
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if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
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return;
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msm_timer_init(24576000 / 4, 32, 1, false);
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}
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void __init qsd8x50_timer_init(void)
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{
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if (msm_timer_map(0xAC100000, 0xAC100010))
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if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
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return;
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msm_timer_init(19200000 / 4, 32, 7, false);
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}
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