mmc: sd: add support for tuning during uhs initialization
Host Controller needs tuning during initialization to operate SDR50 and SDR104 UHS-I cards. Whether SDR50 mode actually needs tuning is indicated by bit 45 of the Host Controller Capabilities register. A new command CMD19 has been defined in the Physical Layer spec v3.01 to request the card to send tuning pattern. We enable Buffer Read Ready interrupt at the very begining of tuning procedure, because that is the only interrupt generated by the Host Controller during tuning. We program the block size to 64 in the Block Size register. We make sure that DMA Enable and Multi Block Select in the Transfer Mode register are set to 0 before actually sending CMD19. The tuning block is sent by the card to the Host Controller using DAT lines, so we set Data Present Select (bit 5) in the Command register. The Host Controller is responsible for doing the verfication of tuning block sent by the card at the hardware level. After sending CMD19, we wait for Buffer Read Ready interrupt. In case we don't receive an interrupt after the specified timeout value, we fall back on fixed sampling clock by setting Execute Tuning (bit 6) and Sampling Clock Select (bit 7) of Host Control2 register to 0. Before exiting the tuning procedure, we disable Buffer Read Ready interrupt and re-enable other interrupts. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
This commit is contained in:
Arindam Nath
Chris Ball
parent
3a30351143
commit
b513ea250e
6 changed files with 182 additions and 1 deletions
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@ -618,6 +618,12 @@ static int mmc_sd_init_uhs_card(struct mmc_card *card)
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/* Set current limit for the card */
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err = sd_set_current_limit(card, status);
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if (err)
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goto out;
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/* SPI mode doesn't define CMD19 */
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if (!mmc_host_is_spi(card->host) && card->host->ops->execute_tuning)
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err = card->host->ops->execute_tuning(card->host);
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out:
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kfree(status);
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@ -38,6 +38,8 @@
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#define SDHCI_USE_LEDS_CLASS
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#endif
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#define MAX_TUNING_LOOP 40
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static unsigned int debug_quirks = 0;
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static void sdhci_finish_data(struct sdhci_host *);
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@ -968,7 +970,9 @@ static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
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flags |= SDHCI_CMD_CRC;
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if (cmd->flags & MMC_RSP_OPCODE)
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flags |= SDHCI_CMD_INDEX;
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if (cmd->data)
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/* CMD19 is special in that the Data Present Select should be set */
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if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
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flags |= SDHCI_CMD_DATA;
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sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
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@ -1501,12 +1505,157 @@ static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
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return 0;
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}
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static int sdhci_execute_tuning(struct mmc_host *mmc)
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{
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struct sdhci_host *host;
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u16 ctrl;
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u32 ier;
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int tuning_loop_counter = MAX_TUNING_LOOP;
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unsigned long timeout;
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int err = 0;
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host = mmc_priv(mmc);
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disable_irq(host->irq);
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spin_lock(&host->lock);
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ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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/*
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* Host Controller needs tuning only in case of SDR104 mode
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* and for SDR50 mode when Use Tuning for SDR50 is set in
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* Capabilities register.
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*/
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if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
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(((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
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(host->flags & SDHCI_SDR50_NEEDS_TUNING)))
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ctrl |= SDHCI_CTRL_EXEC_TUNING;
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else {
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spin_unlock(&host->lock);
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enable_irq(host->irq);
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return 0;
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}
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sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
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/*
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* As per the Host Controller spec v3.00, tuning command
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* generates Buffer Read Ready interrupt, so enable that.
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*
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* Note: The spec clearly says that when tuning sequence
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* is being performed, the controller does not generate
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* interrupts other than Buffer Read Ready interrupt. But
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* to make sure we don't hit a controller bug, we _only_
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* enable Buffer Read Ready interrupt here.
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*/
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ier = sdhci_readl(host, SDHCI_INT_ENABLE);
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sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
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/*
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* Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
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* of loops reaches 40 times or a timeout of 150ms occurs.
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*/
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timeout = 150;
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do {
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struct mmc_command cmd = {0};
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struct mmc_request mrq = {0};
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if (!tuning_loop_counter && !timeout)
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break;
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cmd.opcode = MMC_SEND_TUNING_BLOCK;
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cmd.arg = 0;
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cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
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cmd.retries = 0;
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cmd.data = NULL;
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cmd.error = 0;
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mrq.cmd = &cmd;
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host->mrq = &mrq;
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/*
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* In response to CMD19, the card sends 64 bytes of tuning
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* block to the Host Controller. So we set the block size
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* to 64 here.
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*/
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sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
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/*
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* The tuning block is sent by the card to the host controller.
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* So we set the TRNS_READ bit in the Transfer Mode register.
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* This also takes care of setting DMA Enable and Multi Block
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* Select in the same register to 0.
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*/
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sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
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sdhci_send_command(host, &cmd);
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host->cmd = NULL;
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host->mrq = NULL;
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spin_unlock(&host->lock);
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enable_irq(host->irq);
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/* Wait for Buffer Read Ready interrupt */
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wait_event_interruptible_timeout(host->buf_ready_int,
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(host->tuning_done == 1),
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msecs_to_jiffies(50));
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disable_irq(host->irq);
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spin_lock(&host->lock);
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if (!host->tuning_done) {
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printk(KERN_INFO DRIVER_NAME ": Timeout waiting for "
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"Buffer Read Ready interrupt during tuning "
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"procedure, falling back to fixed sampling "
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"clock\n");
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ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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ctrl &= ~SDHCI_CTRL_TUNED_CLK;
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ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
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sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
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err = -EIO;
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goto out;
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}
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host->tuning_done = 0;
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ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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tuning_loop_counter--;
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timeout--;
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mdelay(1);
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} while (ctrl & SDHCI_CTRL_EXEC_TUNING);
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/*
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* The Host Driver has exhausted the maximum number of loops allowed,
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* so use fixed sampling frequency.
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*/
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if (!tuning_loop_counter || !timeout) {
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ctrl &= ~SDHCI_CTRL_TUNED_CLK;
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sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
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} else {
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if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
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printk(KERN_INFO DRIVER_NAME ": Tuning procedure"
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" failed, falling back to fixed sampling"
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" clock\n");
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err = -EIO;
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}
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}
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out:
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sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
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spin_unlock(&host->lock);
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enable_irq(host->irq);
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return err;
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}
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static const struct mmc_host_ops sdhci_ops = {
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.request = sdhci_request,
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.set_ios = sdhci_set_ios,
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.get_ro = sdhci_get_ro,
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.enable_sdio_irq = sdhci_enable_sdio_irq,
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.start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
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.execute_tuning = sdhci_execute_tuning,
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};
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/*****************************************************************************\
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@ -1724,6 +1873,16 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
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{
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BUG_ON(intmask == 0);
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/* CMD19 generates _only_ Buffer Read Ready interrupt */
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if (intmask & SDHCI_INT_DATA_AVAIL) {
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if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
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MMC_SEND_TUNING_BLOCK) {
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host->tuning_done = 1;
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wake_up(&host->buf_ready_int);
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return;
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}
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}
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if (!host->data) {
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/*
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* The "data complete" interrupt is also used to
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@ -2160,6 +2319,10 @@ int sdhci_add_host(struct sdhci_host *host)
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if (caps[1] & SDHCI_SUPPORT_DDR50)
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mmc->caps |= MMC_CAP_UHS_DDR50;
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/* Does the host needs tuning for SDR50? */
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if (caps[1] & SDHCI_USE_SDR50_TUNING)
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host->flags |= SDHCI_SDR50_NEEDS_TUNING;
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/* Driver Type(s) (A, C, D) supported by the host */
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if (caps[1] & SDHCI_DRIVER_TYPE_A)
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mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
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@ -2313,6 +2476,9 @@ int sdhci_add_host(struct sdhci_host *host)
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setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
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if (host->version >= SDHCI_SPEC_300)
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init_waitqueue_head(&host->buf_ready_int);
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ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
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mmc_hostname(mmc), host);
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if (ret)
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@ -161,6 +161,8 @@
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#define SDHCI_CTRL_DRV_TYPE_A 0x0010
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#define SDHCI_CTRL_DRV_TYPE_C 0x0020
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#define SDHCI_CTRL_DRV_TYPE_D 0x0030
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#define SDHCI_CTRL_EXEC_TUNING 0x0040
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#define SDHCI_CTRL_TUNED_CLK 0x0080
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#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
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#define SDHCI_CAPABILITIES 0x40
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@ -188,6 +190,7 @@
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#define SDHCI_DRIVER_TYPE_A 0x00000010
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#define SDHCI_DRIVER_TYPE_C 0x00000020
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#define SDHCI_DRIVER_TYPE_D 0x00000040
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#define SDHCI_USE_SDR50_TUNING 0x00002000
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#define SDHCI_CAPABILITIES_1 0x44
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@ -136,6 +136,7 @@ struct mmc_host_ops {
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void (*init_card)(struct mmc_host *host, struct mmc_card *card);
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int (*start_signal_voltage_switch)(struct mmc_host *host, struct mmc_ios *ios);
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int (*execute_tuning)(struct mmc_host *host);
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};
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struct mmc_card;
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@ -50,6 +50,7 @@
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#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
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#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
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#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
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#define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */
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/* class 3 */
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#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
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@ -111,6 +111,7 @@ struct sdhci_host {
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#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
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#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
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#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
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#define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */
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unsigned int version; /* SDHCI spec. version */
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@ -147,6 +148,9 @@ struct sdhci_host {
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unsigned int ocr_avail_sd;
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unsigned int ocr_avail_mmc;
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wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
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unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
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unsigned long private[0] ____cacheline_aligned;
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};
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#endif /* __SDHCI_H */
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